[Devel] ACPI 5.0 implementation for armv7 and armv8 architecture

[Devel] ACPI 5.0 implementation for armv7 and armv8 architecture

[Ayan Halder]

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Hi,

I am planning to implement ACPI5.0 on an SOC having Cortex A5 and Atlas cpu( based on armv8 architecture) running linux on top of them.
As per the ACPI 5.0 hardware specification(Fixed Hardware/ Generic Hardware  model) of ACPI5.0, the processor needs to support various low power modes(C0, C1, C2, C3) and sleep states(S1, S2, S3, S4, S5) via register interfaces as well as OEM provided AML(ACPI Machine Language).
Therefore, which instructions in armv7 and armv8 put the processor into the afore-mentioned low power modes and sleep states?
( The arm instruction manual specifies "wfe" and "wfi" to put the processor in a sleep state, but I am not sure if this confirms to the ACPI 5.0 requirements )
Besides, does arm provide any AML(ACPI Machine Language) code to put the processor to low power modes? If not, then how do we create an ACPI machine language code for armv7 and armv8 architecture and do we have an AML interpreter for armv7 and armv8 architecture?

Regards,
Ayan Kumar Halder


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Re: [Devel] ACPI 5.0 implementation for armv7 and armv8 architecture

[@ 2012-12-03 3:37 UTC (permalink / raw)]

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Copying Andrew Sloss from ARM.

-          DW

From: devel-bounces(a)acpica.org [mailto:devel-bounces(a)acpica.org] On Behalf Of Ayan Halder
Sent: Sunday, December 02, 2012 5:30 AM
To: devel(a)acpica.org
Subject: [Devel] ACPI 5.0 implementation for armv7 and armv8 architecture

Hi,

I am planning to implement ACPI5.0 on an SOC having Cortex A5 and Atlas cpu( based on armv8 architecture) running linux on top of them.
As per the ACPI 5.0 hardware specification(Fixed Hardware/ Generic Hardware  model) of ACPI5.0, the processor needs to support various low power modes(C0, C1, C2, C3) and sleep states(S1, S2, S3, S4, S5) via register interfaces as well as OEM provided AML(ACPI Machine Language).
Therefore, which instructions in armv7 and armv8 put the processor into the afore-mentioned low power modes and sleep states?
( The arm instruction manual specifies “wfe” and “wfi” to put the processor in a sleep state, but I am not sure if this confirms to the ACPI 5.0 requirements )
Besides, does arm provide any AML(ACPI Machine Language) code to put the processor to low power modes? If not, then how do we create an ACPI machine language code for armv7 and armv8 architecture and do we have an AML interpreter for armv7 and armv8 architecture?

Regards,
Ayan Kumar Halder


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Re: [Devel] ACPI 5.0 implementation for armv7 and armv8 architecture

[Al Stone]

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I've only lurked on this list in the past, but this work sounds very
similar to work I've been tasked to take on for Linaro (please see
https://wiki.linaro.org/LEG for the context).  I'll be looking at
Cortex A9/A15 and ARMv8 for the same reasons so I'm thinking perhaps
we should coordinate our efforts here...

On 12/02/2012 08:37 PM, Wei, Dong (魏东 UEFI-ACPI) wrote:
> Copying Andrew Sloss from ARM.
>
> -DW
>
> *From:*devel-bounces(a)acpica.org [mailto:devel-bounces(a)acpica.org] *On
> Behalf Of *Ayan Halder
> *Sent:* Sunday, December 02, 2012 5:30 AM
> *To:* devel(a)acpica.org
> *Subject:* [Devel] ACPI 5.0 implementation for armv7 and armv8 architecture
>
> Hi,
>
> I am planning to implement ACPI5.0 on an SOC having Cortex A5 and Atlas
> cpu( based on armv8 architecture) running linux on top of them.
>
> As per the ACPI 5.0 hardware specification(Fixed Hardware/ Generic
> Hardware  model) of ACPI5.0, the processor needs to support various low
> power modes(C0, C1, C2, C3) and sleep states(S1, S2, S3, S4, S5) via
> register interfaces as well as OEM provided AML(ACPI Machine Language).
>
> Therefore, which instructions in armv7 and armv8 put the processor into
> the afore-mentioned low power modes and sleep states?
>
> ( The arm instruction manual specifies “wfe” and “wfi” to put the
> processor in a sleep state, but I am not sure if this confirms to the
> ACPI 5.0 requirements )
>
> Besides, does arm provide any AML(ACPI Machine Language) code to put the
> processor to low power modes? If not, then how do we create an ACPI
> machine language code for armv7 and armv8 architecture and do we have an
> AML interpreter for armv7 and armv8 architecture?
>
> Regards,
>
> Ayan Kumar Halder
>
>
>
> _______________________________________________
> Devel mailing list
> Devel(a)acpica.org
> http://lists.acpica.org/listinfo/devel
>


-- 
ciao,
al
-----------------------------------
Al Stone
Software Engineer
Red Hat, Inc.
ahs3(a)redhat.com
-----------------------------------

Re: [Devel] ACPI 5.0 implementation for armv7 and armv8 architecture

[@ 2012-12-18 0:00 UTC (permalink / raw)]

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Hi Al,

I fully agree. I was hoping Andrew could introduce Ayan to the LEG work:-)

- DW
- 
-----Original Message-----
From: Al Stone [mailto:ahs3(a)redhat.com] 
Sent: Monday, December 17, 2012 3:30 PM
To: Wei, Dong (魏东 UEFI-ACPI)
Cc: Ayan Halder; devel(a)acpica.org; Andrew N. Sloss
Subject: Re: [Devel] ACPI 5.0 implementation for armv7 and armv8 architecture

I've only lurked on this list in the past, but this work sounds very similar to work I've been tasked to take on for Linaro (please see https://wiki.linaro.org/LEG for the context).  I'll be looking at Cortex A9/A15 and ARMv8 for the same reasons so I'm thinking perhaps we should coordinate our efforts here...

On 12/02/2012 08:37 PM, Wei, Dong (魏东 UEFI-ACPI) wrote:
> Copying Andrew Sloss from ARM.
>
> -DW
>
> *From:*devel-bounces(a)acpica.org [mailto:devel-bounces(a)acpica.org] *On 
> Behalf Of *Ayan Halder
> *Sent:* Sunday, December 02, 2012 5:30 AM
> *To:* devel(a)acpica.org
> *Subject:* [Devel] ACPI 5.0 implementation for armv7 and armv8 
> architecture
>
> Hi,
>
> I am planning to implement ACPI5.0 on an SOC having Cortex A5 and 
> Atlas cpu( based on armv8 architecture) running linux on top of them.
>
> As per the ACPI 5.0 hardware specification(Fixed Hardware/ Generic 
> Hardware  model) of ACPI5.0, the processor needs to support various 
> low power modes(C0, C1, C2, C3) and sleep states(S1, S2, S3, S4, S5) 
> via register interfaces as well as OEM provided AML(ACPI Machine Language).
>
> Therefore, which instructions in armv7 and armv8 put the processor 
> into the afore-mentioned low power modes and sleep states?
>
> ( The arm instruction manual specifies “wfe” and “wfi” to put the 
> processor in a sleep state, but I am not sure if this confirms to the 
> ACPI 5.0 requirements )
>
> Besides, does arm provide any AML(ACPI Machine Language) code to put 
> the processor to low power modes? If not, then how do we create an 
> ACPI machine language code for armv7 and armv8 architecture and do we 
> have an AML interpreter for armv7 and armv8 architecture?
>
> Regards,
>
> Ayan Kumar Halder
>
>
>
> _______________________________________________
> Devel mailing list
> Devel(a)acpica.org
> http://lists.acpica.org/listinfo/devel
>


--
ciao,
al
-----------------------------------
Al Stone
Software Engineer
Red Hat, Inc.
ahs3(a)redhat.com
-----------------------------------

Re: [Devel] ACPI 5.0 implementation for armv7 and armv8 architecture

[Zheng, Lv]

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> > Therefore, which instructions in armv7 and armv8 put the processor
> > into the afore-mentioned low power modes and sleep states?
> >
> > ( The arm instruction manual specifies “wfe” and “wfi” to put the
> > processor in a sleep state, but I am not sure if this confirms to the
> > ACPI 5.0 requirements )

IMO, this is more like the S0Ix state in the ACPI spec. I'll forward your request to the knowledgeable.

Best regards
-Lv