From: Prashant Gaikwad <pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
To: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
Cc: Laxman Dewangan
<ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
"linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
"linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
Subject: Re: [PATCH 3/4] ARM: tegra: Add OF_DEV_AUXDATA for uart driver in board dt
Date: Tue, 18 Dec 2012 11:48:33 +0530 [thread overview]
Message-ID: <50D00AB9.8090800@nvidia.com> (raw)
In-Reply-To: <50CF92D5.6090805-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
On Tuesday 18 December 2012 03:17 AM, Stephen Warren wrote:
> On 12/17/2012 05:08 AM, Laxman Dewangan wrote:
>> Add OF_DEV_AUXDATA for high speed uart controller driver for
>> Tegra20/Tegra30 board dt files.
>> Set the parent clock of uart controller to PLLP.
>> diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
>> @@ -94,6 +94,11 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
>> + OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006000, "tegra-uart.0", NULL),
>> + OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006040, "tegra-uart.1", NULL),
>> + OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006200, "tegra-uart.2", NULL),
>> + OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006300, "tegra-uart.3", NULL),
>> + OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006400, "tegra-uart.4", NULL),
> Instead, can we simply get the clocks from device tree? Prashant, how
> much effort will that be once your clock patches are checked in, or is
> it already part of those patches?
It is not part of rework patches, but I will send a patch for it
immediately after those patches are accepted upstream.
>> @@ -106,7 +111,10 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
>> static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
>> /* name parent rate enabled */
>> { "uarta", "pll_p", 216000000, true },
>> + { "uartb", "pll_p", 216000000, false },
>> + { "uartc", "pll_p", 216000000, false },
>> { "uartd", "pll_p", 216000000, true },
>> + { "uarte", "pll_p", 216000000, false },
> Prashant's clock patches remove this table. Please work with him to work
> out how to deal with that.
Laxman,
If you want I can include these entries in current tables.
WARNING: multiple messages have this Message-ID (diff)
From: pgaikwad@nvidia.com (Prashant Gaikwad)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/4] ARM: tegra: Add OF_DEV_AUXDATA for uart driver in board dt
Date: Tue, 18 Dec 2012 11:48:33 +0530 [thread overview]
Message-ID: <50D00AB9.8090800@nvidia.com> (raw)
In-Reply-To: <50CF92D5.6090805@wwwdotorg.org>
On Tuesday 18 December 2012 03:17 AM, Stephen Warren wrote:
> On 12/17/2012 05:08 AM, Laxman Dewangan wrote:
>> Add OF_DEV_AUXDATA for high speed uart controller driver for
>> Tegra20/Tegra30 board dt files.
>> Set the parent clock of uart controller to PLLP.
>> diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
>> @@ -94,6 +94,11 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
>> + OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006000, "tegra-uart.0", NULL),
>> + OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006040, "tegra-uart.1", NULL),
>> + OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006200, "tegra-uart.2", NULL),
>> + OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006300, "tegra-uart.3", NULL),
>> + OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006400, "tegra-uart.4", NULL),
> Instead, can we simply get the clocks from device tree? Prashant, how
> much effort will that be once your clock patches are checked in, or is
> it already part of those patches?
It is not part of rework patches, but I will send a patch for it
immediately after those patches are accepted upstream.
>> @@ -106,7 +111,10 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
>> static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
>> /* name parent rate enabled */
>> { "uarta", "pll_p", 216000000, true },
>> + { "uartb", "pll_p", 216000000, false },
>> + { "uartc", "pll_p", 216000000, false },
>> { "uartd", "pll_p", 216000000, true },
>> + { "uarte", "pll_p", 216000000, false },
> Prashant's clock patches remove this table. Please work with him to work
> out how to deal with that.
Laxman,
If you want I can include these entries in current tables.
WARNING: multiple messages have this Message-ID (diff)
From: Prashant Gaikwad <pgaikwad@nvidia.com>
To: Stephen Warren <swarren@wwwdotorg.org>
Cc: Laxman Dewangan <ldewangan@nvidia.com>,
"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 3/4] ARM: tegra: Add OF_DEV_AUXDATA for uart driver in board dt
Date: Tue, 18 Dec 2012 11:48:33 +0530 [thread overview]
Message-ID: <50D00AB9.8090800@nvidia.com> (raw)
In-Reply-To: <50CF92D5.6090805@wwwdotorg.org>
On Tuesday 18 December 2012 03:17 AM, Stephen Warren wrote:
> On 12/17/2012 05:08 AM, Laxman Dewangan wrote:
>> Add OF_DEV_AUXDATA for high speed uart controller driver for
>> Tegra20/Tegra30 board dt files.
>> Set the parent clock of uart controller to PLLP.
>> diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
>> @@ -94,6 +94,11 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
>> + OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006000, "tegra-uart.0", NULL),
>> + OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006040, "tegra-uart.1", NULL),
>> + OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006200, "tegra-uart.2", NULL),
>> + OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006300, "tegra-uart.3", NULL),
>> + OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006400, "tegra-uart.4", NULL),
> Instead, can we simply get the clocks from device tree? Prashant, how
> much effort will that be once your clock patches are checked in, or is
> it already part of those patches?
It is not part of rework patches, but I will send a patch for it
immediately after those patches are accepted upstream.
>> @@ -106,7 +111,10 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
>> static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
>> /* name parent rate enabled */
>> { "uarta", "pll_p", 216000000, true },
>> + { "uartb", "pll_p", 216000000, false },
>> + { "uartc", "pll_p", 216000000, false },
>> { "uartd", "pll_p", 216000000, true },
>> + { "uarte", "pll_p", 216000000, false },
> Prashant's clock patches remove this table. Please work with him to work
> out how to deal with that.
Laxman,
If you want I can include these entries in current tables.
next prev parent reply other threads:[~2012-12-18 6:18 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-12-17 12:08 [PATCH 0/4] ARM: tegra: add support for highspeed serial driver Laxman Dewangan
2012-12-17 12:08 ` Laxman Dewangan
2012-12-17 12:08 ` Laxman Dewangan
2012-12-17 12:08 ` [PATCH 1/4] ARM: tegra30: Add support for Uart clock source divider as 15.1 Laxman Dewangan
2012-12-17 12:08 ` Laxman Dewangan
2012-12-17 12:08 ` Laxman Dewangan
[not found] ` <1355746101-15291-2-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2012-12-17 21:43 ` Stephen Warren
2012-12-17 21:43 ` Stephen Warren
2012-12-17 21:43 ` Stephen Warren
[not found] ` <50CF91F7.5010402-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2012-12-18 6:14 ` Prashant Gaikwad
2012-12-18 6:14 ` Prashant Gaikwad
2012-12-18 6:14 ` Prashant Gaikwad
[not found] ` <50D009E0.3050409-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2012-12-18 6:24 ` Laxman Dewangan
2012-12-18 6:24 ` Laxman Dewangan
2012-12-18 6:24 ` Laxman Dewangan
[not found] ` <50D00C1D.9090100-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2012-12-18 7:07 ` Prashant Gaikwad
2012-12-18 7:07 ` Prashant Gaikwad
2012-12-18 7:07 ` Prashant Gaikwad
2012-12-18 13:05 ` Laxman Dewangan
2012-12-18 13:05 ` Laxman Dewangan
2012-12-17 12:08 ` [PATCH 2/4] ARM: tegra: add connection name for uart clock table Laxman Dewangan
2012-12-17 12:08 ` Laxman Dewangan
2012-12-17 12:08 ` Laxman Dewangan
[not found] ` <1355746101-15291-3-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2012-12-17 21:44 ` Stephen Warren
2012-12-17 21:44 ` Stephen Warren
2012-12-17 21:44 ` Stephen Warren
[not found] ` <50CF9233.3010506-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2012-12-18 7:05 ` Laxman Dewangan
2012-12-18 7:05 ` Laxman Dewangan
2012-12-18 7:05 ` Laxman Dewangan
2012-12-18 16:55 ` Stephen Warren
2012-12-18 16:55 ` Stephen Warren
2012-12-17 12:08 ` [PATCH 3/4] ARM: tegra: Add OF_DEV_AUXDATA for uart driver in board dt Laxman Dewangan
2012-12-17 12:08 ` Laxman Dewangan
2012-12-17 12:08 ` Laxman Dewangan
2012-12-17 21:47 ` Stephen Warren
2012-12-17 21:47 ` Stephen Warren
[not found] ` <50CF92D5.6090805-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2012-12-18 6:18 ` Prashant Gaikwad [this message]
2012-12-18 6:18 ` Prashant Gaikwad
2012-12-18 6:18 ` Prashant Gaikwad
[not found] ` <50D00AB9.8090800-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2012-12-18 7:00 ` Laxman Dewangan
2012-12-18 7:00 ` Laxman Dewangan
2012-12-18 7:00 ` Laxman Dewangan
2012-12-17 12:08 ` [PATCH 4/4] ARM: tegra: dts: add dma requestor and port numbers for serial controller Laxman Dewangan
2012-12-17 12:08 ` Laxman Dewangan
2012-12-17 12:08 ` Laxman Dewangan
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