[U-Boot] [PATCH RESEND V2 1/4] EXYNOS5: Change parent clock of FIMD to MPLL

[Donghwa Lee <dh09.lee@samsung.com>]

On 2012? 12? 20? 21:35, Ajay Kumar wrote:
> With VPLL as source clock to FIMD,
> Exynos DP Initializaton was failing sometimes with unstable clock.
> Changing FIMD source to MPLL resolves this issue.
>
> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
>   arch/arm/cpu/armv7/exynos/clock.c |    2 +-
>   1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
> index fe61f88..bfcd5f7 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -603,7 +603,7 @@ void exynos5_set_lcd_clk(void)
>   	 */
>   	cfg = readl(&clk->src_disp1_0);
>   	cfg &= ~(0xf);
> -	cfg |= 0x8;
> +	cfg |= 0x6;
>   	writel(cfg, &clk->src_disp1_0);
>   
>   	/*
It looks good to me.
Acked-by: Donghwa Lee <dh09.lee@samsung.com>

Thank you,
Donghwa Lee