From: Xi Wang <xi.wang@gmail.com>
To: Drunkard Zhang <gongfan193@gmail.com>
Cc: "James E.J. Bottomley" <JBottomley@parallels.com>,
Dan Williams <dan.j.williams@intel.com>,
Jack Wang <jack_wang@usish.com>,
Xiangliang Yu <yuxiangl@marvell.com>,
linux-scsi@vger.kernel.org,
linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: mvsas regression since 3.5
Date: Sun, 23 Dec 2012 02:17:06 -0500 [thread overview]
Message-ID: <50D6AFF2.1010708@gmail.com> (raw)
In-Reply-To: <CAJiejCRCXgCw957to0fWhQPS69doacY9DOaQMpfyxM4bm3igQw@mail.gmail.com>
On 12/22/12 10:33 AM, Drunkard Zhang wrote:
> I'm using Asus PIKE 6480 SAS card, whose chipset is "RAID bus
> controller: Marvell Technology Group Ltd. MV64460/64461/64462 System
> Controller, Revision B", with latest stable branch 3.7.1 only 1 of 8
> ports works, to get others works I got to pull & plug back. While with
> 3.5.7 it's all good, so it must be a regression.
Can you try to revert commit beecadea1b8d67f591b13f7099559f32f3fd601d?
Particularly, can you first change
#define bit(n) ((u64)1 << n)
in drivers/scsi/mvsas/mv_sas.h back to
#define bit(n) ((u32)1 << n)
and see if it works for you? Thanks.
- xi
next prev parent reply other threads:[~2012-12-23 7:22 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-12-22 15:33 mvsas regression since 3.5 Drunkard Zhang
2012-12-23 7:17 ` Xi Wang [this message]
2012-12-23 8:26 ` Drunkard Zhang
2012-12-23 8:44 ` James Bottomley
2012-12-24 1:50 ` Jack Wang
2012-12-24 1:50 ` Jack Wang
2012-12-24 4:32 ` Drunkard Zhang
2012-12-24 4:32 ` Drunkard Zhang
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