Re: [Qemu-devel] [PATCH] PIIX3: reset the VM when the Reset Control Register's RCPU bit gets set

[Paolo Bonzini <pbonzini@redhat.com>]

Il 15/01/2013 00:47, Laszlo Ersek ha scritto:
> @@ -442,12 +455,14 @@ static void piix3_reset(void *opaque)
>      pci_conf[0xae] = 0x00;
>  
>      d->pic_levels = 0;
> +    d->rcr = 0;
>  }
>  
>  static int piix3_post_load(void *opaque, int version_id)
>  {
>      PIIX3State *piix3 = opaque;
>      piix3_update_irq_levels(piix3);
> +    piix3->rcr &= 2; /* keep System Reset type only */
>      return 0;
>  }
>  
> @@ -464,7 +479,7 @@ static void piix3_pre_save(void *opaque)
>  
>  static const VMStateDescription vmstate_piix3 = {
>      .name = "PIIX3",
> -    .version_id = 3,
> +    .version_id = 4,
>      .minimum_version_id = 2,
>      .minimum_version_id_old = 2,
>      .post_load = piix3_post_load,
> @@ -473,15 +488,46 @@ static const VMStateDescription vmstate_piix3 = {
>          VMSTATE_PCI_DEVICE(dev, PIIX3State),
>          VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
>                                PIIX_NUM_PIRQS, 3),
> +        VMSTATE_UINT8_V(rcr, PIIX3State, 4),
>          VMSTATE_END_OF_LIST()
>      }

It would be nice to put this in a subsection, since it should be almost
always 0.

Otherwise, the patch looks good.

Thanks!

Paolo