[Qemu-devel] [RFC qom-cpu v2 0/2] target-sh4: SuperHCPU subclasses

[Qemu-devel] [RFC qom-cpu v2 0/2] target-sh4: SuperHCPU subclasses

[Andreas Färber]

Hello,

This series introduces SuperH CPU subclasses.
The first conversion to QOM patch had used a declarative approach reusing
sh4_def_t as SuperHCPUInfo. This approach now uses imperative instance_init
functions. To preserve -cpu ? output and case-insensitivity, distinct name
and type name are used, but allowing use of the type name as done for alpha.

TODO: guard against abstract types (may apply to other targets as well)
TODO: move class -> name lookup to cpu.c?

This series in context:
+ qom-cpu cleanups and bugfixes being queued for 1.4
+ CPUState QOM realizefn and initfn RFC for 1.5 / qom-cpu-next
~ SuperHCPU subclasses (this series)
- SH7750 QOM'ification (to be rebased)
- cross-target refactoring of cpu_init() and "realized" behavior (TBD)

Available for testing at:
git://github.com/afaerber/qemu-cpu.git qom-cpu-sh4-classes.v2
https://github.com/afaerber/qemu-cpu/commits/qom-cpu-sh4-classes.v2

Regards,
Andreas

v2:
* Fixed bug in class name comparison, spotted by Igor.
* Refactored name -> ObjectClass mapping into new function.
* Moved realizefn patch into CPUState series, rebased.

v1 -> preview on GitHub:
* Redone, using combination of initfn and class_init instead of SuperHCPUInfo.
* Adopted naming scheme suggested by Eduardo.
* Split out SuperHCPUClass field movements into separate patch.

Cc: Aurélien Jarno <aurelien@aurel32.net>

Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Eduardo Habkost <ehabkost@redhat.com>

Andreas Färber (2):
  target-sh4: Introduce SuperHCPU subclasses
  target-sh4: Move PVR/PRR/CVR into SuperHCPUClass

 hw/sh7750.c            |   10 ++--
 target-sh4/cpu-qom.h   |   13 +++++
 target-sh4/cpu.c       |  124 +++++++++++++++++++++++++++++++++++++++++++++++-
 target-sh4/cpu.h       |    3 --
 target-sh4/translate.c |   94 +++++++++++++-----------------------
 5 Dateien geändert, 175 Zeilen hinzugefügt(+), 69 Zeilen entfernt(-)

-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 1/2] target-sh4: Introduce SuperHCPU subclasses

[Andreas Färber]

Store legacy name in SuperHCPUClass for -cpu ? and for case-insensitive
class lookup.

List CPUs by iterating over TYPE_SUPERH_CPU subclasses.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-sh4/cpu-qom.h   |    7 +++
 target-sh4/cpu.c       |  124 +++++++++++++++++++++++++++++++++++++++++++++++-
 target-sh4/translate.c |   94 +++++++++++++-----------------------
 3 Dateien geändert, 162 Zeilen hinzugefügt(+), 63 Zeilen entfernt(-)

diff --git a/target-sh4/cpu-qom.h b/target-sh4/cpu-qom.h
index d368db1..8326ceb 100644
--- a/target-sh4/cpu-qom.h
+++ b/target-sh4/cpu-qom.h
@@ -24,6 +24,10 @@
 
 #define TYPE_SUPERH_CPU "superh-cpu"
 
+#define TYPE_SH7750R_CPU "sh7750r-" TYPE_SUPERH_CPU
+#define TYPE_SH7751R_CPU "sh7751r-" TYPE_SUPERH_CPU
+#define TYPE_SH7785_CPU "sh7785-" TYPE_SUPERH_CPU
+
 #define SUPERH_CPU_CLASS(klass) \
     OBJECT_CLASS_CHECK(SuperHCPUClass, (klass), TYPE_SUPERH_CPU)
 #define SUPERH_CPU(obj) \
@@ -35,6 +39,7 @@
  * SuperHCPUClass:
  * @parent_realize: The parent class' realize handler.
  * @parent_reset: The parent class' reset handler.
+ * @name: The name.
  *
  * A SuperH CPU model.
  */
@@ -45,6 +50,8 @@ typedef struct SuperHCPUClass {
 
     DeviceRealize parent_realize;
     void (*parent_reset)(CPUState *cpu);
+
+    const char *name;
 } SuperHCPUClass;
 
 /**
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index 223008a..80804ef 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -53,6 +53,125 @@ static void superh_cpu_reset(CPUState *s)
     set_default_nan_mode(1, &env->fp_status);
 }
 
+typedef struct SuperHCPUListState {
+    fprintf_function cpu_fprintf;
+    FILE *file;
+} SuperHCPUListState;
+
+/* Sort alphabetically by type name. */
+static gint superh_cpu_list_compare(gconstpointer a, gconstpointer b)
+{
+    ObjectClass *class_a = (ObjectClass *)a;
+    ObjectClass *class_b = (ObjectClass *)b;
+    const char *name_a, *name_b;
+
+    name_a = object_class_get_name(class_a);
+    name_b = object_class_get_name(class_b);
+    return strcmp(name_a, name_b);
+}
+
+static void superh_cpu_list_entry(gpointer data, gpointer user_data)
+{
+    ObjectClass *oc = data;
+    SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
+    SuperHCPUListState *s = user_data;
+
+    (*s->cpu_fprintf)(s->file, "%s\n",
+                      scc->name);
+}
+
+void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf)
+{
+    SuperHCPUListState s = {
+        .cpu_fprintf = cpu_fprintf,
+        .file = f,
+    };
+    GSList *list;
+
+    list = object_class_get_list(TYPE_SUPERH_CPU, false);
+    list = g_slist_sort(list, superh_cpu_list_compare);
+    g_slist_foreach(list, superh_cpu_list_entry, &s);
+    g_slist_free(list);
+}
+
+static void sh7750r_cpu_initfn(Object *obj)
+{
+    SuperHCPU *cpu = SUPERH_CPU(obj);
+    CPUSH4State *env = &cpu->env;
+
+    env->id = SH_CPU_SH7750R;
+    env->pvr = 0x00050000;
+    env->prr = 0x00000100;
+    env->cvr = 0x00110000;
+    env->features = SH_FEATURE_BCR3_AND_BCR4;
+}
+
+static void sh7750r_class_init(ObjectClass *oc, void *data)
+{
+    SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
+
+    scc->name = "SH7750R";
+}
+
+static const TypeInfo sh7750r_type_info = {
+    .name = TYPE_SH7750R_CPU,
+    .parent = TYPE_SUPERH_CPU,
+    .class_init = sh7750r_class_init,
+    .instance_init = sh7750r_cpu_initfn,
+};
+
+static void sh7751r_cpu_initfn(Object *obj)
+{
+    SuperHCPU *cpu = SUPERH_CPU(obj);
+    CPUSH4State *env = &cpu->env;
+
+    env->id = SH_CPU_SH7751R;
+    env->pvr = 0x04050005;
+    env->prr = 0x00000113;
+    env->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
+    env->features = SH_FEATURE_BCR3_AND_BCR4;
+}
+
+static void sh7751r_class_init(ObjectClass *oc, void *data)
+{
+    SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
+
+    scc->name = "SH7751R";
+}
+
+static const TypeInfo sh7751r_type_info = {
+    .name = TYPE_SH7751R_CPU,
+    .parent = TYPE_SUPERH_CPU,
+    .class_init = sh7751r_class_init,
+    .instance_init = sh7751r_cpu_initfn,
+};
+
+static void sh7785_cpu_initfn(Object *obj)
+{
+    SuperHCPU *cpu = SUPERH_CPU(obj);
+    CPUSH4State *env = &cpu->env;
+
+    env->id = SH_CPU_SH7785;
+    env->pvr = 0x10300700;
+    env->prr = 0x00000200;
+    env->cvr = 0x71440211;
+    env->features = SH_FEATURE_SH4A;
+}
+
+static void sh7785_class_init(ObjectClass *oc, void *data)
+{
+    SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
+
+    scc->name = "SH7785";
+}
+
+static const TypeInfo sh7785_type_info = {
+    .name = TYPE_SH7785_CPU,
+    .parent = TYPE_SUPERH_CPU,
+    .class_init = sh7785_class_init,
+    .instance_init = sh7785_cpu_initfn,
+};
+
 static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
 {
     SuperHCPU *cpu = SUPERH_CPU(dev);
@@ -96,7 +215,7 @@ static const TypeInfo superh_cpu_type_info = {
     .parent = TYPE_CPU,
     .instance_size = sizeof(SuperHCPU),
     .instance_init = superh_cpu_initfn,
-    .abstract = false,
+    .abstract = true,
     .class_size = sizeof(SuperHCPUClass),
     .class_init = superh_cpu_class_init,
 };
@@ -104,6 +223,9 @@ static const TypeInfo superh_cpu_type_info = {
 static void superh_cpu_register_types(void)
 {
     type_register_static(&superh_cpu_type_info);
+    type_register_static(&sh7750r_type_info);
+    type_register_static(&sh7751r_type_info);
+    type_register_static(&sh7785_type_info);
 }
 
 type_init(superh_cpu_register_types)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index c58d79a..2bdf3b2 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -175,84 +175,54 @@ void cpu_dump_state(CPUSH4State * env, FILE * f,
     }
 }
 
-typedef struct {
-    const char *name;
-    int id;
-    uint32_t pvr;
-    uint32_t prr;
-    uint32_t cvr;
-    uint32_t features;
-} sh4_def_t;
-
-static sh4_def_t sh4_defs[] = {
-    {
-	.name = "SH7750R",
-	.id = SH_CPU_SH7750R,
-	.pvr = 0x00050000,
-	.prr = 0x00000100,
-	.cvr = 0x00110000,
-	.features = SH_FEATURE_BCR3_AND_BCR4,
-    }, {
-	.name = "SH7751R",
-	.id = SH_CPU_SH7751R,
-	.pvr = 0x04050005,
-	.prr = 0x00000113,
-	.cvr = 0x00110000,	/* Neutered caches, should be 0x20480000 */
-	.features = SH_FEATURE_BCR3_AND_BCR4,
-    }, {
-	.name = "SH7785",
-	.id = SH_CPU_SH7785,
-	.pvr = 0x10300700,
-	.prr = 0x00000200,
-	.cvr = 0x71440211,
-	.features = SH_FEATURE_SH4A,
-     },
-};
-
-static const sh4_def_t *cpu_sh4_find_by_name(const char *name)
+static gint superh_cpu_name_compare(gconstpointer a, gconstpointer b)
 {
-    int i;
+    const SuperHCPUClass *scc = SUPERH_CPU_CLASS(a);
+    const char *name = b;
 
-    if (strcasecmp(name, "any") == 0)
-	return &sh4_defs[0];
-
-    for (i = 0; i < ARRAY_SIZE(sh4_defs); i++)
-	if (strcasecmp(name, sh4_defs[i].name) == 0)
-	    return &sh4_defs[i];
-
-    return NULL;
+    return strcasecmp(scc->name, name);
 }
 
-void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf)
+static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
 {
-    int i;
+    ObjectClass *oc;
+    GSList *list, *item;
 
-    for (i = 0; i < ARRAY_SIZE(sh4_defs); i++)
-	(*cpu_fprintf)(f, "%s\n", sh4_defs[i].name);
-}
+    if (cpu_model == NULL) {
+        return NULL;
+    }
+    if (strcasecmp(cpu_model, "any") == 0) {
+        return object_class_by_name(TYPE_SH7750R_CPU);
+    }
 
-static void cpu_register(CPUSH4State *env, const sh4_def_t *def)
-{
-    env->pvr = def->pvr;
-    env->prr = def->prr;
-    env->cvr = def->cvr;
-    env->id = def->id;
+    oc = object_class_by_name(cpu_model);
+    if (oc != NULL && object_class_dynamic_cast(oc, TYPE_SUPERH_CPU) != NULL) {
+        return oc;
+    }
+
+    oc = NULL;
+    list = object_class_get_list(TYPE_SUPERH_CPU, false);
+    item = g_slist_find_custom(list, cpu_model, superh_cpu_name_compare);
+    if (item != NULL) {
+        oc = item->data;
+    }
+    g_slist_free(list);
+    return oc;
 }
 
 SuperHCPU *cpu_sh4_init(const char *cpu_model)
 {
     SuperHCPU *cpu;
     CPUSH4State *env;
-    const sh4_def_t *def;
+    ObjectClass *oc;
 
-    def = cpu_sh4_find_by_name(cpu_model);
-    if (!def)
-	return NULL;
-    cpu = SUPERH_CPU(object_new(TYPE_SUPERH_CPU));
+    oc = superh_cpu_class_by_name(cpu_model);
+    if (oc == NULL) {
+        return NULL;
+    }
+    cpu = SUPERH_CPU(object_new(object_class_get_name(oc)));
     env = &cpu->env;
-    env->features = def->features;
     env->cpu_model_str = cpu_model;
-    cpu_register(env, def);
 
     object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
 
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 2/2] target-sh4: Move PVR/PRR/CVR into SuperHCPUClass

[Andreas Färber]

They are never changed once initialized, and moving them to the class
will allow to inspect them before instantiating.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 hw/sh7750.c          |   10 +++++++---
 target-sh4/cpu-qom.h |    6 ++++++
 target-sh4/cpu.c     |   18 +++++++++---------
 target-sh4/cpu.h     |    3 ---
 4 Dateien geändert, 22 Zeilen hinzugefügt(+), 15 Zeilen entfernt(-)

diff --git a/hw/sh7750.c b/hw/sh7750.c
index 666f865..2259b59 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -255,6 +255,7 @@ static uint32_t sh7750_mem_readw(void *opaque, hwaddr addr)
 static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr)
 {
     SH7750State *s = opaque;
+    SuperHCPUClass *scc;
 
     switch (addr) {
     case SH7750_BCR1_A7:
@@ -288,11 +289,14 @@ static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr)
     case SH7750_CCR_A7:
 	return s->ccr;
     case 0x1f000030:		/* Processor version */
-	return s->cpu->pvr;
+        scc = SUPERH_CPU_GET_CLASS(s->cpu);
+        return scc->pvr;
     case 0x1f000040:		/* Cache version */
-	return s->cpu->cvr;
+        scc = SUPERH_CPU_GET_CLASS(s->cpu);
+        return scc->cvr;
     case 0x1f000044:		/* Processor revision */
-	return s->cpu->prr;
+        scc = SUPERH_CPU_GET_CLASS(s->cpu);
+        return scc->prr;
     default:
 	error_access("long read", addr);
         abort();
diff --git a/target-sh4/cpu-qom.h b/target-sh4/cpu-qom.h
index 8326ceb..b264be7 100644
--- a/target-sh4/cpu-qom.h
+++ b/target-sh4/cpu-qom.h
@@ -40,6 +40,9 @@
  * @parent_realize: The parent class' realize handler.
  * @parent_reset: The parent class' reset handler.
  * @name: The name.
+ * @pvr: Processor Version Register
+ * @prr: Processor Revision Register
+ * @cvr: Cache Version Register
  *
  * A SuperH CPU model.
  */
@@ -52,6 +55,9 @@ typedef struct SuperHCPUClass {
     void (*parent_reset)(CPUState *cpu);
 
     const char *name;
+    uint32_t pvr;
+    uint32_t prr;
+    uint32_t cvr;
 } SuperHCPUClass;
 
 /**
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index 80804ef..d4ba957 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -100,9 +100,6 @@ static void sh7750r_cpu_initfn(Object *obj)
     CPUSH4State *env = &cpu->env;
 
     env->id = SH_CPU_SH7750R;
-    env->pvr = 0x00050000;
-    env->prr = 0x00000100;
-    env->cvr = 0x00110000;
     env->features = SH_FEATURE_BCR3_AND_BCR4;
 }
 
@@ -111,6 +108,9 @@ static void sh7750r_class_init(ObjectClass *oc, void *data)
     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 
     scc->name = "SH7750R";
+    scc->pvr = 0x00050000;
+    scc->prr = 0x00000100;
+    scc->cvr = 0x00110000;
 }
 
 static const TypeInfo sh7750r_type_info = {
@@ -126,9 +126,6 @@ static void sh7751r_cpu_initfn(Object *obj)
     CPUSH4State *env = &cpu->env;
 
     env->id = SH_CPU_SH7751R;
-    env->pvr = 0x04050005;
-    env->prr = 0x00000113;
-    env->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
     env->features = SH_FEATURE_BCR3_AND_BCR4;
 }
 
@@ -137,6 +134,9 @@ static void sh7751r_class_init(ObjectClass *oc, void *data)
     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 
     scc->name = "SH7751R";
+    scc->pvr = 0x04050005;
+    scc->prr = 0x00000113;
+    scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
 }
 
 static const TypeInfo sh7751r_type_info = {
@@ -152,9 +152,6 @@ static void sh7785_cpu_initfn(Object *obj)
     CPUSH4State *env = &cpu->env;
 
     env->id = SH_CPU_SH7785;
-    env->pvr = 0x10300700;
-    env->prr = 0x00000200;
-    env->cvr = 0x71440211;
     env->features = SH_FEATURE_SH4A;
 }
 
@@ -163,6 +160,9 @@ static void sh7785_class_init(ObjectClass *oc, void *data)
     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 
     scc->name = "SH7785";
+    scc->pvr = 0x10300700;
+    scc->prr = 0x00000200;
+    scc->cvr = 0x71440211;
 }
 
 static const TypeInfo sh7785_type_info = {
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 49dcd9e..f805778 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -179,9 +179,6 @@ typedef struct CPUSH4State {
     CPU_COMMON
 
     int id;			/* CPU model */
-    uint32_t pvr;		/* Processor Version Register */
-    uint32_t prr;		/* Processor Revision Register */
-    uint32_t cvr;		/* Cache Version Register */
 
     void *intc_handle;
     int in_sleep;		/* SR_BL ignored during sleep */
-- 
1.7.10.4

Re: [Qemu-devel] [RFC qom-cpu v2 0/2] target-sh4: SuperHCPU subclasses

[Andreas Färber]

Am 21.01.2013 04:28, schrieb Andreas Färber:
> Hello,
> 
> This series introduces SuperH CPU subclasses.
> The first conversion to QOM patch had used a declarative approach reusing
> sh4_def_t as SuperHCPUInfo. This approach now uses imperative instance_init
> functions. To preserve -cpu ? output and case-insensitivity, distinct name
> and type name are used, but allowing use of the type name as done for alpha.
> 
> TODO: guard against abstract types (may apply to other targets as well)
> TODO: move class -> name lookup to cpu.c?
> 
> This series in context:
> + qom-cpu cleanups and bugfixes being queued for 1.4
> + CPUState QOM realizefn and initfn RFC for 1.5 / qom-cpu-next
> ~ SuperHCPU subclasses (this series)
> - SH7750 QOM'ification (to be rebased)
> - cross-target refactoring of cpu_init() and "realized" behavior (TBD)
> 
> Available for testing at:
> git://github.com/afaerber/qemu-cpu.git qom-cpu-sh4-classes.v2
> https://github.com/afaerber/qemu-cpu/commits/qom-cpu-sh4-classes.v2

Note that the default sh4 machine shix does not check the return value
of cpu_init() and silently continues even without CPU. I've used -M r2d
for testing and will try to post a fix for 1.4.

Andreas

> v2:
> * Fixed bug in class name comparison, spotted by Igor.
> * Refactored name -> ObjectClass mapping into new function.
> * Moved realizefn patch into CPUState series, rebased.
> 
> v1 -> preview on GitHub:
> * Redone, using combination of initfn and class_init instead of SuperHCPUInfo.
> * Adopted naming scheme suggested by Eduardo.
> * Split out SuperHCPUClass field movements into separate patch.
> 
> Cc: Aurélien Jarno <aurelien@aurel32.net>
> 
> Cc: Igor Mammedov <imammedo@redhat.com>
> Cc: Eduardo Habkost <ehabkost@redhat.com>
> 
> Andreas Färber (2):
>   target-sh4: Introduce SuperHCPU subclasses
>   target-sh4: Move PVR/PRR/CVR into SuperHCPUClass
> 
>  hw/sh7750.c            |   10 ++--
>  target-sh4/cpu-qom.h   |   13 +++++
>  target-sh4/cpu.c       |  124 +++++++++++++++++++++++++++++++++++++++++++++++-
>  target-sh4/cpu.h       |    3 --
>  target-sh4/translate.c |   94 +++++++++++++-----------------------
>  5 Dateien geändert, 175 Zeilen hinzugefügt(+), 69 Zeilen entfernt(-)

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