* [PATCH v3] PCI: Document PCIE BUS MPS parameters
@ 2013-01-25 9:36 Yijing Wang
2013-01-29 5:00 ` Jon Mason
0 siblings, 1 reply; 4+ messages in thread
From: Yijing Wang @ 2013-01-25 9:36 UTC (permalink / raw)
To: Rob Landley, Bjorn Helgaas, Jon Mason
Cc: linux-doc, linux-kernel, linux-pci, Andrew Murray, Joe Lawrence,
Randy Dunlap, Hanjun Guo, jiang.liu, Yijing Wang
v0->v1: Update MPS parameters as non-arch and add MRRS
description into pcie_bus_perf parameter suggested
by Andrew Murray.
v1->v2: Update some semantic problems and add MPS and MRRS
explanation suggested by Joe Lawrence and Randy Dunlap.
v2->v3: Update some semantic problems and the description
of pcie_bus_safe and pcie_bus_peer2peer suggested
by Bjorn Helgaas.
Document PCIE BUS MPS parameters pcie_bus_tune_off, pcie_bus_safe,
pcie_bus_peer2peer, pcie_bus_perf into Documentation/kernel-parameters.txt.
These parameters were introduced by Jon Mason <mason@myri.com> at
commit 5f39e6705 and commit b03e7495a8.
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
---
Documentation/kernel-parameters.txt | 13 +++++++++++++
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 363e348..2997df2 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -2227,6 +2227,19 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
This sorting is done to get a device
order compatible with older (<= 2.4) kernels.
nobfsort Don't sort PCI devices into breadth-first order.
+ pcie_bus_tune_off Disable PCIe MPS (Max Payload Size)
+ tuning and use the BIOS-configured MPS defaults.
+ pcie_bus_safe Use the smallest supported MPS of any device
+ below a root complex.
+ pcie_bus_perf Configure device MPS to the largest
+ allowable MPS based on its parent bus. Also set
+ MRRS (Max Read Request Size) to the largest supported
+ value (no larger than the MPS that the device or bus
+ can support) for best performance.
+ pcie_bus_peer2peer Set every device's MPS to 128B, which
+ every device is guaranteed to support. This
+ configuration allows peer-to-peer DMA between any pair
+ of devices possibly at the cost of reduced performance.
cbiosize=nn[KMG] The fixed amount of bus space which is
reserved for the CardBus bridge's IO window.
The default value is 256 bytes.
--
1.7.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v3] PCI: Document PCIE BUS MPS parameters
2013-01-25 9:36 [PATCH v3] PCI: Document PCIE BUS MPS parameters Yijing Wang
@ 2013-01-29 5:00 ` Jon Mason
2013-01-29 6:09 ` Yijing Wang
0 siblings, 1 reply; 4+ messages in thread
From: Jon Mason @ 2013-01-29 5:00 UTC (permalink / raw)
To: Yijing Wang
Cc: Rob Landley, Bjorn Helgaas, linux-doc, linux-kernel, linux-pci,
Andrew Murray, Joe Lawrence, Randy Dunlap, Hanjun Guo, jiang.liu
On Fri, Jan 25, 2013 at 2:36 AM, Yijing Wang <wangyijing@huawei.com> wrote:
> v0->v1: Update MPS parameters as non-arch and add MRRS
> description into pcie_bus_perf parameter suggested
> by Andrew Murray.
> v1->v2: Update some semantic problems and add MPS and MRRS
> explanation suggested by Joe Lawrence and Randy Dunlap.
> v2->v3: Update some semantic problems and the description
> of pcie_bus_safe and pcie_bus_peer2peer suggested
> by Bjorn Helgaas.
>
> Document PCIE BUS MPS parameters pcie_bus_tune_off, pcie_bus_safe,
> pcie_bus_peer2peer, pcie_bus_perf into Documentation/kernel-parameters.txt.
> These parameters were introduced by Jon Mason <mason@myri.com> at
> commit 5f39e6705 and commit b03e7495a8.
>
> Signed-off-by: Yijing Wang <wangyijing@huawei.com>
> ---
> Documentation/kernel-parameters.txt | 13 +++++++++++++
> 1 files changed, 13 insertions(+), 0 deletions(-)
>
> diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
> index 363e348..2997df2 100644
> --- a/Documentation/kernel-parameters.txt
> +++ b/Documentation/kernel-parameters.txt
> @@ -2227,6 +2227,19 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
> This sorting is done to get a device
> order compatible with older (<= 2.4) kernels.
> nobfsort Don't sort PCI devices into breadth-first order.
> + pcie_bus_tune_off Disable PCIe MPS (Max Payload Size)
> + tuning and use the BIOS-configured MPS defaults.
> + pcie_bus_safe Use the smallest supported MPS of any device
> + below a root complex.
This isn't correct. It should be something like "The largest MPS
common to all devices below the root complex".
> + pcie_bus_perf Configure device MPS to the largest
> + allowable MPS based on its parent bus. Also set
> + MRRS (Max Read Request Size) to the largest supported
> + value (no larger than the MPS that the device or bus
> + can support) for best performance.
> + pcie_bus_peer2peer Set every device's MPS to 128B, which
> + every device is guaranteed to support. This
> + configuration allows peer-to-peer DMA between any pair
> + of devices possibly at the cost of reduced performance.
> cbiosize=nn[KMG] The fixed amount of bus space which is
> reserved for the CardBus bridge's IO window.
> The default value is 256 bytes.
> --
> 1.7.1
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v3] PCI: Document PCIE BUS MPS parameters
2013-01-29 5:00 ` Jon Mason
@ 2013-01-29 6:09 ` Yijing Wang
2013-01-29 14:18 ` Jon Mason
0 siblings, 1 reply; 4+ messages in thread
From: Yijing Wang @ 2013-01-29 6:09 UTC (permalink / raw)
To: Jon Mason
Cc: Rob Landley, Bjorn Helgaas, linux-doc, linux-kernel, linux-pci,
Andrew Murray, Joe Lawrence, Randy Dunlap, Hanjun Guo, jiang.liu
On 2013/1/29 13:00, Jon Mason wrote:
> On Fri, Jan 25, 2013 at 2:36 AM, Yijing Wang <wangyijing@huawei.com> wrote:
>> v0->v1: Update MPS parameters as non-arch and add MRRS
>> description into pcie_bus_perf parameter suggested
>> by Andrew Murray.
>> v1->v2: Update some semantic problems and add MPS and MRRS
>> explanation suggested by Joe Lawrence and Randy Dunlap.
>> v2->v3: Update some semantic problems and the description
>> of pcie_bus_safe and pcie_bus_peer2peer suggested
>> by Bjorn Helgaas.
>>
>> Document PCIE BUS MPS parameters pcie_bus_tune_off, pcie_bus_safe,
>> pcie_bus_peer2peer, pcie_bus_perf into Documentation/kernel-parameters.txt.
>> These parameters were introduced by Jon Mason <mason@myri.com> at
>> commit 5f39e6705 and commit b03e7495a8.
>>
>> Signed-off-by: Yijing Wang <wangyijing@huawei.com>
>> ---
>> Documentation/kernel-parameters.txt | 13 +++++++++++++
>> 1 files changed, 13 insertions(+), 0 deletions(-)
>>
>> diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
>> index 363e348..2997df2 100644
>> --- a/Documentation/kernel-parameters.txt
>> +++ b/Documentation/kernel-parameters.txt
>> @@ -2227,6 +2227,19 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
>> This sorting is done to get a device
>> order compatible with older (<= 2.4) kernels.
>> nobfsort Don't sort PCI devices into breadth-first order.
>> + pcie_bus_tune_off Disable PCIe MPS (Max Payload Size)
>> + tuning and use the BIOS-configured MPS defaults.
>> + pcie_bus_safe Use the smallest supported MPS of any device
>> + below a root complex.
>
> This isn't correct. It should be something like "The largest MPS
> common to all devices below the root complex".
Hi Jon,
Thanks for your review and comment!
What about "Set every device's MPS to the largest MPSS (Max Payload Size Support)
common to all devices below the root complex" ?
>
>> + pcie_bus_perf Configure device MPS to the largest
>> + allowable MPS based on its parent bus. Also set
>> + MRRS (Max Read Request Size) to the largest supported
>> + value (no larger than the MPS that the device or bus
>> + can support) for best performance.
>> + pcie_bus_peer2peer Set every device's MPS to 128B, which
>> + every device is guaranteed to support. This
>> + configuration allows peer-to-peer DMA between any pair
>> + of devices possibly at the cost of reduced performance.
>> cbiosize=nn[KMG] The fixed amount of bus space which is
>> reserved for the CardBus bridge's IO window.
>> The default value is 256 bytes.
>> --
>> 1.7.1
>>
>>
>
> .
>
--
Thanks!
Yijing
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v3] PCI: Document PCIE BUS MPS parameters
2013-01-29 6:09 ` Yijing Wang
@ 2013-01-29 14:18 ` Jon Mason
0 siblings, 0 replies; 4+ messages in thread
From: Jon Mason @ 2013-01-29 14:18 UTC (permalink / raw)
To: Yijing Wang
Cc: Rob Landley, Bjorn Helgaas, linux-doc, linux-kernel, linux-pci,
Andrew Murray, Joe Lawrence, Randy Dunlap, Hanjun Guo, jiang.liu
On Mon, Jan 28, 2013 at 11:09 PM, Yijing Wang <wangyijing@huawei.com> wrote:
> On 2013/1/29 13:00, Jon Mason wrote:
>> On Fri, Jan 25, 2013 at 2:36 AM, Yijing Wang <wangyijing@huawei.com> wrote:
>>> v0->v1: Update MPS parameters as non-arch and add MRRS
>>> description into pcie_bus_perf parameter suggested
>>> by Andrew Murray.
>>> v1->v2: Update some semantic problems and add MPS and MRRS
>>> explanation suggested by Joe Lawrence and Randy Dunlap.
>>> v2->v3: Update some semantic problems and the description
>>> of pcie_bus_safe and pcie_bus_peer2peer suggested
>>> by Bjorn Helgaas.
>>>
>>> Document PCIE BUS MPS parameters pcie_bus_tune_off, pcie_bus_safe,
>>> pcie_bus_peer2peer, pcie_bus_perf into Documentation/kernel-parameters.txt.
>>> These parameters were introduced by Jon Mason <mason@myri.com> at
>>> commit 5f39e6705 and commit b03e7495a8.
>>>
>>> Signed-off-by: Yijing Wang <wangyijing@huawei.com>
>>> ---
>>> Documentation/kernel-parameters.txt | 13 +++++++++++++
>>> 1 files changed, 13 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
>>> index 363e348..2997df2 100644
>>> --- a/Documentation/kernel-parameters.txt
>>> +++ b/Documentation/kernel-parameters.txt
>>> @@ -2227,6 +2227,19 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
>>> This sorting is done to get a device
>>> order compatible with older (<= 2.4) kernels.
>>> nobfsort Don't sort PCI devices into breadth-first order.
>>> + pcie_bus_tune_off Disable PCIe MPS (Max Payload Size)
>>> + tuning and use the BIOS-configured MPS defaults.
>>> + pcie_bus_safe Use the smallest supported MPS of any device
>>> + below a root complex.
>>
>> This isn't correct. It should be something like "The largest MPS
>> common to all devices below the root complex".
>
> Hi Jon,
> Thanks for your review and comment!
> What about "Set every device's MPS to the largest MPSS (Max Payload Size Support)
> common to all devices below the root complex" ?
Sounds great! Thanks so much for documenting this.
>
>>
>>> + pcie_bus_perf Configure device MPS to the largest
>>> + allowable MPS based on its parent bus. Also set
>>> + MRRS (Max Read Request Size) to the largest supported
>>> + value (no larger than the MPS that the device or bus
>>> + can support) for best performance.
>>> + pcie_bus_peer2peer Set every device's MPS to 128B, which
>>> + every device is guaranteed to support. This
>>> + configuration allows peer-to-peer DMA between any pair
>>> + of devices possibly at the cost of reduced performance.
>>> cbiosize=nn[KMG] The fixed amount of bus space which is
>>> reserved for the CardBus bridge's IO window.
>>> The default value is 256 bytes.
>>> --
>>> 1.7.1
>>>
>>>
>>
>> .
>>
>
>
> --
> Thanks!
> Yijing
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2013-01-29 14:18 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2013-01-25 9:36 [PATCH v3] PCI: Document PCIE BUS MPS parameters Yijing Wang
2013-01-29 5:00 ` Jon Mason
2013-01-29 6:09 ` Yijing Wang
2013-01-29 14:18 ` Jon Mason
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