Re: [PATCH 1/2] ARM: mvebu: Add support for SPI controller in Armada 370/XP

[Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>]

Hi Ezequiel,

On 02/04/2013 05:38 PM, Ezequiel Garcia wrote:
> The Armada 370 and Armada XP SoC has an SPI controller.
> This patch adds support for this controller in Armada 370
> and Armada XP SoC common device tree files.
> 
> Cc: Gregory Clement <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> Cc: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> Cc: Lior Amsalem <alior-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Ezequiel Garcia <ezequiel.garcia-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> ---
>  arch/arm/boot/dts/armada-370-xp.dtsi |   22 ++++++++++++++++++++++
>  1 files changed, 22 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
> index 28276fe..22340d5 100644
> --- a/arch/arm/boot/dts/armada-370-xp.dtsi
> +++ b/arch/arm/boot/dts/armada-370-xp.dtsi
> @@ -145,6 +145,28 @@
>  			clocks = <&gateclk 17>;
>  			status = "disabled";
>  		};
> +
> +		spi0: spi@d0010600 {
> +			compatible = "marvell,orion-spi";
> +			reg = <0xd0010600 0x50>;

Currently the driver only use the 5th first register. All of the other
mvebu platform declare the last register at offset 0x28. The Armada
370 SoC have also the last register at offset 0x28. Only for the
Armada XP SoC there are more registers and we have a the last register
at offset 0x50. Obviously the driver won't use these extra register.

So I think that the best for now is to declare:
			reg = <0xd0010600 0x28>;

> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			cell-index = <0>;
> +			interrupts = <30>;
> +			clocks = <&coreclk 0>;
> +			status = "disabled";
> +		};
> +
> +		spi1: spi@d0010680 {
> +			compatible = "marvell,orion-spi";
> +			reg = <0xd0010680 0x50>;
and here:
			reg = <0xd0010680 0x28>;

> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			cell-index = <1>;
> +			interrupts = <92>;
> +			clocks = <&coreclk 0>;
> +			status = "disabled";
> +		};
>  	};
>  };
>  
> 

Once it will be fixed, for this patch you can add my

Acked-by: Gregory Clement <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>


Regards,
-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

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