Re: [Qemu-devel] [PATCH 3/4] target-arm: Fix VFP register byte order in GDB remote

[Fabien Chouteau <chouteau@adacore.com>]

On 03/05/2013 12:34 AM, Paul Brook wrote:
>>> Because we're actually storing two halves of a 128-bit value.   You still
>>> store the least significant half first.
>>
>> Right, I'm sorry I didn't see you comment was only about the Q registers.
>> What would be the solution then?
>>
>> #ifdef TARGET_WORDS_BIGENDIAN
>>             stfq_p(buf, env->vfp.regs[(reg - 32) * 2 + 1]);
>>             stfq_p(buf + 8, env->vfp.regs[(reg - 32) * 2]);
>> #else
>>             stfq_p(buf, env->vfp.regs[(reg - 32) * 2]);
>>             stfq_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
>> #endif  /* TARGET_WORDS_BIGENDIAN */
> 
> Yes, something like that.
> 

Alright, I'll do that for V2.

Thanks,

-- 
Fabien Chouteau