* [PATCH] Add CPUID bit mask for Performance Counter Extension
@ 2013-03-01 20:40 suravee.suthikulpanit
2013-03-04 10:07 ` Jan Beulich
0 siblings, 1 reply; 3+ messages in thread
From: suravee.suthikulpanit @ 2013-03-01 20:40 UTC (permalink / raw)
To: xen-devel, JBeulich; +Cc: Jacob Shin
From: Jacob Shin <jacob.shin@amd.com>
Signed-off-by: Jacob Shin <Jacob.Shin@amd.com>
Submitted-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
tools/libxc/xc_cpufeature.h | 1 +
tools/libxc/xc_cpuid_x86.c | 1 +
tools/libxl/libxl_cpuid.c | 1 +
3 files changed, 3 insertions(+)
diff --git a/tools/libxc/xc_cpufeature.h b/tools/libxc/xc_cpufeature.h
index c464e3a..c804af3 100644
--- a/tools/libxc/xc_cpufeature.h
+++ b/tools/libxc/xc_cpufeature.h
@@ -125,6 +125,7 @@
#define X86_FEATURE_NODEID_MSR 19 /* NodeId MSR */
#define X86_FEATURE_TBM 21 /* trailing bit manipulations */
#define X86_FEATURE_TOPOEXT 22 /* topology extensions CPUID leafs */
+#define X86_FEATURE_PERFCTR_CORE 23 /* core performance counter extensions */
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx) */
#define X86_FEATURE_FSGSBASE 0 /* {RD,WR}{FS,GS}BASE instructions */
diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c
index 17efc0f..c269468 100644
--- a/tools/libxc/xc_cpuid_x86.c
+++ b/tools/libxc/xc_cpuid_x86.c
@@ -112,6 +112,7 @@ static void amd_xc_cpuid_policy(
bitmaskof(X86_FEATURE_XOP) |
bitmaskof(X86_FEATURE_FMA4) |
bitmaskof(X86_FEATURE_TBM) |
+ bitmaskof(X86_FEATURE_PERFCTR_CORE) |
bitmaskof(X86_FEATURE_LWP));
regs[3] &= (0x0183f3ff | /* features shared with 0x00000001:EDX */
(is_pae ? bitmaskof(X86_FEATURE_NX) : 0) |
diff --git a/tools/libxl/libxl_cpuid.c b/tools/libxl/libxl_cpuid.c
index d17fdd6..f3f1265 100644
--- a/tools/libxl/libxl_cpuid.c
+++ b/tools/libxl/libxl_cpuid.c
@@ -147,6 +147,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
{"vme", 0x00000001, NA, CPUID_REG_EDX, 1, 1},
{"fpu", 0x00000001, NA, CPUID_REG_EDX, 0, 1},
{"topoext", 0x80000001, NA, CPUID_REG_ECX, 22, 1},
+ {"perfctr_core", 0x80000001, NA, CPUID_REG_ECX, 23, 1},
{"tbm", 0x80000001, NA, CPUID_REG_ECX, 21, 1},
{"nodeid", 0x80000001, NA, CPUID_REG_ECX, 19, 1},
{"fma4", 0x80000001, NA, CPUID_REG_ECX, 16, 1},
--
1.7.10.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] Add CPUID bit mask for Performance Counter Extension
2013-03-01 20:40 [PATCH] Add CPUID bit mask for Performance Counter Extension suravee.suthikulpanit
@ 2013-03-04 10:07 ` Jan Beulich
2013-03-05 22:49 ` Suravee Suthikulanit
0 siblings, 1 reply; 3+ messages in thread
From: Jan Beulich @ 2013-03-04 10:07 UTC (permalink / raw)
To: Jacob Shin, suravee.suthikulpanit; +Cc: xen-devel
>>> On 01.03.13 at 21:40, <suravee.suthikulpanit@amd.com> wrote:
> From: Jacob Shin <jacob.shin@amd.com>
So are you saying that this will work for guests without _any_
respective virtualization code in the hypervisor? If so, it would be
nice if there was text in the (currently empty) patch description
making this explicit.
Jan
> Signed-off-by: Jacob Shin <Jacob.Shin@amd.com>
> Submitted-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
> ---
> tools/libxc/xc_cpufeature.h | 1 +
> tools/libxc/xc_cpuid_x86.c | 1 +
> tools/libxl/libxl_cpuid.c | 1 +
> 3 files changed, 3 insertions(+)
>
> diff --git a/tools/libxc/xc_cpufeature.h b/tools/libxc/xc_cpufeature.h
> index c464e3a..c804af3 100644
> --- a/tools/libxc/xc_cpufeature.h
> +++ b/tools/libxc/xc_cpufeature.h
> @@ -125,6 +125,7 @@
> #define X86_FEATURE_NODEID_MSR 19 /* NodeId MSR */
> #define X86_FEATURE_TBM 21 /* trailing bit manipulations */
> #define X86_FEATURE_TOPOEXT 22 /* topology extensions CPUID leafs */
> +#define X86_FEATURE_PERFCTR_CORE 23 /* core performance counter extensions
> */
>
> /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx) */
> #define X86_FEATURE_FSGSBASE 0 /* {RD,WR}{FS,GS}BASE instructions */
> diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c
> index 17efc0f..c269468 100644
> --- a/tools/libxc/xc_cpuid_x86.c
> +++ b/tools/libxc/xc_cpuid_x86.c
> @@ -112,6 +112,7 @@ static void amd_xc_cpuid_policy(
> bitmaskof(X86_FEATURE_XOP) |
> bitmaskof(X86_FEATURE_FMA4) |
> bitmaskof(X86_FEATURE_TBM) |
> + bitmaskof(X86_FEATURE_PERFCTR_CORE) |
> bitmaskof(X86_FEATURE_LWP));
> regs[3] &= (0x0183f3ff | /* features shared with 0x00000001:EDX */
> (is_pae ? bitmaskof(X86_FEATURE_NX) : 0) |
> diff --git a/tools/libxl/libxl_cpuid.c b/tools/libxl/libxl_cpuid.c
> index d17fdd6..f3f1265 100644
> --- a/tools/libxl/libxl_cpuid.c
> +++ b/tools/libxl/libxl_cpuid.c
> @@ -147,6 +147,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list
> *cpuid, const char* str)
> {"vme", 0x00000001, NA, CPUID_REG_EDX, 1, 1},
> {"fpu", 0x00000001, NA, CPUID_REG_EDX, 0, 1},
> {"topoext", 0x80000001, NA, CPUID_REG_ECX, 22, 1},
> + {"perfctr_core", 0x80000001, NA, CPUID_REG_ECX, 23, 1},
> {"tbm", 0x80000001, NA, CPUID_REG_ECX, 21, 1},
> {"nodeid", 0x80000001, NA, CPUID_REG_ECX, 19, 1},
> {"fma4", 0x80000001, NA, CPUID_REG_ECX, 16, 1},
> --
> 1.7.10.4
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] Add CPUID bit mask for Performance Counter Extension
2013-03-04 10:07 ` Jan Beulich
@ 2013-03-05 22:49 ` Suravee Suthikulanit
0 siblings, 0 replies; 3+ messages in thread
From: Suravee Suthikulanit @ 2013-03-05 22:49 UTC (permalink / raw)
To: Jan Beulich; +Cc: Jacob Shin, xen-devel
On 3/4/2013 4:07 AM, Jan Beulich wrote:
>>>> On 01.03.13 at 21:40, <suravee.suthikulpanit@amd.com> wrote:
>> From: Jacob Shin <jacob.shin@amd.com>
> So are you saying that this will work for guests without _any_
> respective virtualization code in the hypervisor?
Yes. The MSRs are already virtualized. This patch is just adding the
mask in the CPUID to allow feature detection in the initialization code.
> If so, it would be
> nice if there was text in the (currently empty) patch description
> making this explicit.
Sorry. I am resending the patch with the commit log.
Suravee
>
> Jan
>
>> Signed-off-by: Jacob Shin <Jacob.Shin@amd.com>
>> Submitted-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
>> ---
>> tools/libxc/xc_cpufeature.h | 1 +
>> tools/libxc/xc_cpuid_x86.c | 1 +
>> tools/libxl/libxl_cpuid.c | 1 +
>> 3 files changed, 3 insertions(+)
>>
>> diff --git a/tools/libxc/xc_cpufeature.h b/tools/libxc/xc_cpufeature.h
>> index c464e3a..c804af3 100644
>> --- a/tools/libxc/xc_cpufeature.h
>> +++ b/tools/libxc/xc_cpufeature.h
>> @@ -125,6 +125,7 @@
>> #define X86_FEATURE_NODEID_MSR 19 /* NodeId MSR */
>> #define X86_FEATURE_TBM 21 /* trailing bit manipulations */
>> #define X86_FEATURE_TOPOEXT 22 /* topology extensions CPUID leafs */
>> +#define X86_FEATURE_PERFCTR_CORE 23 /* core performance counter extensions
>> */
>>
>> /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx) */
>> #define X86_FEATURE_FSGSBASE 0 /* {RD,WR}{FS,GS}BASE instructions */
>> diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c
>> index 17efc0f..c269468 100644
>> --- a/tools/libxc/xc_cpuid_x86.c
>> +++ b/tools/libxc/xc_cpuid_x86.c
>> @@ -112,6 +112,7 @@ static void amd_xc_cpuid_policy(
>> bitmaskof(X86_FEATURE_XOP) |
>> bitmaskof(X86_FEATURE_FMA4) |
>> bitmaskof(X86_FEATURE_TBM) |
>> + bitmaskof(X86_FEATURE_PERFCTR_CORE) |
>> bitmaskof(X86_FEATURE_LWP));
>> regs[3] &= (0x0183f3ff | /* features shared with 0x00000001:EDX */
>> (is_pae ? bitmaskof(X86_FEATURE_NX) : 0) |
>> diff --git a/tools/libxl/libxl_cpuid.c b/tools/libxl/libxl_cpuid.c
>> index d17fdd6..f3f1265 100644
>> --- a/tools/libxl/libxl_cpuid.c
>> +++ b/tools/libxl/libxl_cpuid.c
>> @@ -147,6 +147,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list
>> *cpuid, const char* str)
>> {"vme", 0x00000001, NA, CPUID_REG_EDX, 1, 1},
>> {"fpu", 0x00000001, NA, CPUID_REG_EDX, 0, 1},
>> {"topoext", 0x80000001, NA, CPUID_REG_ECX, 22, 1},
>> + {"perfctr_core", 0x80000001, NA, CPUID_REG_ECX, 23, 1},
>> {"tbm", 0x80000001, NA, CPUID_REG_ECX, 21, 1},
>> {"nodeid", 0x80000001, NA, CPUID_REG_ECX, 19, 1},
>> {"fma4", 0x80000001, NA, CPUID_REG_ECX, 16, 1},
>> --
>> 1.7.10.4
>
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2013-03-05 22:49 UTC | newest]
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2013-03-01 20:40 [PATCH] Add CPUID bit mask for Performance Counter Extension suravee.suthikulpanit
2013-03-04 10:07 ` Jan Beulich
2013-03-05 22:49 ` Suravee Suthikulanit
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