* [PATCH 1/8] powerpc/85xx: Added SEC-5.0 device tree. @ 2013-03-05 23:15 Kumar Gala 2013-03-05 23:15 ` [PATCH 2/8] powerpc/85xx: Add support for FSL PCIe controller v3.0 Kumar Gala 2013-03-12 21:14 ` [PATCH 1/8] powerpc/85xx: Added SEC-5.0 device tree Kumar Gala 0 siblings, 2 replies; 19+ messages in thread From: Kumar Gala @ 2013-03-05 23:15 UTC (permalink / raw) To: linuxppc-dev; +Cc: Vakul Garg From: Vakul Garg <vakul@freescale.com> Add device tree for SEC (crypto engine) version 5.0 used on T4240. Signed-off-by: Vakul Garg <vakul@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/boot/dts/fsl/qoriq-sec5.0-0.dtsi | 109 +++++++++++++++++++++++++ 1 file changed, 109 insertions(+) create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-sec5.0-0.dtsi diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec5.0-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sec5.0-0.dtsi new file mode 100644 index 0000000..ffd458f --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-sec5.0-0.dtsi @@ -0,0 +1,109 @@ +/* + * QorIQ Sec/Crypto 5.0 device tree stub [ controller @ offset 0x300000 ] + * + * Copyright 2012 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +crypto: crypto@300000 { + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x300000 0x10000>; + ranges = <0 0x300000 0x10000>; + interrupts = <92 2 0 0>; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = <88 2 0 0>; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = <89 2 0 0>; + }; + + sec_jr2: jr@3000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = <90 2 0 0>; + }; + + sec_jr3: jr@4000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x4000 0x1000>; + interrupts = <91 2 0 0>; + }; + + rtic@6000 { + compatible = "fsl,sec-v5.0-rtic", + "fsl,sec-v4.0-rtic"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x6000 0x100>; + ranges = <0x0 0x6100 0xe00>; + + rtic_a: rtic-a@0 { + compatible = "fsl,sec-v5.0-rtic-memory", + "fsl,sec-v4.0-rtic-memory"; + reg = <0x00 0x20 0x100 0x80>; + }; + + rtic_b: rtic-b@20 { + compatible = "fsl,sec-v5.0-rtic-memory", + "fsl,sec-v4.0-rtic-memory"; + reg = <0x20 0x20 0x200 0x80>; + }; + + rtic_c: rtic-c@40 { + compatible = "fsl,sec-v5.0-rtic-memory", + "fsl,sec-v4.0-rtic-memory"; + reg = <0x40 0x20 0x300 0x80>; + }; + + rtic_d: rtic-d@60 { + compatible = "fsl,sec-v5.0-rtic-memory", + "fsl,sec-v4.0-rtic-memory"; + reg = <0x60 0x20 0x500 0x80>; + }; + }; +}; + +sec_mon: sec_mon@314000 { + compatible = "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon"; + reg = <0x314000 0x1000>; + interrupts = <93 2 0 0>; +}; -- 1.7.9.7 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 2/8] powerpc/85xx: Add support for FSL PCIe controller v3.0 2013-03-05 23:15 [PATCH 1/8] powerpc/85xx: Added SEC-5.0 device tree Kumar Gala @ 2013-03-05 23:15 ` Kumar Gala 2013-03-05 23:15 ` [PATCH 3/8] powerpc/fsl-booke: Support detection of page sizes on Kumar Gala 2013-03-12 21:15 ` [PATCH 2/8] powerpc/85xx: Add support for FSL PCIe controller v3.0 Kumar Gala 2013-03-12 21:14 ` [PATCH 1/8] powerpc/85xx: Added SEC-5.0 device tree Kumar Gala 1 sibling, 2 replies; 19+ messages in thread From: Kumar Gala @ 2013-03-05 23:15 UTC (permalink / raw) To: linuxppc-dev From: Roy ZANG <tie-fei.zang@freescale.com> The T4240 utilizes a new PCIe controller block that has some minor programming model differences from previous versions. The major one that impacts initialization is how we determine the link state. On the 3.x controllers we have a memory mapped SoC register instead of a PCI config register that reports the link state. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/sysdev/fsl_pci.c | 29 ++++++++++++++++++++++++++--- arch/powerpc/sysdev/fsl_pci.h | 11 +++++++++++ 2 files changed, 37 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 682084d..3271177 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -54,13 +54,35 @@ static void quirk_fsl_pcie_header(struct pci_dev *dev) return; } -static int __init fsl_pcie_check_link(struct pci_controller *hose) +static int __init fsl_pcie_check_link(struct pci_controller *hose, + struct resource *rsrc) { + struct ccsr_pci __iomem *pci = NULL; u32 val; + /* for PCIe IP rev 3.0 or greater use CSR0 for link state */ + if (rsrc) { + pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", + (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1); + pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); + if (!pci) { + dev_err(hose->parent, "Unable to map PCIe registers\n"); + return -ENOMEM; + } + if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_3_0) { + val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK) + >> PEX_CSR0_LTSSM_SHIFT; + if (val != PEX_CSR0_LTSSM_L0) + return 1; + iounmap(pci); + return 0; + } + iounmap(pci); + } early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); if (val < PCIE_LTSSM_L0) return 1; + return 0; } @@ -483,7 +505,7 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary) if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG | PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; - if (fsl_pcie_check_link(hose)) + if (fsl_pcie_check_link(hose, &rsrc)) hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; } @@ -685,7 +707,7 @@ static int __init mpc83xx_pcie_setup(struct pci_controller *hose, out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0); out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0); - if (fsl_pcie_check_link(hose)) + if (fsl_pcie_check_link(hose, NULL)) hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; return 0; @@ -836,6 +858,7 @@ static const struct of_device_id pci_ids[] = { { .compatible = "fsl,qoriq-pcie-v2.2", }, { .compatible = "fsl,qoriq-pcie-v2.3", }, { .compatible = "fsl,qoriq-pcie-v2.4", }, + { .compatible = "fsl,qoriq-pcie-v3.0", }, /* * The following entries are for compatibility with older device diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h index c495c00..c81bf44 100644 --- a/arch/powerpc/sysdev/fsl_pci.h +++ b/arch/powerpc/sysdev/fsl_pci.h @@ -17,6 +17,7 @@ #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */ #define PCIE_LTSSM_L0 0x16 /* L0 state */ #define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */ +#define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */ #define PIWAR_EN 0x80000000 /* Enable */ #define PIWAR_PF 0x20000000 /* prefetch */ #define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */ @@ -89,6 +90,16 @@ struct ccsr_pci { __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */ __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */ __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */ + u8 res_e38[200]; + __be32 pdb_stat; /* 0x.f00 - PCIE Debug Status */ + u8 res_f04[16]; + __be32 pex_csr0; /* 0x.f14 - PEX Control/Status register 0*/ +#define PEX_CSR0_LTSSM_MASK 0xFC +#define PEX_CSR0_LTSSM_SHIFT 2 +#define PEX_CSR0_LTSSM_L0 0x11 + __be32 pex_csr1; /* 0x.f18 - PEX Control/Status register 1*/ + u8 res_f1c[228]; + }; extern int fsl_add_bridge(struct platform_device *pdev, int is_primary); -- 1.7.9.7 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 3/8] powerpc/fsl-booke: Support detection of page sizes on 2013-03-05 23:15 ` [PATCH 2/8] powerpc/85xx: Add support for FSL PCIe controller v3.0 Kumar Gala @ 2013-03-05 23:15 ` Kumar Gala 2013-03-05 23:15 ` [PATCH 4/8] powerpc/85xx: Add AltiVec support for e6500 Kumar Gala 2013-03-12 21:15 ` [PATCH 3/8] powerpc/fsl-booke: Support detection of page sizes on Kumar Gala 2013-03-12 21:15 ` [PATCH 2/8] powerpc/85xx: Add support for FSL PCIe controller v3.0 Kumar Gala 1 sibling, 2 replies; 19+ messages in thread From: Kumar Gala @ 2013-03-05 23:15 UTC (permalink / raw) To: linuxppc-dev The e6500 core used on T4240 and B4860 SoCs from FSL implements MMUv2 of the Power Book-E Architecture. However there are some minor differences between it and other Book-E implementations. Add support to parse SPRN_TLB1PS for the variable page sizes supported. In the future this should be expanded for more page sizes supported on e6500 as well as other MMU features. This patch is based on code from Scott Wood. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/mm/tlb_nohash.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c index df32a83..6888cad 100644 --- a/arch/powerpc/mm/tlb_nohash.c +++ b/arch/powerpc/mm/tlb_nohash.c @@ -414,9 +414,9 @@ static void setup_page_sizes(void) #ifdef CONFIG_PPC_FSL_BOOK3E unsigned int mmucfg = mfspr(SPRN_MMUCFG); + int fsl_mmu = mmu_has_feature(MMU_FTR_TYPE_FSL_E); - if (((mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) && - (mmu_has_feature(MMU_FTR_TYPE_FSL_E))) { + if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) { unsigned int tlb1cfg = mfspr(SPRN_TLB1CFG); unsigned int min_pg, max_pg; @@ -442,6 +442,20 @@ static void setup_page_sizes(void) goto no_indirect; } + + if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V2) { + u32 tlb1ps = mfspr(SPRN_TLB1PS); + + for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) { + struct mmu_psize_def *def = &mmu_psize_defs[psize]; + + if (tlb1ps & (1U << (def->shift - 10))) { + def->flags |= MMU_PAGE_SIZE_DIRECT; + } + } + + goto no_indirect; + } #endif tlb0cfg = mfspr(SPRN_TLB0CFG); -- 1.7.9.7 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 4/8] powerpc/85xx: Add AltiVec support for e6500 2013-03-05 23:15 ` [PATCH 3/8] powerpc/fsl-booke: Support detection of page sizes on Kumar Gala @ 2013-03-05 23:15 ` Kumar Gala 2013-03-05 23:15 ` [PATCH 5/8] powerpc/fsl-booke: Add initial silicon device tree for Kumar Gala 2013-03-12 21:15 ` [PATCH 3/8] powerpc/fsl-booke: Support detection of page sizes on Kumar Gala 1 sibling, 1 reply; 19+ messages in thread From: Kumar Gala @ 2013-03-05 23:15 UTC (permalink / raw) To: linuxppc-dev The e6500 core adds support for AltiVec on a Book-E class processor. Connect up all the various exception handling code and build config mechanisms to allow user spaces apps to utilize AltiVec. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/include/asm/cputable.h | 2 +- arch/powerpc/include/asm/kvm_asm.h | 4 +++ arch/powerpc/kernel/cpu_setup_fsl_booke.S | 14 +++++++++ arch/powerpc/kernel/cputable.c | 9 ++++-- arch/powerpc/kernel/exceptions-64e.S | 47 +++++++++++++++++++++++++++++ arch/powerpc/platforms/Kconfig.cputype | 2 +- 6 files changed, 73 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index fb3245e..f326444 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h @@ -374,7 +374,7 @@ extern const char *powerpc_base_platform; #define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ - CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV) + CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP) #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) /* 64-bit CPUs */ diff --git a/arch/powerpc/include/asm/kvm_asm.h b/arch/powerpc/include/asm/kvm_asm.h index aabcdba..b9dd382 100644 --- a/arch/powerpc/include/asm/kvm_asm.h +++ b/arch/powerpc/include/asm/kvm_asm.h @@ -67,6 +67,10 @@ #define BOOKE_INTERRUPT_HV_SYSCALL 40 #define BOOKE_INTERRUPT_HV_PRIV 41 +/* altivec */ +#define BOOKE_INTERRUPT_ALTIVEC_UNAVAIL 42 +#define BOOKE_INTERRUPT_ALTIVEC_ASSIST 43 + /* book3s */ #define BOOK3S_INTERRUPT_SYSTEM_RESET 0x100 diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S index dcd8819..c16729b 100644 --- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S +++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S @@ -53,6 +53,13 @@ _GLOBAL(__e500_dcache_setup) isync blr +_GLOBAL(__setup_cpu_e6500) + mflr r6 + bl .setup_altivec_ivors + bl __setup_cpu_e5500 + mtlr r6 + blr + #ifdef CONFIG_PPC32 _GLOBAL(__setup_cpu_e200) /* enable dedicated debug exception handling resources (Debug APU) */ @@ -107,6 +114,13 @@ _GLOBAL(__setup_cpu_e5500) #endif #ifdef CONFIG_PPC_BOOK3E_64 +_GLOBAL(__restore_cpu_e6500) + mflr r5 + bl .setup_altivec_ivors + bl __restore_cpu_e5500 + mtlr r5 + blr + _GLOBAL(__restore_cpu_e5500) mflr r4 bl __e500_icache_setup diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index 75a3d71..cc39139 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c @@ -74,7 +74,9 @@ extern void __restore_cpu_a2(void); #endif /* CONFIG_PPC64 */ #if defined(CONFIG_E500) extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec); +extern void __setup_cpu_e6500(unsigned long offset, struct cpu_spec* spec); extern void __restore_cpu_e5500(void); +extern void __restore_cpu_e6500(void); #endif /* CONFIG_E500 */ /* This table only contains "desktop" CPUs, it need to be filled with embedded @@ -2065,7 +2067,8 @@ static struct cpu_spec __initdata cpu_specs[] = { .pvr_value = 0x80400000, .cpu_name = "e6500", .cpu_features = CPU_FTRS_E6500, - .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, + .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU | + PPC_FEATURE_HAS_ALTIVEC_COMP, .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | MMU_FTR_USE_TLBILX, .icache_bsize = 64, @@ -2073,9 +2076,9 @@ static struct cpu_spec __initdata cpu_specs[] = { .num_pmcs = 4, .oprofile_cpu_type = "ppc/e6500", .oprofile_type = PPC_OPROFILE_FSL_EMB, - .cpu_setup = __setup_cpu_e5500, + .cpu_setup = __setup_cpu_e6500, #ifndef CONFIG_PPC32 - .cpu_restore = __restore_cpu_e5500, + .cpu_restore = __restore_cpu_e6500, #endif .machine_check = machine_check_e500mc, .platform = "ppce6500", diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S index ae54553..42a756e 100644 --- a/arch/powerpc/kernel/exceptions-64e.S +++ b/arch/powerpc/kernel/exceptions-64e.S @@ -299,6 +299,8 @@ interrupt_base_book3e: /* fake trap */ EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */ EXCEPTION_STUB(0x1c0, data_tlb_miss) EXCEPTION_STUB(0x1e0, instruction_tlb_miss) + EXCEPTION_STUB(0x200, altivec_unavailable) /* 0x0f20 */ + EXCEPTION_STUB(0x220, altivec_assist) /* 0x1700 */ EXCEPTION_STUB(0x260, perfmon) EXCEPTION_STUB(0x280, doorbell) EXCEPTION_STUB(0x2a0, doorbell_crit) @@ -395,6 +397,45 @@ interrupt_end_book3e: bl .kernel_fp_unavailable_exception b .ret_from_except +/* Altivec Unavailable Interrupt */ + START_EXCEPTION(altivec_unavailable); + NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_ALTIVEC_UNAVAIL, + PROLOG_ADDITION_NONE) + /* we can probably do a shorter exception entry for that one... */ + EXCEPTION_COMMON(0x200, PACA_EXGEN, INTS_KEEP) +#ifdef CONFIG_ALTIVEC +BEGIN_FTR_SECTION + ld r12,_MSR(r1) + andi. r0,r12,MSR_PR; + beq- 1f + bl .load_up_altivec + b fast_exception_return +1: +END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) +#endif + INTS_DISABLE + bl .save_nvgprs + addi r3,r1,STACK_FRAME_OVERHEAD + bl .altivec_unavailable_exception + b .ret_from_except + +/* AltiVec Assist */ + START_EXCEPTION(altivec_assist); + NORMAL_EXCEPTION_PROLOG(0x220, BOOKE_INTERRUPT_ALTIVEC_ASSIST, + PROLOG_ADDITION_NONE) + EXCEPTION_COMMON(0x220, PACA_EXGEN, INTS_DISABLE) + bl .save_nvgprs + addi r3,r1,STACK_FRAME_OVERHEAD +#ifdef CONFIG_ALTIVEC +BEGIN_FTR_SECTION + bl .altivec_assist_exception +END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) +#else + bl .unknown_exception +#endif + b .ret_from_except + + /* Decrementer Interrupt */ MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER, decrementer, .timer_interrupt, ACK_DEC) @@ -807,6 +848,7 @@ fast_exception_return: BAD_STACK_TRAMPOLINE(0x000) BAD_STACK_TRAMPOLINE(0x100) BAD_STACK_TRAMPOLINE(0x200) +BAD_STACK_TRAMPOLINE(0x220) BAD_STACK_TRAMPOLINE(0x260) BAD_STACK_TRAMPOLINE(0x280) BAD_STACK_TRAMPOLINE(0x2a0) @@ -1350,6 +1392,11 @@ _GLOBAL(__setup_base_ivors) blr +_GLOBAL(setup_altivec_ivors) + SET_IVOR(32, 0x200) /* AltiVec Unavailable */ + SET_IVOR(33, 0x220) /* AltiVec Assist */ + blr + _GLOBAL(setup_perfmon_ivor) SET_IVOR(35, 0x260) /* Performance Monitor */ blr diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype index cea2f09..6dfdb65 100644 --- a/arch/powerpc/platforms/Kconfig.cputype +++ b/arch/powerpc/platforms/Kconfig.cputype @@ -232,7 +232,7 @@ config PHYS_64BIT config ALTIVEC bool "AltiVec Support" - depends on 6xx || POWER4 + depends on 6xx || POWER4 || (PPC_E500MC && PPC64) ---help--- This option enables kernel support for the Altivec extensions to the PowerPC processor. The kernel currently supports saving and restoring -- 1.7.9.7 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 5/8] powerpc/fsl-booke: Add initial silicon device tree for 2013-03-05 23:15 ` [PATCH 4/8] powerpc/85xx: Add AltiVec support for e6500 Kumar Gala @ 2013-03-05 23:15 ` Kumar Gala 2013-03-05 23:15 ` [PATCH 6/8] powerpc/fsl-booke: Add initial T4240QDS board device Kumar Gala ` (2 more replies) 0 siblings, 3 replies; 19+ messages in thread From: Kumar Gala @ 2013-03-05 23:15 UTC (permalink / raw) To: linuxppc-dev Enable a baseline T4240 SoC to boot. There are several things missing from the device trees for T4240: * Thread support on e6500 * Proper PAMU topology information * DPAA related nodes (Qman, Bman, Fman, Rman, DCE) * Prefetch Manager * Thermal monitor unit * Interlaken Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Vakul Garg <vakul@freescale.com> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/boot/dts/fsl/qoriq-gpio-1.dtsi | 41 ++++ arch/powerpc/boot/dts/fsl/qoriq-gpio-2.dtsi | 41 ++++ arch/powerpc/boot/dts/fsl/qoriq-gpio-3.dtsi | 41 ++++ arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 311 +++++++++++++++++++++++++++ arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi | 129 +++++++++++ 5 files changed, 563 insertions(+) create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-gpio-1.dtsi create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-gpio-2.dtsi create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-gpio-3.dtsi create mode 100644 arch/powerpc/boot/dts/fsl/t4240si-post.dtsi create mode 100644 arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi diff --git a/arch/powerpc/boot/dts/fsl/qoriq-gpio-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-gpio-1.dtsi new file mode 100644 index 0000000..c2f9cda --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-gpio-1.dtsi @@ -0,0 +1,41 @@ +/* + * QorIQ GPIO device tree stub [ controller @ offset 0x131000 ] + * + * Copyright 2013 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +gpio1: gpio@131000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x131000 0x1000>; + interrupts = <54 2 0 0>; + #gpio-cells = <2>; + gpio-controller; +}; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-gpio-2.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-gpio-2.dtsi new file mode 100644 index 0000000..33f3ccb --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-gpio-2.dtsi @@ -0,0 +1,41 @@ +/* + * QorIQ GPIO device tree stub [ controller @ offset 0x132000 ] + * + * Copyright 2013 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +gpio2: gpio@132000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x132000 0x1000>; + interrupts = <86 2 0 0>; + #gpio-cells = <2>; + gpio-controller; +}; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-gpio-3.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-gpio-3.dtsi new file mode 100644 index 0000000..86954e9 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-gpio-3.dtsi @@ -0,0 +1,41 @@ +/* + * QorIQ GPIO device tree stub [ controller @ offset 0x133000 ] + * + * Copyright 2013 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +gpio3: gpio@133000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x133000 0x1000>; + interrupts = <87 2 0 0>; + #gpio-cells = <2>; + gpio-controller; +}; diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi new file mode 100644 index 0000000..a0cc3fb --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi @@ -0,0 +1,311 @@ +/* + * T4240 Silicon/SoC Device Tree Source (post include) + * + * Copyright 2012 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,ifc", "simple-bus"; + interrupts = <25 2 0 0>; +}; + +/* controller at 0x240000 */ +&pci0 { + compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; + device_type = "pci"; + #size-cells = <2>; + #address-cells = <3>; + bus-range = <0x0 0xff>; + clock-frequency = <33333333>; + interrupts = <20 2 0 0>; + pcie@0 { + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + interrupts = <20 2 0 0>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 40 1 0 0 + 0000 0 0 2 &mpic 1 1 0 0 + 0000 0 0 3 &mpic 2 1 0 0 + 0000 0 0 4 &mpic 3 1 0 0 + >; + }; +}; + +/* controller at 0x250000 */ +&pci1 { + compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; + device_type = "pci"; + #size-cells = <2>; + #address-cells = <3>; + bus-range = <0 0xff>; + clock-frequency = <33333333>; + interrupts = <21 2 0 0>; + pcie@0 { + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + interrupts = <21 2 0 0>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 41 1 0 0 + 0000 0 0 2 &mpic 5 1 0 0 + 0000 0 0 3 &mpic 6 1 0 0 + 0000 0 0 4 &mpic 7 1 0 0 + >; + }; +}; + +/* controller at 0x260000 */ +&pci2 { + compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; + device_type = "pci"; + #size-cells = <2>; + #address-cells = <3>; + bus-range = <0x0 0xff>; + clock-frequency = <33333333>; + interrupts = <22 2 0 0>; + pcie@0 { + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + interrupts = <22 2 0 0>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 42 1 0 0 + 0000 0 0 2 &mpic 9 1 0 0 + 0000 0 0 3 &mpic 10 1 0 0 + 0000 0 0 4 &mpic 11 1 0 0 + >; + }; +}; + +/* controller at 0x270000 */ +&pci3 { + compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; + device_type = "pci"; + #size-cells = <2>; + #address-cells = <3>; + bus-range = <0x0 0xff>; + clock-frequency = <33333333>; + interrupts = <23 2 0 0>; + pcie@0 { + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + interrupts = <23 2 0 0>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 43 1 0 0 + 0000 0 0 2 &mpic 0 1 0 0 + 0000 0 0 3 &mpic 4 1 0 0 + 0000 0 0 4 &mpic 8 1 0 0 + >; + }; +}; + +&rio { + compatible = "fsl,srio"; + interrupts = <16 2 1 11>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + port1 { + #address-cells = <2>; + #size-cells = <2>; + cell-index = <1>; + }; + + port2 { + #address-cells = <2>; + #size-cells = <2>; + cell-index = <2>; + }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + + soc-sram-error { + compatible = "fsl,soc-sram-error"; + interrupts = <16 2 1 29>; + }; + + corenet-law@0 { + compatible = "fsl,corenet-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <32>; + }; + + ddr1: memory-controller@8000 { + compatible = "fsl,qoriq-memory-controller-v4.7", + "fsl,qoriq-memory-controller"; + reg = <0x8000 0x1000>; + interrupts = <16 2 1 23>; + }; + + ddr2: memory-controller@9000 { + compatible = "fsl,qoriq-memory-controller-v4.7", + "fsl,qoriq-memory-controller"; + reg = <0x9000 0x1000>; + interrupts = <16 2 1 22>; + }; + + ddr3: memory-controller@a000 { + compatible = "fsl,qoriq-memory-controller-v4.7", + "fsl,qoriq-memory-controller"; + reg = <0xa000 0x1000>; + interrupts = <16 2 1 21>; + }; + + cpc: l3-cache-controller@10000 { + compatible = "fsl,t4240-l3-cache-controller", "cache"; + reg = <0x10000 0x1000 + 0x11000 0x1000 + 0x12000 0x1000>; + interrupts = <16 2 1 27 + 16 2 1 26 + 16 2 1 25>; + }; + + corenet-cf@18000 { + compatible = "fsl,corenet-cf"; + reg = <0x18000 0x1000>; + interrupts = <16 2 1 31>; + fsl,ccf-num-csdids = <32>; + fsl,ccf-num-snoopids = <32>; + }; + + iommu@20000 { + compatible = "fsl,pamu-v1.0", "fsl,pamu"; + reg = <0x20000 0x6000>; + interrupts = < + 24 2 0 0 + 16 2 1 30>; + }; + +/include/ "qoriq-mpic.dtsi" + + guts: global-utilities@e0000 { + compatible = "fsl,t4240-device-config"; + reg = <0xe0000 0xe00>; + fsl,has-rstcr; + fsl,liodn-bits = <12>; + }; + + clockgen: global-utilities@e1000 { + compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2"; + reg = <0xe1000 0x1000>; + }; + + rcpm: global-utilities@e2000 { + compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2"; + reg = <0xe2000 0x1000>; + }; + + sfp: sfp@e8000 { + compatible = "fsl,t4240-sfp"; + reg = <0xe8000 0x1000>; + }; + + serdes: serdes@ea000 { + compatible = "fsl,t4240-serdes"; + reg = <0xea000 0x4000>; + }; + +/include/ "qoriq-dma-0.dtsi" +/include/ "qoriq-dma-1.dtsi" + +/include/ "qoriq-espi-0.dtsi" + spi@110000 { + fsl,espi-num-chipselects = <4>; + }; + +/include/ "qoriq-esdhc-0.dtsi" + sdhc@114000 { + compatible = "fsl,t4240-esdhc", "fsl,esdhc"; + sdhci,auto-cmd12; + }; +/include/ "qoriq-i2c-0.dtsi" +/include/ "qoriq-i2c-1.dtsi" +/include/ "qoriq-duart-0.dtsi" +/include/ "qoriq-duart-1.dtsi" +/include/ "qoriq-gpio-0.dtsi" +/include/ "qoriq-gpio-1.dtsi" +/include/ "qoriq-gpio-2.dtsi" +/include/ "qoriq-gpio-3.dtsi" +/include/ "qoriq-usb2-mph-0.dtsi" + usb0: usb@210000 { + compatible = "fsl-usb2-mph-v2.4", "fsl-usb2-mph"; + phy_type = "utmi"; + port0; + }; +/include/ "qoriq-usb2-dr-0.dtsi" + usb1: usb@211000 { + compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr"; + dr_mode = "host"; + phy_type = "utmi"; + }; +/include/ "qoriq-sata2-0.dtsi" +/include/ "qoriq-sata2-1.dtsi" +/include/ "qoriq-sec5.0-0.dtsi" + + L2_1: l2-cache-controller@c20000 { + compatible = "fsl,t4240-l2-cache-controller"; + reg = <0xc20000 0x40000>; + next-level-cache = <&cpc>; + }; + L2_2: l2-cache-controller@c60000 { + compatible = "fsl,t4240-l2-cache-controller"; + reg = <0xc60000 0x40000>; + next-level-cache = <&cpc>; + }; + L2_3: l2-cache-controller@ca0000 { + compatible = "fsl,t4240-l2-cache-controller"; + reg = <0xca0000 0x40000>; + next-level-cache = <&cpc>; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi new file mode 100644 index 0000000..0ddf072 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi @@ -0,0 +1,129 @@ +/* + * T4240 Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2012 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +/include/ "e6500_power_isa.dtsi" + +/ { + compatible = "fsl,T4240"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + aliases { + ccsr = &soc; + + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + crypto = &crypto; + pci0 = &pci0; + pci1 = &pci1; + pci2 = &pci2; + pci3 = &pci3; + dma0 = &dma0; + dma1 = &dma1; + sdhc = &sdhc; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,e6500@0 { + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2_1>; + }; + PowerPC,e6500@1 { + device_type = "cpu"; + reg = <2>; + next-level-cache = <&L2_1>; + }; + PowerPC,e6500@2 { + device_type = "cpu"; + reg = <4>; + next-level-cache = <&L2_1>; + }; + PowerPC,e6500@3 { + device_type = "cpu"; + reg = <6>; + next-level-cache = <&L2_1>; + }; + + PowerPC,e6500@4 { + device_type = "cpu"; + reg = <8>; + next-level-cache = <&L2_2>; + }; + PowerPC,e6500@5 { + device_type = "cpu"; + reg = <10>; + next-level-cache = <&L2_2>; + }; + PowerPC,e6500@6 { + device_type = "cpu"; + reg = <12>; + next-level-cache = <&L2_2>; + }; + PowerPC,e6500@7 { + device_type = "cpu"; + reg = <14>; + next-level-cache = <&L2_2>; + }; + + PowerPC,e6500@8 { + device_type = "cpu"; + reg = <16>; + next-level-cache = <&L2_3>; + }; + PowerPC,e6500@9 { + device_type = "cpu"; + reg = <18>; + next-level-cache = <&L2_3>; + }; + PowerPC,e6500@10 { + device_type = "cpu"; + reg = <20>; + next-level-cache = <&L2_3>; + }; + PowerPC,e6500@11 { + device_type = "cpu"; + reg = <22>; + next-level-cache = <&L2_3>; + }; + }; +}; -- 1.7.9.7 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 6/8] powerpc/fsl-booke: Add initial T4240QDS board device 2013-03-05 23:15 ` [PATCH 5/8] powerpc/fsl-booke: Add initial silicon device tree for Kumar Gala @ 2013-03-05 23:15 ` Kumar Gala 2013-03-05 23:15 ` [PATCH 7/8] powerpc/fsl-booke: Add initial T4240QDS board support Kumar Gala 2013-03-12 21:15 ` [PATCH 6/8] powerpc/fsl-booke: Add initial T4240QDS board device Kumar Gala 2013-03-06 0:15 ` [PATCH 5/8] powerpc/fsl-booke: Add initial silicon device tree for Scott Wood 2013-03-06 11:02 ` Roy Zang 2 siblings, 2 replies; 19+ messages in thread From: Kumar Gala @ 2013-03-05 23:15 UTC (permalink / raw) To: linuxppc-dev Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/boot/dts/t4240qds.dts | 220 ++++++++++++++++++++++++++++++++++++ 1 file changed, 220 insertions(+) create mode 100644 arch/powerpc/boot/dts/t4240qds.dts diff --git a/arch/powerpc/boot/dts/t4240qds.dts b/arch/powerpc/boot/dts/t4240qds.dts new file mode 100644 index 0000000..83b479f --- /dev/null +++ b/arch/powerpc/boot/dts/t4240qds.dts @@ -0,0 +1,220 @@ +/* + * T4240QDS Device Tree Source + * + * Copyright 2012 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/include/ "fsl/t4240si-pre.dtsi" + +/ { + model = "fsl,T4240QDS"; + compatible = "fsl,T4240QDS"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + ifc: localbus@ffe124000 { + reg = <0xf 0xfe124000 0 0x2000>; + ranges = <0 0 0xf 0xe8000000 0x08000000 + 2 0 0xf 0xff800000 0x00010000 + 3 0 0xf 0xffdf0000 0x00008000>; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + + bank-width = <2>; + device-width = <1>; + }; + + nand@2,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,ifc-nand"; + reg = <0x2 0x0 0x10000>; + + partition@0 { + /* This location must not be altered */ + /* 1MB for u-boot Bootloader Image */ + reg = <0x0 0x00100000>; + label = "NAND U-Boot Image"; + read-only; + }; + + partition@100000 { + /* 1MB for DTB Image */ + reg = <0x00100000 0x00100000>; + label = "NAND DTB Image"; + }; + + partition@200000 { + /* 10MB for Linux Kernel Image */ + reg = <0x00200000 0x00A00000>; + label = "NAND Linux Kernel Image"; + }; + + partition@C00000 { + /* 500MB for Root file System Image */ + reg = <0x00c00000 0x1F400000>; + label = "NAND RFS Image"; + }; + }; + + board-control@3,0 { + compatible = "fsl,t4240qds-fpga", "fsl,fpga-qixis"; + reg = <3 0 0x300>; + }; + }; + + memory { + device_type = "memory"; + }; + + soc: soc@ffe000000 { + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; + reg = <0xf 0xfe000000 0 0x00001000>; + spi@110000 { + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25wf040"; + reg = <0>; + spi-max-frequency = <40000000>; /* input clock */ + }; + }; + + i2c@118000 { + eeprom@51 { + compatible = "at24,24c256"; + reg = <0x51>; + }; + eeprom@52 { + compatible = "at24,24c256"; + reg = <0x52>; + }; + eeprom@53 { + compatible = "at24,24c256"; + reg = <0x53>; + }; + eeprom@54 { + compatible = "at24,24c256"; + reg = <0x54>; + }; + eeprom@55 { + compatible = "at24,24c256"; + reg = <0x55>; + }; + eeprom@56 { + compatible = "at24,24c256"; + reg = <0x56>; + }; + rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + interrupts = <0x1 0x1 0 0>; + }; + }; + }; + + pci0: pcie@ffe240000 { + reg = <0xf 0xfe240000 0 0x10000>; + ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 + 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; + pcie@0 { + ranges = <0x02000000 0 0xe0000000 + 0x02000000 0 0xe0000000 + 0 0x20000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; + + pci1: pcie@ffe250000 { + reg = <0xf 0xfe250000 0 0x10000>; + ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 + 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; + pcie@0 { + ranges = <0x02000000 0 0xe0000000 + 0x02000000 0 0xe0000000 + 0 0x20000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; + + pci2: pcie@ffe260000 { + reg = <0xf 0xfe260000 0 0x1000>; + ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 + 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; + pcie@0 { + ranges = <0x02000000 0 0xe0000000 + 0x02000000 0 0xe0000000 + 0 0x20000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; + + pci3: pcie@ffe270000 { + reg = <0xf 0xfe270000 0 0x10000>; + ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000 + 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; + pcie@0 { + ranges = <0x02000000 0 0xe0000000 + 0x02000000 0 0xe0000000 + 0 0x20000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; + rio: rapidio@ffe0c0000 { + reg = <0xf 0xfe0c0000 0 0x11000>; + + port1 { + ranges = <0 0 0xc 0x20000000 0 0x10000000>; + }; + port2 { + ranges = <0 0 0xc 0x30000000 0 0x10000000>; + }; + }; +}; + +/include/ "fsl/t4240si-post.dtsi" -- 1.7.9.7 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 7/8] powerpc/fsl-booke: Add initial T4240QDS board support 2013-03-05 23:15 ` [PATCH 6/8] powerpc/fsl-booke: Add initial T4240QDS board device Kumar Gala @ 2013-03-05 23:15 ` Kumar Gala 2013-03-05 23:16 ` [PATCH 8/8] powerpc/85xx: Update corenet64_smp_defconfig for T4240 Kumar Gala 2013-03-12 21:16 ` [PATCH 7/8] powerpc/fsl-booke: Add initial T4240QDS board support Kumar Gala 2013-03-12 21:15 ` [PATCH 6/8] powerpc/fsl-booke: Add initial T4240QDS board device Kumar Gala 1 sibling, 2 replies; 19+ messages in thread From: Kumar Gala @ 2013-03-05 23:15 UTC (permalink / raw) To: linuxppc-dev Some minor changes to the common corenet_ds.c code are needed to support the T4240QDS: * Add support for "fsl,qoriq-pcie-v3.0" controller * Bump max # of IRQs to 512 (T4240 supports more interrupts than previous SoCs). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/platforms/85xx/Kconfig | 17 ++++++ arch/powerpc/platforms/85xx/Makefile | 1 + arch/powerpc/platforms/85xx/corenet_ds.c | 5 +- arch/powerpc/platforms/85xx/t4240_qds.c | 98 ++++++++++++++++++++++++++++++ 4 files changed, 120 insertions(+), 1 deletion(-) create mode 100644 arch/powerpc/platforms/85xx/t4240_qds.c diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig index a0dcd57..31dc066 100644 --- a/arch/powerpc/platforms/85xx/Kconfig +++ b/arch/powerpc/platforms/85xx/Kconfig @@ -305,6 +305,23 @@ config PPC_QEMU_E500 unset based on the emulated CPU (or actual host CPU in the case of KVM). +if PPC64 + +config T4240_QDS + bool "Freescale T4240 QDS" + select DEFAULT_UIMAGE + select E500 + select PPC_E500MC + select PHYS_64BIT + select SWIOTLB + select ARCH_REQUIRE_GPIOLIB + select GPIO_MPC8XXX + select HAS_RAPIDIO + select PPC_EPAPR_HV_PIC + help + This option enables support for the T4240 QDS board + +endif endif # FSL_SOC_BOOKE config TQM85xx diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile index 07d0dbb..712e233 100644 --- a/arch/powerpc/platforms/85xx/Makefile +++ b/arch/powerpc/platforms/85xx/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o obj-$(CONFIG_P5040_DS) += p5040_ds.o corenet_ds.o +obj-$(CONFIG_T4240_QDS) += t4240_qds.o corenet_ds.o obj-$(CONFIG_STX_GP3) += stx_gp3.o obj-$(CONFIG_TQM85xx) += tqm85xx.o obj-$(CONFIG_SBC8548) += sbc8548.o diff --git a/arch/powerpc/platforms/85xx/corenet_ds.c b/arch/powerpc/platforms/85xx/corenet_ds.c index 6f355d8..c59c617 100644 --- a/arch/powerpc/platforms/85xx/corenet_ds.c +++ b/arch/powerpc/platforms/85xx/corenet_ds.c @@ -40,7 +40,7 @@ void __init corenet_ds_pic_init(void) if (ppc_md.get_irq == mpic_get_coreint_irq) flags |= MPIC_ENABLE_COREINT; - mpic = mpic_alloc(NULL, 0, flags, 0, 256, " OpenPIC "); + mpic = mpic_alloc(NULL, 0, flags, 0, 512, " OpenPIC "); BUG_ON(mpic == NULL); mpic_init(mpic); @@ -83,6 +83,9 @@ static const struct of_device_id of_device_ids[] = { { .compatible = "fsl,qoriq-pcie-v2.4", }, + { + .compatible = "fsl,qoriq-pcie-v3.0", + }, /* The following two are for the Freescale hypervisor */ { .name = "hypervisor", diff --git a/arch/powerpc/platforms/85xx/t4240_qds.c b/arch/powerpc/platforms/85xx/t4240_qds.c new file mode 100644 index 0000000..5998e9f --- /dev/null +++ b/arch/powerpc/platforms/85xx/t4240_qds.c @@ -0,0 +1,98 @@ +/* + * T4240 QDS Setup + * + * Maintained by Kumar Gala (see MAINTAINERS for contact information) + * + * Copyright 2012 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <linux/kernel.h> +#include <linux/pci.h> +#include <linux/kdev_t.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/phy.h> + +#include <asm/time.h> +#include <asm/machdep.h> +#include <asm/pci-bridge.h> +#include <mm/mmu_decl.h> +#include <asm/prom.h> +#include <asm/udbg.h> +#include <asm/mpic.h> + +#include <linux/of_platform.h> +#include <sysdev/fsl_soc.h> +#include <sysdev/fsl_pci.h> +#include <asm/ehv_pic.h> + +#include "corenet_ds.h" + +/* + * Called very early, device-tree isn't unflattened + */ +static int __init t4240_qds_probe(void) +{ + unsigned long root = of_get_flat_dt_root(); +#ifdef CONFIG_SMP + extern struct smp_ops_t smp_85xx_ops; +#endif + + if (of_flat_dt_is_compatible(root, "fsl,T4240QDS")) + return 1; + + /* Check if we're running under the Freescale hypervisor */ + if (of_flat_dt_is_compatible(root, "fsl,T4240QDS-hv")) { + ppc_md.init_IRQ = ehv_pic_init; + ppc_md.get_irq = ehv_pic_get_irq; + ppc_md.restart = fsl_hv_restart; + ppc_md.power_off = fsl_hv_halt; + ppc_md.halt = fsl_hv_halt; +#ifdef CONFIG_SMP + /* + * Disable the timebase sync operations because we can't write + * to the timebase registers under the hypervisor. + */ + smp_85xx_ops.give_timebase = NULL; + smp_85xx_ops.take_timebase = NULL; +#endif + return 1; + } + + return 0; +} + +define_machine(t4240_qds) { + .name = "T4240 QDS", + .probe = t4240_qds_probe, + .setup_arch = corenet_ds_setup_arch, + .init_IRQ = corenet_ds_pic_init, +#ifdef CONFIG_PCI + .pcibios_fixup_bus = fsl_pcibios_fixup_bus, +#endif +/* coreint doesn't play nice with lazy EE, use legacy mpic for now */ +#ifdef CONFIG_PPC64 + .get_irq = mpic_get_irq, +#else + .get_irq = mpic_get_coreint_irq, +#endif + .restart = fsl_rstcr_restart, + .calibrate_decr = generic_calibrate_decr, + .progress = udbg_progress, +#ifdef CONFIG_PPC64 + .power_save = book3e_idle, +#else + .power_save = e500_idle, +#endif +}; + +machine_arch_initcall(t4240_qds, corenet_ds_publish_devices); + +#ifdef CONFIG_SWIOTLB +machine_arch_initcall(t4240_qds, swiotlb_setup_bus_notifier); +#endif -- 1.7.9.7 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 8/8] powerpc/85xx: Update corenet64_smp_defconfig for T4240 2013-03-05 23:15 ` [PATCH 7/8] powerpc/fsl-booke: Add initial T4240QDS board support Kumar Gala @ 2013-03-05 23:16 ` Kumar Gala 2013-03-12 21:15 ` Kumar Gala 2013-03-12 21:16 ` [PATCH 7/8] powerpc/fsl-booke: Add initial T4240QDS board support Kumar Gala 1 sibling, 1 reply; 19+ messages in thread From: Kumar Gala @ 2013-03-05 23:16 UTC (permalink / raw) To: linuxppc-dev * Add support for up to 24 cores on T4240 (includes threads) * Enable AltiVec support (on T4240) * Add T4240QDS board into build * Other changes are due to general kernel update of defconfig Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/configs/corenet64_smp_defconfig | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig index 3d139fa..c3da860 100644 --- a/arch/powerpc/configs/corenet64_smp_defconfig +++ b/arch/powerpc/configs/corenet64_smp_defconfig @@ -1,14 +1,13 @@ CONFIG_PPC64=y CONFIG_PPC_BOOK3E_64=y -# CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set +CONFIG_ALTIVEC=y CONFIG_SMP=y -CONFIG_NR_CPUS=2 -CONFIG_EXPERIMENTAL=y +CONFIG_NR_CPUS=24 CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y CONFIG_IRQ_DOMAIN_DEBUG=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_BSD_PROCESS_ACCT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 @@ -24,6 +23,7 @@ CONFIG_PARTITION_ADVANCED=y CONFIG_MAC_PARTITION=y CONFIG_P5020_DS=y CONFIG_P5040_DS=y +CONFIG_T4240_QDS=y # CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set CONFIG_BINFMT_MISC=m CONFIG_PCIEPORTBUS=y @@ -140,6 +140,5 @@ CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_DEV_FSL_CAAM=y -- 1.7.9.7 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH 8/8] powerpc/85xx: Update corenet64_smp_defconfig for T4240 2013-03-05 23:16 ` [PATCH 8/8] powerpc/85xx: Update corenet64_smp_defconfig for T4240 Kumar Gala @ 2013-03-12 21:15 ` Kumar Gala 0 siblings, 0 replies; 19+ messages in thread From: Kumar Gala @ 2013-03-12 21:15 UTC (permalink / raw) To: linuxppc-dev On Mar 5, 2013, at 5:16 PM, Kumar Gala wrote: > * Add support for up to 24 cores on T4240 (includes threads) > * Enable AltiVec support (on T4240) > * Add T4240QDS board into build > * Other changes are due to general kernel update of defconfig > > Signed-off-by: Kumar Gala <galak@kernel.crashing.org> > --- > arch/powerpc/configs/corenet64_smp_defconfig | 9 ++++----- > 1 file changed, 4 insertions(+), 5 deletions(-) applied to next - k ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 7/8] powerpc/fsl-booke: Add initial T4240QDS board support 2013-03-05 23:15 ` [PATCH 7/8] powerpc/fsl-booke: Add initial T4240QDS board support Kumar Gala 2013-03-05 23:16 ` [PATCH 8/8] powerpc/85xx: Update corenet64_smp_defconfig for T4240 Kumar Gala @ 2013-03-12 21:16 ` Kumar Gala 1 sibling, 0 replies; 19+ messages in thread From: Kumar Gala @ 2013-03-12 21:16 UTC (permalink / raw) To: linuxppc-dev On Mar 5, 2013, at 5:15 PM, Kumar Gala wrote: > Some minor changes to the common corenet_ds.c code are needed to = support > the T4240QDS: > * Add support for "fsl,qoriq-pcie-v3.0" controller > * Bump max # of IRQs to 512 (T4240 supports more interrupts than > previous SoCs). >=20 > Signed-off-by: Kumar Gala <galak@kernel.crashing.org> > --- > arch/powerpc/platforms/85xx/Kconfig | 17 ++++++ > arch/powerpc/platforms/85xx/Makefile | 1 + > arch/powerpc/platforms/85xx/corenet_ds.c | 5 +- > arch/powerpc/platforms/85xx/t4240_qds.c | 98 = ++++++++++++++++++++++++++++++ > 4 files changed, 120 insertions(+), 1 deletion(-) > create mode 100644 arch/powerpc/platforms/85xx/t4240_qds.c applied to next - k= ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 6/8] powerpc/fsl-booke: Add initial T4240QDS board device 2013-03-05 23:15 ` [PATCH 6/8] powerpc/fsl-booke: Add initial T4240QDS board device Kumar Gala 2013-03-05 23:15 ` [PATCH 7/8] powerpc/fsl-booke: Add initial T4240QDS board support Kumar Gala @ 2013-03-12 21:15 ` Kumar Gala 1 sibling, 0 replies; 19+ messages in thread From: Kumar Gala @ 2013-03-12 21:15 UTC (permalink / raw) To: linuxppc-dev On Mar 5, 2013, at 5:15 PM, Kumar Gala wrote: > Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> > Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> > Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> > Signed-off-by: Andy Fleming <afleming@freescale.com> > Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> > Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> > Signed-off-by: Scott Wood <scottwood@freescale.com> > Signed-off-by: Kumar Gala <galak@kernel.crashing.org> > --- > arch/powerpc/boot/dts/t4240qds.dts | 220 = ++++++++++++++++++++++++++++++++++++ > 1 file changed, 220 insertions(+) > create mode 100644 arch/powerpc/boot/dts/t4240qds.dts applied to next - k= ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 5/8] powerpc/fsl-booke: Add initial silicon device tree for 2013-03-05 23:15 ` [PATCH 5/8] powerpc/fsl-booke: Add initial silicon device tree for Kumar Gala 2013-03-05 23:15 ` [PATCH 6/8] powerpc/fsl-booke: Add initial T4240QDS board device Kumar Gala @ 2013-03-06 0:15 ` Scott Wood 2013-03-07 17:09 ` Kumar Gala 2013-03-06 11:02 ` Roy Zang 2 siblings, 1 reply; 19+ messages in thread From: Scott Wood @ 2013-03-06 0:15 UTC (permalink / raw) To: Kumar Gala; +Cc: linuxppc-dev On 03/05/2013 05:15:57 PM, Kumar Gala wrote: > Enable a baseline T4240 SoC to boot. There are several things missing > from the device trees for T4240: >=20 > * Thread support on e6500 Why did threads get removed from the device tree? It's supposed to =20 describe hardware, not what Linux currently supports. > * Proper PAMU topology information > * DPAA related nodes (Qman, Bman, Fman, Rman, DCE) > * Prefetch Manager > * Thermal monitor unit > * Interlaken The dts should be marked preliminary somehow -- we really should get =20 out of the habit of letting device nodes trickle in as drivers get =20 added. > +/* controller at 0x240000 */ > +&pci0 { > + compatible =3D "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; We have a version register -- do we really need to keep sticking the =20 version number in the compatible? Note that we've had device trees =20 that specified the version incorrectly in the past. > + device_type =3D "pci"; > + #size-cells =3D <2>; > + #address-cells =3D <3>; > + bus-range =3D <0x0 0xff>; > + clock-frequency =3D <33333333>; This clock-frequency is not correct (I doubt it's needed at all). > + PowerPC,e6500@1 { > + device_type =3D "cpu"; > + reg =3D <2>; > + next-level-cache =3D <&L2_1>; > + }; > + PowerPC,e6500@2 { > + device_type =3D "cpu"; > + reg =3D <4>; > + next-level-cache =3D <&L2_1>; > + }; > + PowerPC,e6500@3 { > + device_type =3D "cpu"; > + reg =3D <6>; > + next-level-cache =3D <&L2_1>; > + }; > + > + PowerPC,e6500@4 { > + device_type =3D "cpu"; > + reg =3D <8>; > + next-level-cache =3D <&L2_2>; > + }; Inconsistent whitespace. As usual, the pre/post split is unnecessary. Everything in it can go =20 in post. -Scott= ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 5/8] powerpc/fsl-booke: Add initial silicon device tree for 2013-03-06 0:15 ` [PATCH 5/8] powerpc/fsl-booke: Add initial silicon device tree for Scott Wood @ 2013-03-07 17:09 ` Kumar Gala 2013-03-07 17:47 ` Scott Wood 0 siblings, 1 reply; 19+ messages in thread From: Kumar Gala @ 2013-03-07 17:09 UTC (permalink / raw) To: Scott Wood; +Cc: linuxppc-dev On Mar 5, 2013, at 6:15 PM, Scott Wood wrote: > On 03/05/2013 05:15:57 PM, Kumar Gala wrote: >> Enable a baseline T4240 SoC to boot. There are several things = missing >> from the device trees for T4240: >> * Thread support on e6500 >=20 > Why did threads get removed from the device tree? It's supposed to = describe hardware, not what Linux currently supports. will fix, was concerned if we'd be able to boot if they exited >=20 >> * Proper PAMU topology information >> * DPAA related nodes (Qman, Bman, Fman, Rman, DCE) >> * Prefetch Manager >> * Thermal monitor unit >> * Interlaken >=20 > The dts should be marked preliminary somehow -- we really should get = out of the habit of letting device nodes trickle in as drivers get = added. agreed but forward progress always gets in the way >=20 >> +/* controller at 0x240000 */ >> +&pci0 { >> + compatible =3D "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; >=20 > We have a version register -- do we really need to keep sticking the = version number in the compatible? Note that we've had device trees that = specified the version incorrectly in the past. >=20 >> + device_type =3D "pci"; >> + #size-cells =3D <2>; >> + #address-cells =3D <3>; >> + bus-range =3D <0x0 0xff>; >> + clock-frequency =3D <33333333>; >=20 > This clock-frequency is not correct (I doubt it's needed at all). I can zero the field, but its spec'd by pci binding >=20 >> + PowerPC,e6500@1 { >> + device_type =3D "cpu"; >> + reg =3D <2>; >> + next-level-cache =3D <&L2_1>; >> + }; >> + PowerPC,e6500@2 { >> + device_type =3D "cpu"; >> + reg =3D <4>; >> + next-level-cache =3D <&L2_1>; >> + }; >> + PowerPC,e6500@3 { >> + device_type =3D "cpu"; >> + reg =3D <6>; >> + next-level-cache =3D <&L2_1>; >> + }; >> + >> + PowerPC,e6500@4 { >> + device_type =3D "cpu"; >> + reg =3D <8>; >> + next-level-cache =3D <&L2_2>; >> + }; >=20 > Inconsistent whitespace. will kill the whitespace. > As usual, the pre/post split is unnecessary. Everything in it can go = in post. >=20 > -Scott ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 5/8] powerpc/fsl-booke: Add initial silicon device tree for 2013-03-07 17:09 ` Kumar Gala @ 2013-03-07 17:47 ` Scott Wood 2013-03-07 19:53 ` Kumar Gala 0 siblings, 1 reply; 19+ messages in thread From: Scott Wood @ 2013-03-07 17:47 UTC (permalink / raw) To: Kumar Gala; +Cc: linuxppc-dev On 03/07/2013 11:09:50 AM, Kumar Gala wrote: >=20 > On Mar 5, 2013, at 6:15 PM, Scott Wood wrote: >=20 > > On 03/05/2013 05:15:57 PM, Kumar Gala wrote: > >> Enable a baseline T4240 SoC to boot. There are several things =20 > missing > >> from the device trees for T4240: > >> * Thread support on e6500 > > > > Why did threads get removed from the device tree? It's supposed to =20 > describe hardware, not what Linux currently supports. >=20 > will fix, was concerned if we'd be able to boot if they exited I don't think it'd be a problem (and if it is, then fix Linux). > >> + device_type =3D "pci"; > >> + #size-cells =3D <2>; > >> + #address-cells =3D <3>; > >> + bus-range =3D <0x0 0xff>; > >> + clock-frequency =3D <33333333>; > > > > This clock-frequency is not correct (I doubt it's needed at all). >=20 > I can zero the field, but its spec'd by pci binding If we aren't going to put a correct value in, is zero better than =20 omitting it entirely? There are other properties in the PCI binding that we don't have, such =20 as slot-names. I don't see any language in the PCI binding that says =20 one is required but the other isn't. And shouldn't we be using the PCI express binding (device_type =3D =20 "pciex", or just get rid of it since this isn't real OF)? -Scott= ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 5/8] powerpc/fsl-booke: Add initial silicon device tree for 2013-03-07 17:47 ` Scott Wood @ 2013-03-07 19:53 ` Kumar Gala 0 siblings, 0 replies; 19+ messages in thread From: Kumar Gala @ 2013-03-07 19:53 UTC (permalink / raw) To: Scott Wood; +Cc: linuxppc-dev On Mar 7, 2013, at 11:47 AM, Scott Wood wrote: > On 03/07/2013 11:09:50 AM, Kumar Gala wrote: >> On Mar 5, 2013, at 6:15 PM, Scott Wood wrote: >> > On 03/05/2013 05:15:57 PM, Kumar Gala wrote: >> >> Enable a baseline T4240 SoC to boot. There are several things = missing >> >> from the device trees for T4240: >> >> * Thread support on e6500 >> > >> > Why did threads get removed from the device tree? It's supposed to = describe hardware, not what Linux currently supports. >> will fix, was concerned if we'd be able to boot if they exited >=20 > I don't think it'd be a problem (and if it is, then fix Linux). looks fine, so I'll add them in v2 patch. >=20 >> >> + device_type =3D "pci"; >> >> + #size-cells =3D <2>; >> >> + #address-cells =3D <3>; >> >> + bus-range =3D <0x0 0xff>; >> >> + clock-frequency =3D <33333333>; >> > >> > This clock-frequency is not correct (I doubt it's needed at all). >> I can zero the field, but its spec'd by pci binding >=20 > If we aren't going to put a correct value in, is zero better than = omitting it entirely? >=20 > There are other properties in the PCI binding that we don't have, such = as slot-names. I don't see any language in the PCI binding that says = one is required but the other isn't. >=20 > And shouldn't we be using the PCI express binding (device_type =3D = "pciex", or just get rid of it since this isn't real OF)? I'll drop clock-frequency since we dont use it. - k ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 5/8] powerpc/fsl-booke: Add initial silicon device tree for 2013-03-05 23:15 ` [PATCH 5/8] powerpc/fsl-booke: Add initial silicon device tree for Kumar Gala 2013-03-05 23:15 ` [PATCH 6/8] powerpc/fsl-booke: Add initial T4240QDS board device Kumar Gala 2013-03-06 0:15 ` [PATCH 5/8] powerpc/fsl-booke: Add initial silicon device tree for Scott Wood @ 2013-03-06 11:02 ` Roy Zang 2 siblings, 0 replies; 19+ messages in thread From: Roy Zang @ 2013-03-06 11:02 UTC (permalink / raw) To: Kumar Gala; +Cc: linuxppc-dev On 03/06/2013 07:15 AM, Kumar Gala wrote: > * Thread support on e6500 > * Proper PAMU topology information > * DPAA related nodes (Qman, Bman, Fman, Rman, DCE) > * Prefetch Manager > * Thermal monitor unit > * Interlaken > > Signed-off-by: Roy Zang<tie-fei.zang@freescale.com> > Signed-off-by: Minghuan Lian<Minghuan.Lian@freescale.com> > Signed-off-by: Haiying Wang<Haiying.Wang@freescale.com> > Signed-off-by: Andy Fleming<afleming@freescale.com> > Signed-off-by: Prabhakar Kushwaha<prabhakar@freescale.com> > Signed-off-by: York Sun<yorksun@freescale.com> > Signed-off-by: Vakul Garg<vakul@freescale.com> > Signed-off-by: Tang Yuantian<Yuantian.Tang@freescale.com> > Signed-off-by: Zhao Chenhui<chenhui.zhao@freescale.com> > Signed-off-by: Li Yang<leoli@freescale.com> > Signed-off-by: Ramneek Mehresh<ramneek.mehresh@freescale.com> > Signed-off-by: Haiying Wang<Haiying.Wang@freescale.com> Haiying is doubled. Roy ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 3/8] powerpc/fsl-booke: Support detection of page sizes on 2013-03-05 23:15 ` [PATCH 3/8] powerpc/fsl-booke: Support detection of page sizes on Kumar Gala 2013-03-05 23:15 ` [PATCH 4/8] powerpc/85xx: Add AltiVec support for e6500 Kumar Gala @ 2013-03-12 21:15 ` Kumar Gala 1 sibling, 0 replies; 19+ messages in thread From: Kumar Gala @ 2013-03-12 21:15 UTC (permalink / raw) To: linuxppc-dev On Mar 5, 2013, at 5:15 PM, Kumar Gala wrote: > The e6500 core used on T4240 and B4860 SoCs from FSL implements MMUv2 of > the Power Book-E Architecture. However there are some minor differences > between it and other Book-E implementations. > > Add support to parse SPRN_TLB1PS for the variable page sizes supported. > In the future this should be expanded for more page sizes supported on > e6500 as well as other MMU features. > > This patch is based on code from Scott Wood. > > Signed-off-by: Kumar Gala <galak@kernel.crashing.org> > --- > arch/powerpc/mm/tlb_nohash.c | 18 ++++++++++++++++-- > 1 file changed, 16 insertions(+), 2 deletions(-) applied to next - k ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/8] powerpc/85xx: Add support for FSL PCIe controller v3.0 2013-03-05 23:15 ` [PATCH 2/8] powerpc/85xx: Add support for FSL PCIe controller v3.0 Kumar Gala 2013-03-05 23:15 ` [PATCH 3/8] powerpc/fsl-booke: Support detection of page sizes on Kumar Gala @ 2013-03-12 21:15 ` Kumar Gala 1 sibling, 0 replies; 19+ messages in thread From: Kumar Gala @ 2013-03-12 21:15 UTC (permalink / raw) To: linuxppc-dev On Mar 5, 2013, at 5:15 PM, Kumar Gala wrote: > From: Roy ZANG <tie-fei.zang@freescale.com> > > The T4240 utilizes a new PCIe controller block that has some minor > programming model differences from previous versions. > > The major one that impacts initialization is how we determine the link > state. On the 3.x controllers we have a memory mapped SoC register > instead of a PCI config register that reports the link state. > > Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> > Signed-off-by: Andy Fleming <afleming@freescale.com> > Signed-off-by: Kumar Gala <galak@kernel.crashing.org> > --- > arch/powerpc/sysdev/fsl_pci.c | 29 ++++++++++++++++++++++++++--- > arch/powerpc/sysdev/fsl_pci.h | 11 +++++++++++ > 2 files changed, 37 insertions(+), 3 deletions(-) applied to next - k ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/8] powerpc/85xx: Added SEC-5.0 device tree. 2013-03-05 23:15 [PATCH 1/8] powerpc/85xx: Added SEC-5.0 device tree Kumar Gala 2013-03-05 23:15 ` [PATCH 2/8] powerpc/85xx: Add support for FSL PCIe controller v3.0 Kumar Gala @ 2013-03-12 21:14 ` Kumar Gala 1 sibling, 0 replies; 19+ messages in thread From: Kumar Gala @ 2013-03-12 21:14 UTC (permalink / raw) To: linuxppc-dev; +Cc: Vakul Garg On Mar 5, 2013, at 5:15 PM, Kumar Gala wrote: > From: Vakul Garg <vakul@freescale.com> >=20 > Add device tree for SEC (crypto engine) version 5.0 used on T4240. >=20 > Signed-off-by: Vakul Garg <vakul@freescale.com> > Signed-off-by: Andy Fleming <afleming@freescale.com> > Signed-off-by: Kumar Gala <galak@kernel.crashing.org> > --- > arch/powerpc/boot/dts/fsl/qoriq-sec5.0-0.dtsi | 109 = +++++++++++++++++++++++++ > 1 file changed, 109 insertions(+) > create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-sec5.0-0.dtsi applied to next - k= ^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2013-03-12 21:17 UTC | newest] Thread overview: 19+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-03-05 23:15 [PATCH 1/8] powerpc/85xx: Added SEC-5.0 device tree Kumar Gala 2013-03-05 23:15 ` [PATCH 2/8] powerpc/85xx: Add support for FSL PCIe controller v3.0 Kumar Gala 2013-03-05 23:15 ` [PATCH 3/8] powerpc/fsl-booke: Support detection of page sizes on Kumar Gala 2013-03-05 23:15 ` [PATCH 4/8] powerpc/85xx: Add AltiVec support for e6500 Kumar Gala 2013-03-05 23:15 ` [PATCH 5/8] powerpc/fsl-booke: Add initial silicon device tree for Kumar Gala 2013-03-05 23:15 ` [PATCH 6/8] powerpc/fsl-booke: Add initial T4240QDS board device Kumar Gala 2013-03-05 23:15 ` [PATCH 7/8] powerpc/fsl-booke: Add initial T4240QDS board support Kumar Gala 2013-03-05 23:16 ` [PATCH 8/8] powerpc/85xx: Update corenet64_smp_defconfig for T4240 Kumar Gala 2013-03-12 21:15 ` Kumar Gala 2013-03-12 21:16 ` [PATCH 7/8] powerpc/fsl-booke: Add initial T4240QDS board support Kumar Gala 2013-03-12 21:15 ` [PATCH 6/8] powerpc/fsl-booke: Add initial T4240QDS board device Kumar Gala 2013-03-06 0:15 ` [PATCH 5/8] powerpc/fsl-booke: Add initial silicon device tree for Scott Wood 2013-03-07 17:09 ` Kumar Gala 2013-03-07 17:47 ` Scott Wood 2013-03-07 19:53 ` Kumar Gala 2013-03-06 11:02 ` Roy Zang 2013-03-12 21:15 ` [PATCH 3/8] powerpc/fsl-booke: Support detection of page sizes on Kumar Gala 2013-03-12 21:15 ` [PATCH 2/8] powerpc/85xx: Add support for FSL PCIe controller v3.0 Kumar Gala 2013-03-12 21:14 ` [PATCH 1/8] powerpc/85xx: Added SEC-5.0 device tree Kumar Gala
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