Re: [PATCH] x86/MCE: Present MSR_IA32_MCx_MISC(2-6) as invalid on AMD

[Egger Christoph <chegger@amazon.de>]

On 12.03.13 16:32, Boris Ostrovsky wrote:
> MSR_IA32_MCx_MISC(4) register on AMD processors is used for error
> thresholding. PV guests may try to set it up for threshold
> interrupts which will fail and result in these warnings in the log:
>
>    [Firmware Bug]: cpu 0, try to use APIC510 (LVT offset 1) for vector
>    0xf9, but the register is already in use for vector 0x0 on this cpu
>
> Mark this register as invalid to avoid this. While at it, also present
> other MSR_IA32_MCx_MISC() registers as invalid (except for the first
> GUEST_MC_BANK_NUM which are emulated).
>
> Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>

Acked-by: Christoph Egger <chegger@amazon.de>

> ---
>   xen/arch/x86/cpu/mcheck/mce.h | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/xen/arch/x86/cpu/mcheck/mce.h b/xen/arch/x86/cpu/mcheck/mce.h
> index f2aeacb..d6526a4 100644
> --- a/xen/arch/x86/cpu/mcheck/mce.h
> +++ b/xen/arch/x86/cpu/mcheck/mce.h
> @@ -166,6 +166,7 @@ static inline int mce_vendor_bank_msr(const struct vcpu *v, uint32_t msr)
>           case MSR_F10_MC4_MISC1:
>           case MSR_F10_MC4_MISC2:
>           case MSR_F10_MC4_MISC3:
> +        case MSR_IA32_MCx_MISC(GUEST_MC_BANK_NUM)...MSR_IA32_MCx_MISC(6):
>               return 1;
>           }
>           break;
>