From: Fabien Chouteau <chouteau@adacore.com>
To: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Subject: [Qemu-devel] Cortex-M4F Floating Point system registers
Date: Wed, 20 Mar 2013 17:05:10 +0100 [thread overview]
Message-ID: <5149DE36.3060301@adacore.com> (raw)
Hello QEMU ARM folks,
I'm looking at the ARMv7-M profile and the implementation in QEMU.
Looks like M3 is supported and I'd like to work on M4F (FP context save
and lazy FP context save).
I wonder how the FPU system registers, and more generally how the
co-processor registers are implemented in QEMU.
For example in the Cortex-M4 TRM it seems like FP system registers are
mapped in memory. I don't see that implemented in QEMU.
Thanks,
--
Fabien Chouteau
next reply other threads:[~2013-03-20 16:05 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-20 16:05 Fabien Chouteau [this message]
2013-03-20 16:43 ` [Qemu-devel] Cortex-M4F Floating Point system registers Peter Maydell
2013-03-20 17:26 ` Fabien Chouteau
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