[PATCH 0/6] drm/radeon: minor HDMI improvements

[PATCH 0/6] drm/radeon: minor HDMI improvements

[Rafał Miłecki]

I've managed to track fglrx operations on HDMI regs, so we can finally setup
everything in (hopefully) the correct way and order.

This changes HDMI setup on Evergreen to mostly match fglrx and was tested on:
1) AMD Radeon HD 6320 (PALM == DCE41)
2) AMD Radeon HD 6970M (BARTS == DCE5)
No regressions noticed, I can still play audio, including LPCM, AC3 and DTS.

Unfortunately I don't have any DCE4 hardware to test this, but that changes
shouldn't cause any regressions. I hope that with such improvements we will
finally able to enable audio by default.

Rafał Miłecki (6):
  drm/radeon: add helpers for masking and setting bits in regs
  drm/radeon: remove HDMI interrupts on Evergreen
  drm/radeon: add some HDMI comments
  drm/radeon/evergreen: setup HDMI before enabling it
  drm/radeon/evergreen: reorder HDMI setup
  drm/radeon/evergreen: write default channel numbers

 drivers/gpu/drm/radeon/evergreen.c      |  127 +------------------------------
 drivers/gpu/drm/radeon/evergreen_hdmi.c |   77 +++++++++++++++----
 drivers/gpu/drm/radeon/evergreend.h     |    1 +
 drivers/gpu/drm/radeon/r600_hdmi.c      |   16 ++--
 drivers/gpu/drm/radeon/radeon.h         |    2 +
 drivers/gpu/drm/radeon/radeon_display.c |    5 ++
 6 files changed, 76 insertions(+), 152 deletions(-)

-- 
1.7.10.4

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[PATCH 1/6] drm/radeon: add helpers for masking and setting bits in regs

[Rafał Miłecki]

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
---
 drivers/gpu/drm/radeon/r600_hdmi.c |   16 ++++++----------
 drivers/gpu/drm/radeon/radeon.h    |    2 ++
 2 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 21ecc0e..91582a5 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -437,17 +437,15 @@ void r600_hdmi_enable(struct drm_encoder *encoder)
 		hdmi = HDMI0_ERROR_ACK | HDMI0_ENABLE;
 		switch (radeon_encoder->encoder_id) {
 		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
-			WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN,
-				 ~AVIVO_TMDSA_CNTL_HDMI_EN);
+			WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);
 			hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
 			break;
 		case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
-			WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN,
-				 ~AVIVO_LVTMA_CNTL_HDMI_EN);
+			WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);
 			hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
 			break;
 		case ENCODER_OBJECT_ID_INTERNAL_DDI:
-			WREG32_P(DDIA_CNTL, DDIA_HDMI_EN, ~DDIA_HDMI_EN);
+			WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN);
 			hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
 			break;
 		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
@@ -504,15 +502,13 @@ void r600_hdmi_disable(struct drm_encoder *encoder)
 	if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
 		switch (radeon_encoder->encoder_id) {
 		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
-			WREG32_P(AVIVO_TMDSA_CNTL, 0,
-				 ~AVIVO_TMDSA_CNTL_HDMI_EN);
+			WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);
 			break;
 		case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
-			WREG32_P(AVIVO_LVTMA_CNTL, 0,
-				 ~AVIVO_LVTMA_CNTL_HDMI_EN);
+			WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);
 			break;
 		case ENCODER_OBJECT_ID_INTERNAL_DDI:
-			WREG32_P(DDIA_CNTL, 0, ~DDIA_HDMI_EN);
+			WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);
 			break;
 		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 			break;
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 8263af3..1f4559b 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1697,6 +1697,8 @@ void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
 		tmp_ |= ((val) & ~(mask));			\
 		WREG32(reg, tmp_);				\
 	} while (0)
+#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
+#define WREG32_OR(reg, or) WREG32_P(reg, or, ~or)
 #define WREG32_PLL_P(reg, val, mask)				\
 	do {							\
 		uint32_t tmp_ = RREG32_PLL(reg);		\
-- 
1.7.10.4

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[PATCH 2/6] drm/radeon: remove HDMI interrupts on Evergreen

[Rafał Miłecki]

We need interrupts on format change for R6xx only, where hardware seems
to be somehow bugged and requires setting audio info manually.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/gpu/drm/radeon/evergreen.c |  127 +-----------------------------------
 1 file changed, 1 insertion(+), 126 deletions(-)

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 305a657..34d4347 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2702,7 +2702,6 @@ int evergreen_irq_set(struct radeon_device *rdev)
 	u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
 	u32 grbm_int_cntl = 0;
 	u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
-	u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
 	u32 dma_cntl, dma_cntl1 = 0;
 
 	if (!rdev->irq.installed) {
@@ -2724,13 +2723,6 @@ int evergreen_irq_set(struct radeon_device *rdev)
 	hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
 	hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
 
-	afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
-	afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
-	afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
-	afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
-	afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
-	afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
-
 	dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
 
 	if (rdev->family >= CHIP_CAYMAN) {
@@ -2822,30 +2814,6 @@ int evergreen_irq_set(struct radeon_device *rdev)
 		DRM_DEBUG("evergreen_irq_set: hpd 6\n");
 		hpd6 |= DC_HPDx_INT_EN;
 	}
-	if (rdev->irq.afmt[0]) {
-		DRM_DEBUG("evergreen_irq_set: hdmi 0\n");
-		afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK;
-	}
-	if (rdev->irq.afmt[1]) {
-		DRM_DEBUG("evergreen_irq_set: hdmi 1\n");
-		afmt2 |= AFMT_AZ_FORMAT_WTRIG_MASK;
-	}
-	if (rdev->irq.afmt[2]) {
-		DRM_DEBUG("evergreen_irq_set: hdmi 2\n");
-		afmt3 |= AFMT_AZ_FORMAT_WTRIG_MASK;
-	}
-	if (rdev->irq.afmt[3]) {
-		DRM_DEBUG("evergreen_irq_set: hdmi 3\n");
-		afmt4 |= AFMT_AZ_FORMAT_WTRIG_MASK;
-	}
-	if (rdev->irq.afmt[4]) {
-		DRM_DEBUG("evergreen_irq_set: hdmi 4\n");
-		afmt5 |= AFMT_AZ_FORMAT_WTRIG_MASK;
-	}
-	if (rdev->irq.afmt[5]) {
-		DRM_DEBUG("evergreen_irq_set: hdmi 5\n");
-		afmt6 |= AFMT_AZ_FORMAT_WTRIG_MASK;
-	}
 
 	if (rdev->family >= CHIP_CAYMAN) {
 		cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
@@ -2890,13 +2858,6 @@ int evergreen_irq_set(struct radeon_device *rdev)
 	WREG32(DC_HPD5_INT_CONTROL, hpd5);
 	WREG32(DC_HPD6_INT_CONTROL, hpd6);
 
-	WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1);
-	WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2);
-	WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3);
-	WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4);
-	WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5);
-	WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6);
-
 	return 0;
 }
 
@@ -2921,13 +2882,6 @@ static void evergreen_irq_ack(struct radeon_device *rdev)
 		rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
 	}
 
-	rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
-	rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
-	rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
-	rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
-	rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
-	rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
-
 	if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
 		WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
 	if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
@@ -3001,36 +2955,6 @@ static void evergreen_irq_ack(struct radeon_device *rdev)
 		tmp |= DC_HPDx_INT_ACK;
 		WREG32(DC_HPD6_INT_CONTROL, tmp);
 	}
-	if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
-		tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
-		tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
-		WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp);
-	}
-	if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
-		tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
-		tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
-		WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp);
-	}
-	if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
-		tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
-		tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
-		WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp);
-	}
-	if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
-		tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
-		tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
-		WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp);
-	}
-	if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
-		tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
-		tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
-		WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp);
-	}
-	if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
-		tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
-		tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
-		WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp);
-	}
 }
 
 static void evergreen_irq_disable(struct radeon_device *rdev)
@@ -3079,7 +3003,6 @@ int evergreen_irq_process(struct radeon_device *rdev)
 	u32 src_id, src_data;
 	u32 ring_index;
 	bool queue_hotplug = false;
-	bool queue_hdmi = false;
 
 	if (!rdev->ih.enabled || rdev->shutdown)
 		return IRQ_NONE;
@@ -3313,53 +3236,7 @@ restart_ih:
 			}
 			break;
 		case 44: /* hdmi */
-			switch (src_data) {
-			case 0:
-				if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
-					rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG;
-					queue_hdmi = true;
-					DRM_DEBUG("IH: HDMI0\n");
-				}
-				break;
-			case 1:
-				if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
-					rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG;
-					queue_hdmi = true;
-					DRM_DEBUG("IH: HDMI1\n");
-				}
-				break;
-			case 2:
-				if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
-					rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG;
-					queue_hdmi = true;
-					DRM_DEBUG("IH: HDMI2\n");
-				}
-				break;
-			case 3:
-				if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
-					rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG;
-					queue_hdmi = true;
-					DRM_DEBUG("IH: HDMI3\n");
-				}
-				break;
-			case 4:
-				if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
-					rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG;
-					queue_hdmi = true;
-					DRM_DEBUG("IH: HDMI4\n");
-				}
-				break;
-			case 5:
-				if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
-					rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG;
-					queue_hdmi = true;
-					DRM_DEBUG("IH: HDMI5\n");
-				}
-				break;
-			default:
-				DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
-				break;
-			}
+			DRM_ERROR("Unhandled HDMI interrupt: %d %d\n", src_id, src_data);
 			break;
 		case 146:
 		case 147:
@@ -3418,8 +3295,6 @@ restart_ih:
 	}
 	if (queue_hotplug)
 		schedule_work(&rdev->hotplug_work);
-	if (queue_hdmi)
-		schedule_work(&rdev->audio_work);
 	rdev->ih.rptr = rptr;
 	WREG32(IH_RB_RPTR, rdev->ih.rptr);
 	atomic_set(&rdev->ih.lock, 0);
-- 
1.7.10.4

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Re: [PATCH 2/6] drm/radeon: remove HDMI interrupts on Evergreen

[Paul Menzel]

[-- Attachment #1.1: Type: text/plain, Size: 456 bytes --]

Am Sonntag, den 14.04.2013, 01:26 +0200 schrieb Rafał Miłecki:
> We need interrupts on format change for R6xx only, where hardware seems
> to be somehow bugged and requires setting audio info manually.

How should this be tested?

> Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
> ---
>  drivers/gpu/drm/radeon/evergreen.c |  127 +-----------------------------------
>  1 file changed, 1 insertion(+), 126 deletions(-)


Thanks,

Paul

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[-- Type: application/pgp-signature, Size: 198 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

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Re: [PATCH 2/6] drm/radeon: remove HDMI interrupts on Evergreen

[Rafał Miłecki]

2013/4/14 Paul Menzel <paulepanter@users.sourceforge.net>:
> Am Sonntag, den 14.04.2013, 01:26 +0200 schrieb Rafał Miłecki:
>> We need interrupts on format change for R6xx only, where hardware seems
>> to be somehow bugged and requires setting audio info manually.
>
> How should this be tested?

Just play some audio using different settings (like LPCM, AC3, DTS,
various rates). On R6xx we had to adjust some registers on every
format change. It's not needed on Evergreen, GPU setup itself
automatically.

-- 
Rafał
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Re: [PATCH 2/6] drm/radeon: remove HDMI interrupts on Evergreen

[Alex Deucher]

On Sat, Apr 13, 2013 at 7:26 PM, Rafał Miłecki <zajec5@gmail.com> wrote:
> We need interrupts on format change for R6xx only, where hardware seems
> to be somehow bugged and requires setting audio info manually.

Can you confirm that this is actually needed on older chips?  AFAIK,
it shouldn't be required for any chips.  It's mainly for debugging.

Alex

>
> Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
> ---
>  drivers/gpu/drm/radeon/evergreen.c |  127 +-----------------------------------
>  1 file changed, 1 insertion(+), 126 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
> index 305a657..34d4347 100644
> --- a/drivers/gpu/drm/radeon/evergreen.c
> +++ b/drivers/gpu/drm/radeon/evergreen.c
> @@ -2702,7 +2702,6 @@ int evergreen_irq_set(struct radeon_device *rdev)
>         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
>         u32 grbm_int_cntl = 0;
>         u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
> -       u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
>         u32 dma_cntl, dma_cntl1 = 0;
>
>         if (!rdev->irq.installed) {
> @@ -2724,13 +2723,6 @@ int evergreen_irq_set(struct radeon_device *rdev)
>         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
>         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
>
> -       afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
> -       afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
> -       afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
> -       afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
> -       afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
> -       afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
> -
>         dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
>
>         if (rdev->family >= CHIP_CAYMAN) {
> @@ -2822,30 +2814,6 @@ int evergreen_irq_set(struct radeon_device *rdev)
>                 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
>                 hpd6 |= DC_HPDx_INT_EN;
>         }
> -       if (rdev->irq.afmt[0]) {
> -               DRM_DEBUG("evergreen_irq_set: hdmi 0\n");
> -               afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK;
> -       }
> -       if (rdev->irq.afmt[1]) {
> -               DRM_DEBUG("evergreen_irq_set: hdmi 1\n");
> -               afmt2 |= AFMT_AZ_FORMAT_WTRIG_MASK;
> -       }
> -       if (rdev->irq.afmt[2]) {
> -               DRM_DEBUG("evergreen_irq_set: hdmi 2\n");
> -               afmt3 |= AFMT_AZ_FORMAT_WTRIG_MASK;
> -       }
> -       if (rdev->irq.afmt[3]) {
> -               DRM_DEBUG("evergreen_irq_set: hdmi 3\n");
> -               afmt4 |= AFMT_AZ_FORMAT_WTRIG_MASK;
> -       }
> -       if (rdev->irq.afmt[4]) {
> -               DRM_DEBUG("evergreen_irq_set: hdmi 4\n");
> -               afmt5 |= AFMT_AZ_FORMAT_WTRIG_MASK;
> -       }
> -       if (rdev->irq.afmt[5]) {
> -               DRM_DEBUG("evergreen_irq_set: hdmi 5\n");
> -               afmt6 |= AFMT_AZ_FORMAT_WTRIG_MASK;
> -       }
>
>         if (rdev->family >= CHIP_CAYMAN) {
>                 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
> @@ -2890,13 +2858,6 @@ int evergreen_irq_set(struct radeon_device *rdev)
>         WREG32(DC_HPD5_INT_CONTROL, hpd5);
>         WREG32(DC_HPD6_INT_CONTROL, hpd6);
>
> -       WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1);
> -       WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2);
> -       WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3);
> -       WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4);
> -       WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5);
> -       WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6);
> -
>         return 0;
>  }
>
> @@ -2921,13 +2882,6 @@ static void evergreen_irq_ack(struct radeon_device *rdev)
>                 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
>         }
>
> -       rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
> -       rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
> -       rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
> -       rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
> -       rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
> -       rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
> -
>         if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
>                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
>         if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
> @@ -3001,36 +2955,6 @@ static void evergreen_irq_ack(struct radeon_device *rdev)
>                 tmp |= DC_HPDx_INT_ACK;
>                 WREG32(DC_HPD6_INT_CONTROL, tmp);
>         }
> -       if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
> -               tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
> -               tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
> -               WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp);
> -       }
> -       if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
> -               tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
> -               tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
> -               WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp);
> -       }
> -       if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
> -               tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
> -               tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
> -               WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp);
> -       }
> -       if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
> -               tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
> -               tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
> -               WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp);
> -       }
> -       if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
> -               tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
> -               tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
> -               WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp);
> -       }
> -       if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
> -               tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
> -               tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
> -               WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp);
> -       }
>  }
>
>  static void evergreen_irq_disable(struct radeon_device *rdev)
> @@ -3079,7 +3003,6 @@ int evergreen_irq_process(struct radeon_device *rdev)
>         u32 src_id, src_data;
>         u32 ring_index;
>         bool queue_hotplug = false;
> -       bool queue_hdmi = false;
>
>         if (!rdev->ih.enabled || rdev->shutdown)
>                 return IRQ_NONE;
> @@ -3313,53 +3236,7 @@ restart_ih:
>                         }
>                         break;
>                 case 44: /* hdmi */
> -                       switch (src_data) {
> -                       case 0:
> -                               if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
> -                                       rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG;
> -                                       queue_hdmi = true;
> -                                       DRM_DEBUG("IH: HDMI0\n");
> -                               }
> -                               break;
> -                       case 1:
> -                               if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
> -                                       rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG;
> -                                       queue_hdmi = true;
> -                                       DRM_DEBUG("IH: HDMI1\n");
> -                               }
> -                               break;
> -                       case 2:
> -                               if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
> -                                       rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG;
> -                                       queue_hdmi = true;
> -                                       DRM_DEBUG("IH: HDMI2\n");
> -                               }
> -                               break;
> -                       case 3:
> -                               if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
> -                                       rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG;
> -                                       queue_hdmi = true;
> -                                       DRM_DEBUG("IH: HDMI3\n");
> -                               }
> -                               break;
> -                       case 4:
> -                               if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
> -                                       rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG;
> -                                       queue_hdmi = true;
> -                                       DRM_DEBUG("IH: HDMI4\n");
> -                               }
> -                               break;
> -                       case 5:
> -                               if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
> -                                       rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG;
> -                                       queue_hdmi = true;
> -                                       DRM_DEBUG("IH: HDMI5\n");
> -                               }
> -                               break;
> -                       default:
> -                               DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
> -                               break;
> -                       }
> +                       DRM_ERROR("Unhandled HDMI interrupt: %d %d\n", src_id, src_data);
>                         break;
>                 case 146:
>                 case 147:
> @@ -3418,8 +3295,6 @@ restart_ih:
>         }
>         if (queue_hotplug)
>                 schedule_work(&rdev->hotplug_work);
> -       if (queue_hdmi)
> -               schedule_work(&rdev->audio_work);
>         rdev->ih.rptr = rptr;
>         WREG32(IH_RB_RPTR, rdev->ih.rptr);
>         atomic_set(&rdev->ih.lock, 0);
> --
> 1.7.10.4
>
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Re: [PATCH 2/6] drm/radeon: remove HDMI interrupts on Evergreen

[Rafał Miłecki]

2013/4/14 Alex Deucher <alexdeucher@gmail.com>:
> On Sat, Apr 13, 2013 at 7:26 PM, Rafał Miłecki <zajec5@gmail.com> wrote:
>> We need interrupts on format change for R6xx only, where hardware seems
>> to be somehow bugged and requires setting audio info manually.
>
> Can you confirm that this is actually needed on older chips?  AFAIK,
> it shouldn't be required for any chips.  It's mainly for debugging.

I can't really right now :( My notebook with RV620 died (hard disk
ended it's life and power cable got broken). I hope to resurrect him
in about a week.

If that isn't needed on R6xx, I'm not sure why we implemented it in
first place at all. Christian? Do you have idea why this was required?
I remember than in first place we were using timer, then we switched
to the interrupts. But why we needed it at all?

-- 
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Re: [PATCH 2/6] drm/radeon: remove HDMI interrupts on Evergreen

[Alex Deucher]

On Sun, Apr 14, 2013 at 11:55 AM, Rafał Miłecki <zajec5@gmail.com> wrote:
> 2013/4/14 Alex Deucher <alexdeucher@gmail.com>:
>> On Sat, Apr 13, 2013 at 7:26 PM, Rafał Miłecki <zajec5@gmail.com> wrote:
>>> We need interrupts on format change for R6xx only, where hardware seems
>>> to be somehow bugged and requires setting audio info manually.
>>
>> Can you confirm that this is actually needed on older chips?  AFAIK,
>> it shouldn't be required for any chips.  It's mainly for debugging.
>
> I can't really right now :( My notebook with RV620 died (hard disk
> ended it's life and power cable got broken). I hope to resurrect him
> in about a week.
>
> If that isn't needed on R6xx, I'm not sure why we implemented it in
> first place at all. Christian? Do you have idea why this was required?
> I remember than in first place we were using timer, then we switched
> to the interrupts. But why we needed it at all?

I suspect it was just assumed to be necessary due to the original RE.

Alex

>
> --
> Rafał
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Re: [PATCH 2/6] drm/radeon: remove HDMI interrupts on Evergreen

[Rafał Miłecki]

2013/4/14 Alex Deucher <alexdeucher@gmail.com>:
> On Sun, Apr 14, 2013 at 11:55 AM, Rafał Miłecki <zajec5@gmail.com> wrote:
>> 2013/4/14 Alex Deucher <alexdeucher@gmail.com>:
>>> On Sat, Apr 13, 2013 at 7:26 PM, Rafał Miłecki <zajec5@gmail.com> wrote:
>>>> We need interrupts on format change for R6xx only, where hardware seems
>>>> to be somehow bugged and requires setting audio info manually.
>>>
>>> Can you confirm that this is actually needed on older chips?  AFAIK,
>>> it shouldn't be required for any chips.  It's mainly for debugging.
>>
>> I can't really right now :( My notebook with RV620 died (hard disk
>> ended it's life and power cable got broken). I hope to resurrect him
>> in about a week.
>>
>> If that isn't needed on R6xx, I'm not sure why we implemented it in
>> first place at all. Christian? Do you have idea why this was required?
>> I remember than in first place we were using timer, then we switched
>> to the interrupts. But why we needed it at all?
>
> I suspect it was just assumed to be necessary due to the original RE.

I'm OK with removing that from R6xx too, if it's not needed. I just
want to check that first, to don't break audio accidentally. In case
of Evergreen I was able to test it, so I dares to submit this patch ;)

-- 
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Re: [PATCH 2/6] drm/radeon: remove HDMI interrupts on Evergreen

[Christian König]

Am 14.04.2013 20:02, schrieb Rafał Miłecki:
> 2013/4/14 Alex Deucher <alexdeucher@gmail.com>:
>> On Sun, Apr 14, 2013 at 11:55 AM, Rafał Miłecki <zajec5@gmail.com> wrote:
>>> 2013/4/14 Alex Deucher <alexdeucher@gmail.com>:
>>>> On Sat, Apr 13, 2013 at 7:26 PM, Rafał Miłecki <zajec5@gmail.com> wrote:
>>>>> We need interrupts on format change for R6xx only, where hardware seems
>>>>> to be somehow bugged and requires setting audio info manually.
>>>> Can you confirm that this is actually needed on older chips?  AFAIK,
>>>> it shouldn't be required for any chips.  It's mainly for debugging.
>>> I can't really right now :( My notebook with RV620 died (hard disk
>>> ended it's life and power cable got broken). I hope to resurrect him
>>> in about a week.
>>>
>>> If that isn't needed on R6xx, I'm not sure why we implemented it in
>>> first place at all. Christian? Do you have idea why this was required?
>>> I remember than in first place we were using timer, then we switched
>>> to the interrupts. But why we needed it at all?
>> I suspect it was just assumed to be necessary due to the original RE.
> I'm OK with removing that from R6xx too, if it's not needed. I just
> want to check that first, to don't break audio accidentally. In case
> of Evergreen I was able to test it, so I dares to submit this patch ;)

Well, originally I was just imitating fglrx behavior with this, but 
since I now have access to the AMD documentation I can't find a reason 
why fglrx was actually doing it like this. In theory format changes 
should work on their own, but it is still possible they did this because 
of some bug or something like this.

I can't really test it anymore either, so no idea if it is really 
required or not.

Christian.
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Re: [PATCH 2/6] drm/radeon: remove HDMI interrupts on Evergreen

[Alex Deucher]

On Mon, Apr 15, 2013 at 4:08 AM, Christian König
<deathsimple@vodafone.de> wrote:
> Am 14.04.2013 20:02, schrieb Rafał Miłecki:
>
>> 2013/4/14 Alex Deucher <alexdeucher@gmail.com>:
>>>
>>> On Sun, Apr 14, 2013 at 11:55 AM, Rafał Miłecki <zajec5@gmail.com> wrote:
>>>>
>>>> 2013/4/14 Alex Deucher <alexdeucher@gmail.com>:
>>>>>
>>>>> On Sat, Apr 13, 2013 at 7:26 PM, Rafał Miłecki <zajec5@gmail.com>
>>>>> wrote:
>>>>>>
>>>>>> We need interrupts on format change for R6xx only, where hardware
>>>>>> seems
>>>>>> to be somehow bugged and requires setting audio info manually.
>>>>>
>>>>> Can you confirm that this is actually needed on older chips?  AFAIK,
>>>>> it shouldn't be required for any chips.  It's mainly for debugging.
>>>>
>>>> I can't really right now :( My notebook with RV620 died (hard disk
>>>> ended it's life and power cable got broken). I hope to resurrect him
>>>> in about a week.
>>>>
>>>> If that isn't needed on R6xx, I'm not sure why we implemented it in
>>>> first place at all. Christian? Do you have idea why this was required?
>>>> I remember than in first place we were using timer, then we switched
>>>> to the interrupts. But why we needed it at all?
>>>
>>> I suspect it was just assumed to be necessary due to the original RE.
>>
>> I'm OK with removing that from R6xx too, if it's not needed. I just
>> want to check that first, to don't break audio accidentally. In case
>> of Evergreen I was able to test it, so I dares to submit this patch ;)
>
>
> Well, originally I was just imitating fglrx behavior with this, but since I
> now have access to the AMD documentation I can't find a reason why fglrx was
> actually doing it like this. In theory format changes should work on their
> own, but it is still possible they did this because of some bug or something
> like this.
>
> I can't really test it anymore either, so no idea if it is really required
> or not.

For both evergreen and older asics, maybe rather than removing the
code, we could just disable the interrupt src.  I.e., remove the call
to radeon_irq_kms_enable_afmt().  That way we can always re-enable it
if we need it for testing or debugging.

Alex

Re: [PATCH 2/6] drm/radeon: remove HDMI interrupts on Evergreen

[Rafał Miłecki]

2013/4/15 Alex Deucher <alexdeucher@gmail.com>:
> On Mon, Apr 15, 2013 at 4:08 AM, Christian König
> <deathsimple@vodafone.de> wrote:
>> Am 14.04.2013 20:02, schrieb Rafał Miłecki:
>>
>>> 2013/4/14 Alex Deucher <alexdeucher@gmail.com>:
>>>>
>>>> On Sun, Apr 14, 2013 at 11:55 AM, Rafał Miłecki <zajec5@gmail.com> wrote:
>>>>>
>>>>> 2013/4/14 Alex Deucher <alexdeucher@gmail.com>:
>>>>>>
>>>>>> On Sat, Apr 13, 2013 at 7:26 PM, Rafał Miłecki <zajec5@gmail.com>
>>>>>> wrote:
>>>>>>>
>>>>>>> We need interrupts on format change for R6xx only, where hardware
>>>>>>> seems
>>>>>>> to be somehow bugged and requires setting audio info manually.
>>>>>>
>>>>>> Can you confirm that this is actually needed on older chips?  AFAIK,
>>>>>> it shouldn't be required for any chips.  It's mainly for debugging.
>>>>>
>>>>> I can't really right now :( My notebook with RV620 died (hard disk
>>>>> ended it's life and power cable got broken). I hope to resurrect him
>>>>> in about a week.
>>>>>
>>>>> If that isn't needed on R6xx, I'm not sure why we implemented it in
>>>>> first place at all. Christian? Do you have idea why this was required?
>>>>> I remember than in first place we were using timer, then we switched
>>>>> to the interrupts. But why we needed it at all?
>>>>
>>>> I suspect it was just assumed to be necessary due to the original RE.
>>>
>>> I'm OK with removing that from R6xx too, if it's not needed. I just
>>> want to check that first, to don't break audio accidentally. In case
>>> of Evergreen I was able to test it, so I dares to submit this patch ;)
>>
>>
>> Well, originally I was just imitating fglrx behavior with this, but since I
>> now have access to the AMD documentation I can't find a reason why fglrx was
>> actually doing it like this. In theory format changes should work on their
>> own, but it is still possible they did this because of some bug or something
>> like this.
>>
>> I can't really test it anymore either, so no idea if it is really required
>> or not.
>
> For both evergreen and older asics, maybe rather than removing the
> code, we could just disable the interrupt src.  I.e., remove the call
> to radeon_irq_kms_enable_afmt().  That way we can always re-enable it
> if we need it for testing or debugging.

Even removing the code still keeps it in git history :)

Just give me some more time, so I can resurrect my old RV620 and make
some tests.

-- 
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Re: [PATCH 2/6] drm/radeon: remove HDMI interrupts on Evergreen

[Rafał Miłecki]

[-- Attachment #1: Type: text/plain, Size: 1680 bytes --]

2013/4/14 Alex Deucher <alexdeucher@gmail.com>:
> On Sat, Apr 13, 2013 at 7:26 PM, Rafał Miłecki <zajec5@gmail.com> wrote:
>> We need interrupts on format change for R6xx only, where hardware seems
>> to be somehow bugged and requires setting audio info manually.
>
> Can you confirm that this is actually needed on older chips?  AFAIK,
> it shouldn't be required for any chips.  It's mainly for debugging.

I've finally managed to install, run and debug fglrx on RV620. That
was really painful and ignoring Xorg 1.13 release in fglrx legacy
didn't help :|

Please take a look at attached log from fglrx. It seems that fglrx on
every audio format change does:
1) Read audio status (R600_AUDIO_STATUS_BITS, R600_AUDIO_RATE_BPS_CHANNEL)
2) Writes sth to HDMI0_STATUS and HDMI0_INFOFRAME_CONTROL0
3) Updates audio info frame
4) Recalculates checksum of audio info frame
5) Triggers update with HDMI0_AUDIO_INFO_UPDATE bit

That are some extra reads that look like polling, probably for some frame sync.

In the attached logs you can't see any real changes in audio info
frame, because I wasn't able to play more that 2 channels (because of
lacking support for multichannel audio in alsa). However I start
thinking we may need audio interrupts for all ASICs. And removing them
wasn't a good idea at al. After all, how we could handle audio
infoframe update on audio format change?

The thing we may try dropping is code updating HDMI0_60958_0 and
HDMI0_60958_1 registers. I don't see fglrx writing to that registers
on audio format change, so maybe hardware does handle that
automatically? That needs verifying with fglrx and radeon.

-- 
Rafał

[-- Attachment #2: format.change.txt --]
[-- Type: text/plain, Size: 24769 bytes --]

sudo mplayer -ao alsa:device=hw=1.3 01.flac -srate 44100

RREG32(0x00007404); -> 0x00e00000	HDMI0_STATUS
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x05e200a5
RREG32(0x000068a0); -> 0x08540109
RREG32(0x0000689c); -> 0x00020002
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x088602f4
RREG32(0x000068a0); -> 0x02910356
RREG32(0x0000689c); -> 0x00010002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020009
RREG32(0x00007408); -> 0x10020011	HDMI0_AUDIO_PACKET_CONTROL
RREG32(0x000073d8); -> 0x00000001	R600_AUDIO_STATUS_BITS
RREG32(0x000073c0); -> 0x00004011	R600_AUDIO_RATE_BPS_CHANNEL
RREG32(0x00007400); -> 0x00000010	HDMI0_STATUS
WREG32(0x00007400, 0x00000110);		HDMI0_STATUS			|= 1 << 8
RREG32(0x00007414); -> 0x00000013	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x00000013);		HDMI0_INFOFRAME_CONTROL0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
RREG32(0x000074d0); -> 0x00000000	HDMI0_AUDIO_INFO1
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x00007414); -> 0x00000013	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x000000b3);		HDMI0_INFOFRAME_CONTROL0	|= HDMI0_AUDIO_INFO_UPDATE
RREG32(0x00007404); -> 0x00e00010	HDMI0_STATUS
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x01c301f6
RREG32(0x000068a0); -> 0x065f025a
RREG32(0x0000689c); -> 0x00020002
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x0884044a
RREG32(0x000068a0); -> 0x00ad0049
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020009
RREG32(0x00007408); -> 0x10020011	HDMI0_AUDIO_PACKET_CONTROL
RREG32(0x000073d8); -> 0x00000001	R600_AUDIO_STATUS_BITS
RREG32(0x000073c0); -> 0x00004011	R600_AUDIO_RATE_BPS_CHANNEL
RREG32(0x00007400); -> 0x00000010	HDMI0_STATUS
WREG32(0x00007400, 0x00000110);		HDMI0_STATUS			|= 1 << 8
RREG32(0x00007414); -> 0x00000033	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x00000033);		HDMI0_INFOFRAME_CONTROL0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
RREG32(0x000074d0); -> 0x00000000	HDMI0_AUDIO_INFO1
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x00007414); -> 0x00000033	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x000000b3);		HDMI0_INFOFRAME_CONTROL0	|= HDMI0_AUDIO_INFO_UPDATE
RREG32(0x00007404); -> 0x00e00010	HDMI0_STATUS
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x03ab01ea
RREG32(0x000068a0); -> 0x0856024b
RREG32(0x0000689c); -> 0x00020002
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x05260433
RREG32(0x000068a0); -> 0x07b50030
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020009
RREG32(0x00007408); -> 0x10020011	HDMI0_AUDIO_PACKET_CONTROL
RREG32(0x000073d8); -> 0x00000001	R600_AUDIO_STATUS_BITS
RREG32(0x000073c0); -> 0x00004011	R600_AUDIO_RATE_BPS_CHANNEL
RREG32(0x00007400); -> 0x00000010	HDMI0_STATUS
WREG32(0x00007400, 0x00000110);		HDMI0_STATUS			|= 1 << 8
RREG32(0x00007414); -> 0x00000033	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x00000033);		HDMI0_INFOFRAME_CONTROL0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
RREG32(0x000074d0); -> 0x00000000	HDMI0_AUDIO_INFO1
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x00007414); -> 0x00000033	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x000000b3);		HDMI0_INFOFRAME_CONTROL0	|= HDMI0_AUDIO_INFO_UPDATE



sudo mplayer -ao alsa:device=hw=1.3 01.flac -srate 48000

RREG32(0x00007404); -> 0x00e00000	HDMI0_STATUS
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x03f3031c
RREG32(0x000068a0); -> 0x06ca0382
RREG32(0x0000689c); -> 0x00020002
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x0511010a
RREG32(0x000068a0); -> 0x02f7016c
RREG32(0x0000689c); -> 0x00010002
RREG32(0x0000689c); -> 0x00010002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020009
RREG32(0x00007408); -> 0x10020011	HDMI0_AUDIO_PACKET_CONTROL
RREG32(0x000073d8); -> 0x00000001	R600_AUDIO_STATUS_BITS
RREG32(0x000073c0); -> 0x00000011	R600_AUDIO_RATE_BPS_CHANNEL
RREG32(0x00007400); -> 0x00000010	HDMI0_STATUS
WREG32(0x00007400, 0x00000110);		HDMI0_STATUS			|= 1 << 8
RREG32(0x00007414); -> 0x00000033	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x00000033);		HDMI0_INFOFRAME_CONTROL0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
RREG32(0x000074d0); -> 0x00000000	HDMI0_AUDIO_INFO1
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x00007414); -> 0x00000033	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x000000b3);		HDMI0_INFOFRAME_CONTROL0	|= HDMI0_AUDIO_INFO_UPDATE
RREG32(0x00007404); -> 0x00e00010	HDMI0_STATUS
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x02ad01f9
RREG32(0x000068a0); -> 0x0434025d
RREG32(0x0000689c); -> 0x00000002
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x033b0448
RREG32(0x000068a0); -> 0x01a00045
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00010002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00010002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00050002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00050009
RREG32(0x00007408); -> 0x10020011	HDMI0_AUDIO_PACKET_CONTROL
RREG32(0x000073d8); -> 0x00000001	R600_AUDIO_STATUS_BITS
RREG32(0x000073c0); -> 0x00000011	R600_AUDIO_RATE_BPS_CHANNEL
RREG32(0x00007400); -> 0x00000010	HDMI0_STATUS
WREG32(0x00007400, 0x00000110);		HDMI0_STATUS			|= 1 << 8
RREG32(0x00007414); -> 0x00000033	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x00000033);		HDMI0_INFOFRAME_CONTROL0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
RREG32(0x000074d0); -> 0x00000000	HDMI0_AUDIO_INFO1
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x00007414); -> 0x00000033	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x000000b3);		HDMI0_INFOFRAME_CONTROL0	|= HDMI0_AUDIO_INFO_UPDATE



sudo mplayer -ao alsa:device=hw=1.3 01.flac -srate 48000

RREG32(0x00007404); -> 0x00e00000	HDMI0_STATUS
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x08380306
RREG32(0x000068a0); -> 0x07200369
RREG32(0x0000689c); -> 0x00020002
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x069d00f2
RREG32(0x000068a0); -> 0x03910154
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00000002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00000002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020008
RREG32(0x0000689c); -> 0x00000002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00010002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020009
RREG32(0x00007408); -> 0x10020011	HDMI0_AUDIO_PACKET_CONTROL
RREG32(0x000073d8); -> 0x00000001	R600_AUDIO_STATUS_BITS
RREG32(0x000073c0); -> 0x00000011	R600_AUDIO_RATE_BPS_CHANNEL
RREG32(0x00007400); -> 0x00000010	HDMI0_STATUS
WREG32(0x00007400, 0x00000110);		HDMI0_STATUS			|= 1 << 8
RREG32(0x00007414); -> 0x00000033	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x00000033);		HDMI0_INFOFRAME_CONTROL0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
RREG32(0x000074d0); -> 0x00000000	HDMI0_AUDIO_INFO1
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x00007414); -> 0x00000033	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x000000b3);		HDMI0_INFOFRAME_CONTROL0	|= HDMI0_AUDIO_INFO_UPDATE
RREG32(0x00007404); -> 0x00e00010	HDMI0_STATUS
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x039f0201
RREG32(0x000068a0); -> 0x02830264
RREG32(0x0000689c); -> 0x00020002
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x013a044f
RREG32(0x000068a0); -> 0x0220004b
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00000002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00050002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00000002
RREG32(0x0000689c); -> 0x00020009
RREG32(0x00007408); -> 0x10020011	HDMI0_AUDIO_PACKET_CONTROL
RREG32(0x000073d8); -> 0x00000001	R600_AUDIO_STATUS_BITS
RREG32(0x000073c0); -> 0x00000011	R600_AUDIO_RATE_BPS_CHANNEL
RREG32(0x00007400); -> 0x00000010	HDMI0_STATUS
WREG32(0x00007400, 0x00000110);		HDMI0_STATUS			|= 1 << 8
RREG32(0x00007414); -> 0x00000033	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x00000033);		HDMI0_INFOFRAME_CONTROL0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
RREG32(0x000074d0); -> 0x00000000	HDMI0_AUDIO_INFO1
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x00007414); -> 0x00000033	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x000000b3);		HDMI0_INFOFRAME_CONTROL0	|= HDMI0_AUDIO_INFO_UPDATE
RREG32(0x00007404); -> 0x00e00010	HDMI0_STATUS
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x04f501ef
RREG32(0x000068a0); -> 0x03270251
RREG32(0x0000689c); -> 0x00020002
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x02ab043c
RREG32(0x000068a0); -> 0x07000037
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00050002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x0002000d
RREG32(0x00007408); -> 0x10020011	HDMI0_AUDIO_PACKET_CONTROL
RREG32(0x000073d8); -> 0x00000001	R600_AUDIO_STATUS_BITS
RREG32(0x000073c0); -> 0x00000011	R600_AUDIO_RATE_BPS_CHANNEL
RREG32(0x00007400); -> 0x00000010	HDMI0_STATUS
WREG32(0x00007400, 0x00000110);		HDMI0_STATUS			|= 1 << 8
RREG32(0x00007414); -> 0x00000033	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x00000033);		HDMI0_INFOFRAME_CONTROL0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
RREG32(0x000074d0); -> 0x00000000	HDMI0_AUDIO_INFO1
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x00007414); -> 0x00000033	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x000000b3);		HDMI0_INFOFRAME_CONTROL0	|= HDMI0_AUDIO_INFO_UPDATE



sudo mplayer -ao alsa:device=hw=1.3 -ac hwac3 Broadway-5.1-48khz-448kbit.ac3

RREG32(0x00007404); -> 0x00e00010	HDMI0_STATUS
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x05dc01f2
RREG32(0x000068a0); -> 0x06ba0253
RREG32(0x0000689c); -> 0x00020002
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x03f4043a
RREG32(0x000068a0); -> 0x0803003a
RREG32(0x0000689c); -> 0x00010002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00010002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00010002
RREG32(0x0000689c); -> 0x00020009
RREG32(0x00007408); -> 0x10020011	HDMI0_AUDIO_PACKET_CONTROL
RREG32(0x000073d8); -> 0x00000001	R600_AUDIO_STATUS_BITS
RREG32(0x000073c0); -> 0x00000011	R600_AUDIO_RATE_BPS_CHANNEL
RREG32(0x00007400); -> 0x00000010	HDMI0_STATUS
WREG32(0x00007400, 0x00000110);		HDMI0_STATUS			|= 1 << 8
RREG32(0x00007414); -> 0x00000033	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x00000033);		HDMI0_INFOFRAME_CONTROL0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
RREG32(0x000074d0); -> 0x00000000	HDMI0_AUDIO_INFO1
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x00007414); -> 0x00000033	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x000000b3);		HDMI0_INFOFRAME_CONTROL0	|= HDMI0_AUDIO_INFO_UPDATE
RREG32(0x00007404); -> 0x00e00010	HDMI0_STATUS
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x048d01dc
RREG32(0x000068a0); -> 0x0229023d
RREG32(0x0000689c); -> 0x00020002
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x072c0423
RREG32(0x000068a0); -> 0x07150023
RREG32(0x0000689c); -> 0x00000002
RREG32(0x0000689c); -> 0x00010002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020008
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020011
RREG32(0x00007408); -> 0x10020011	HDMI0_AUDIO_PACKET_CONTROL
RREG32(0x000073d8); -> 0x00000001	R600_AUDIO_STATUS_BITS
RREG32(0x000073c0); -> 0x00000011	R600_AUDIO_RATE_BPS_CHANNEL
RREG32(0x00007400); -> 0x00000010	HDMI0_STATUS
WREG32(0x00007400, 0x00000110);		HDMI0_STATUS			|= 1 << 8
RREG32(0x00007414); -> 0x00000033	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x00000033);		HDMI0_INFOFRAME_CONTROL0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
RREG32(0x000074d0); -> 0x00000000	HDMI0_AUDIO_INFO1
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x00007414); -> 0x00000033	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x000000b3);		HDMI0_INFOFRAME_CONTROL0	|= HDMI0_AUDIO_INFO_UPDATE
RREG32(0x00007404); -> 0x00e00010	HDMI0_STATUS
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x03f501f2
RREG32(0x000068a0); -> 0x04cf0254
RREG32(0x0000689c); -> 0x00010002
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x0636043b
RREG32(0x000068a0); -> 0x001f0037
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00010002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00000002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020009
RREG32(0x00007408); -> 0x10020011	HDMI0_AUDIO_PACKET_CONTROL
RREG32(0x000073d8); -> 0x00000001	R600_AUDIO_STATUS_BITS
RREG32(0x000073c0); -> 0x00000011	R600_AUDIO_RATE_BPS_CHANNEL
RREG32(0x00007400); -> 0x00000010	HDMI0_STATUS
WREG32(0x00007400, 0x00000110);		HDMI0_STATUS			|= 1 << 8
RREG32(0x00007414); -> 0x00000033	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x00000033);		HDMI0_INFOFRAME_CONTROL0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
RREG32(0x000074d0); -> 0x00000000	HDMI0_AUDIO_INFO1
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x00007414); -> 0x00000033	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x000000b3);		HDMI0_INFOFRAME_CONTROL0	|= HDMI0_AUDIO_INFO_UPDATE



sudo mplayer -ao alsa:device=hw=1.3 -ac hwdts 06_NEW_JAZZ_SSQ3_ENERGY_DTS.wav

RREG32(0x00007404); -> 0x00e00000	HDMI0_STATUS
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x08750083
RREG32(0x000068a0); -> 0x04c900e6
RREG32(0x0000689c); -> 0x00020002
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x071302d2
RREG32(0x000068a0); -> 0x063e0334
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020008
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00010002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020000
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00010002
RREG32(0x0000689c); -> 0x0002000d
RREG32(0x00007408); -> 0x10020011	HDMI0_AUDIO_PACKET_CONTROL
RREG32(0x000073d8); -> 0x00000001	R600_AUDIO_STATUS_BITS
RREG32(0x000073c0); -> 0x00004011	R600_AUDIO_RATE_BPS_CHANNEL
RREG32(0x00007400); -> 0x00000010	HDMI0_STATUS
WREG32(0x00007400, 0x00000110);		HDMI0_STATUS			|= 1 << 8
RREG32(0x00007414); -> 0x00000033	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x00000033);		HDMI0_INFOFRAME_CONTROL0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
RREG32(0x000074d0); -> 0x00000000	HDMI0_AUDIO_INFO1
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x00007414); -> 0x00000033	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x000000b3);		HDMI0_INFOFRAME_CONTROL0	|= HDMI0_AUDIO_INFO_UPDATE
RREG32(0x00007404); -> 0x00e00010	HDMI0_STATUS
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x009f01ca
RREG32(0x000068a0); -> 0x0115022d
RREG32(0x0000689c); -> 0x00020002
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x00f50412
RREG32(0x000068a0); -> 0x07a10012
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00010002
RREG32(0x0000689c); -> 0x00020008
RREG32(0x0000689c); -> 0x00020000
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00050002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00010002
RREG32(0x0000689c); -> 0x00010002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020009
RREG32(0x00007408); -> 0x10020011	HDMI0_AUDIO_PACKET_CONTROL
RREG32(0x000073d8); -> 0x00000001	R600_AUDIO_STATUS_BITS
RREG32(0x000073c0); -> 0x00004011	R600_AUDIO_RATE_BPS_CHANNEL
RREG32(0x00007400); -> 0x00000010	HDMI0_STATUS
WREG32(0x00007400, 0x00000110);		HDMI0_STATUS			|= 1 << 8
RREG32(0x00007414); -> 0x00000033	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x00000033);		HDMI0_INFOFRAME_CONTROL0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
RREG32(0x000074d0); -> 0x00000000	HDMI0_AUDIO_INFO1
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x00007414); -> 0x00000033	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x000000b3);		HDMI0_INFOFRAME_CONTROL0	|= HDMI0_AUDIO_INFO_UPDATE
RREG32(0x00007404); -> 0x00e00010	HDMI0_STATUS
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x06d901e3
RREG32(0x000068a0); -> 0x01370244
RREG32(0x0000689c); -> 0x00020002
RREG32(0x00000330); -> 0x00000000
RREG32(0x00000338); -> 0x00000000
RREG32(0x000060f8); -> 0x00000003
RREG32(0x000068a0); -> 0x06d70428
RREG32(0x000068a0); -> 0x046b0027
RREG32(0x0000689c); -> 0x00050002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00000002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020008
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00010002
RREG32(0x0000689c); -> 0x00000002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020000
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00010002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00000002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020002
RREG32(0x0000689c); -> 0x00020009
RREG32(0x00007408); -> 0x10020011	HDMI0_AUDIO_PACKET_CONTROL
RREG32(0x000073d8); -> 0x00000001	R600_AUDIO_STATUS_BITS
RREG32(0x000073c0); -> 0x00004011	R600_AUDIO_RATE_BPS_CHANNEL
RREG32(0x00007400); -> 0x00000010	HDMI0_STATUS
WREG32(0x00007400, 0x00000110);		HDMI0_STATUS			|= 1 << 8
RREG32(0x00007414); -> 0x00000033	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x00000033);		HDMI0_INFOFRAME_CONTROL0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x000074cc); -> 0x00000170	HDMI0_AUDIO_INFO0
RREG32(0x000074d0); -> 0x00000000	HDMI0_AUDIO_INFO1
WREG32(0x000074cc, 0x00000170);		HDMI0_AUDIO_INFO0
RREG32(0x00007414); -> 0x00000033	HDMI0_INFOFRAME_CONTROL0
WREG32(0x00007414, 0x000000b3);		HDMI0_INFOFRAME_CONTROL0	|= HDMI0_AUDIO_INFO_UPDATE

[-- Attachment #3: Type: text/plain, Size: 159 bytes --]

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Re: [PATCH 2/6] drm/radeon: remove HDMI interrupts on Evergreen

[Rafał Miłecki]

2013/4/21 Rafał Miłecki <zajec5@gmail.com>:
> 2013/4/14 Alex Deucher <alexdeucher@gmail.com>:
>> On Sat, Apr 13, 2013 at 7:26 PM, Rafał Miłecki <zajec5@gmail.com> wrote:
>>> We need interrupts on format change for R6xx only, where hardware seems
>>> to be somehow bugged and requires setting audio info manually.
>>
>> Can you confirm that this is actually needed on older chips?  AFAIK,
>> it shouldn't be required for any chips.  It's mainly for debugging.
>
> I've finally managed to install, run and debug fglrx on RV620. That
> was really painful and ignoring Xorg 1.13 release in fglrx legacy
> didn't help :|
>
> Please take a look at attached log from fglrx. It seems that fglrx on
> every audio format change does:
> 1) Read audio status (R600_AUDIO_STATUS_BITS, R600_AUDIO_RATE_BPS_CHANNEL)
> 2) Writes sth to HDMI0_STATUS and HDMI0_INFOFRAME_CONTROL0
> 3) Updates audio info frame
> 4) Recalculates checksum of audio info frame
> 5) Triggers update with HDMI0_AUDIO_INFO_UPDATE bit

Btw. could we get a meaning of bit 0x100 in HDMI0_STATUS?

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Re: [PATCH 2/6] drm/radeon: remove HDMI interrupts on Evergreen

[Alex Deucher]

On Sun, Apr 21, 2013 at 3:15 PM, Rafał Miłecki <zajec5@gmail.com> wrote:
> 2013/4/21 Rafał Miłecki <zajec5@gmail.com>:
>> 2013/4/14 Alex Deucher <alexdeucher@gmail.com>:
>>> On Sat, Apr 13, 2013 at 7:26 PM, Rafał Miłecki <zajec5@gmail.com> wrote:
>>>> We need interrupts on format change for R6xx only, where hardware seems
>>>> to be somehow bugged and requires setting audio info manually.
>>>
>>> Can you confirm that this is actually needed on older chips?  AFAIK,
>>> it shouldn't be required for any chips.  It's mainly for debugging.
>>
>> I've finally managed to install, run and debug fglrx on RV620. That
>> was really painful and ignoring Xorg 1.13 release in fglrx legacy
>> didn't help :|
>>
>> Please take a look at attached log from fglrx. It seems that fglrx on
>> every audio format change does:
>> 1) Read audio status (R600_AUDIO_STATUS_BITS, R600_AUDIO_RATE_BPS_CHANNEL)
>> 2) Writes sth to HDMI0_STATUS and HDMI0_INFOFRAME_CONTROL0
>> 3) Updates audio info frame
>> 4) Recalculates checksum of audio info frame
>> 5) Triggers update with HDMI0_AUDIO_INFO_UPDATE bit
>
> Btw. could we get a meaning of bit 0x100 in HDMI0_STATUS?

There is no bit 8 defined in that register.  Also FWIW, HDMI0_STATUS
is a read only register.

Alex

>
> --
> Rafał

Re: [PATCH 2/6] drm/radeon: remove HDMI interrupts on Evergreen

[Rafał Miłecki]

2013/4/21 Alex Deucher <alexdeucher@gmail.com>:
> On Sun, Apr 21, 2013 at 3:15 PM, Rafał Miłecki <zajec5@gmail.com> wrote:
>> 2013/4/21 Rafał Miłecki <zajec5@gmail.com>:
>>> 2013/4/14 Alex Deucher <alexdeucher@gmail.com>:
>>>> On Sat, Apr 13, 2013 at 7:26 PM, Rafał Miłecki <zajec5@gmail.com> wrote:
>>>>> We need interrupts on format change for R6xx only, where hardware seems
>>>>> to be somehow bugged and requires setting audio info manually.
>>>>
>>>> Can you confirm that this is actually needed on older chips?  AFAIK,
>>>> it shouldn't be required for any chips.  It's mainly for debugging.
>>>
>>> I've finally managed to install, run and debug fglrx on RV620. That
>>> was really painful and ignoring Xorg 1.13 release in fglrx legacy
>>> didn't help :|
>>>
>>> Please take a look at attached log from fglrx. It seems that fglrx on
>>> every audio format change does:
>>> 1) Read audio status (R600_AUDIO_STATUS_BITS, R600_AUDIO_RATE_BPS_CHANNEL)
>>> 2) Writes sth to HDMI0_STATUS and HDMI0_INFOFRAME_CONTROL0
>>> 3) Updates audio info frame
>>> 4) Recalculates checksum of audio info frame
>>> 5) Triggers update with HDMI0_AUDIO_INFO_UPDATE bit
>>
>> Btw. could we get a meaning of bit 0x100 in HDMI0_STATUS?
>
> There is no bit 8 defined in that register.  Also FWIW, HDMI0_STATUS
> is a read only register.

Ahh, sorry. 0x7400 is HDMI0_CONTROL not HDMI0_STATUS! My silly
mistake. It makes sense of course:
#       define HDMI0_ERROR_ACK       (1 << 8)

Still I can't see how we could drop interrupts and keep updating audio
infoframe.

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[PATCH 3/6] drm/radeon: add some HDMI comments

[Rafał Miłecki]

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/gpu/drm/radeon/evergreen_hdmi.c |   14 ++++++++++++++
 drivers/gpu/drm/radeon/radeon_display.c |    5 +++++
 2 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index 4fdecc2..8b64bf1 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -143,6 +143,13 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
 
 	WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
 
+	/*
+	 * At this point fglrx reads following regs:
+	 * DCE41: 0x49c
+	 * DCE5: 0x480 0x484 0x488
+	 * Is that something audio related?
+	 */
+
 	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 	if (err < 0) {
 		DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
@@ -158,6 +165,13 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
 	evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
 	evergreen_hdmi_update_ACR(encoder, mode->clock);
 
+	/*
+	 * At this point fglrx changes following regs:
+	 * DCE41: 0x7a70
+	 * DCE5: 0x7a70 and 0x64ec
+	 * Is that something audio related?
+	 */
+
 	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
 	WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
 	WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index e38fd55..a83c272 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -1261,6 +1261,11 @@ static void radeon_afmt_init(struct radeon_device *rdev)
 			rdev->mode_info.afmt[1]->offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
 			rdev->mode_info.afmt[1]->id = 1;
 		}
+		/*
+		 * According to the commens above we should use !DCE41 || DCE5,
+		 * condition, however there isn't any DCE5 that is DCE41, so
+		 * DCE5 check is not needed.
+		 */
 		if (!ASIC_IS_DCE41(rdev)) {
 			rdev->mode_info.afmt[2] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
 			if (rdev->mode_info.afmt[2]) {
-- 
1.7.10.4

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Re: [PATCH 3/6] drm/radeon: add some HDMI comments

[Paul Menzel]

[-- Attachment #1.1: Type: text/plain, Size: 2576 bytes --]

Am Sonntag, den 14.04.2013, 01:26 +0200 schrieb Rafał Miłecki:

Maybe for a more descriptive summary:

drm/radeon: Add some HDMI (audio) comments about fglrx’ reg reads

> Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
> ---
>  drivers/gpu/drm/radeon/evergreen_hdmi.c |   14 ++++++++++++++
>  drivers/gpu/drm/radeon/radeon_display.c |    5 +++++
>  2 files changed, 19 insertions(+)
> 
> diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> index 4fdecc2..8b64bf1 100644
> --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
> +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> @@ -143,6 +143,13 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
>  
>  	WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
>  
> +	/*
> +	 * At this point fglrx reads following regs:
> +	 * DCE41: 0x49c
> +	 * DCE5: 0x480 0x484 0x488
> +	 * Is that something audio related?
> +	 */
> +
>  	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
>  	if (err < 0) {
>  		DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
> @@ -158,6 +165,13 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
>  	evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
>  	evergreen_hdmi_update_ACR(encoder, mode->clock);
>  
> +	/*
> +	 * At this point fglrx changes following regs:
> +	 * DCE41: 0x7a70
> +	 * DCE5: 0x7a70 and 0x64ec
> +	 * Is that something audio related?
> +	 */
> +
>  	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
>  	WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
>  	WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
> diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
> index e38fd55..a83c272 100644
> --- a/drivers/gpu/drm/radeon/radeon_display.c
> +++ b/drivers/gpu/drm/radeon/radeon_display.c
> @@ -1261,6 +1261,11 @@ static void radeon_afmt_init(struct radeon_device *rdev)
>  			rdev->mode_info.afmt[1]->offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
>  			rdev->mode_info.afmt[1]->id = 1;
>  		}

Add an empty line?

> +		/*
> +		 * According to the commens above we should use !DCE41 || DCE5,

commen*t*s

> +		 * condition, however there isn't any DCE5 that is DCE41, so
> +		 * DCE5 check is not needed.
> +		 */
>  		if (!ASIC_IS_DCE41(rdev)) {
>  			rdev->mode_info.afmt[2] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
>  			if (rdev->mode_info.afmt[2]) {


Thanks,

Paul

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Re: [PATCH 3/6] drm/radeon: add some HDMI comments

[Rafał Miłecki]

2013/4/14 Paul Menzel <paulepanter@users.sourceforge.net>:
> Am Sonntag, den 14.04.2013, 01:26 +0200 schrieb Rafał Miłecki:
>
> Maybe for a more descriptive summary:
>
> drm/radeon: Add some HDMI (audio) comments about fglrx’ reg reads

I also comment sth in radeon_display.c.

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[PATCH V2 3/6] drm/radeon: add some HDMI audio comments

[Rafał Miłecki]

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
V2: fix typo and add extra \n
---
 drivers/gpu/drm/radeon/evergreen_hdmi.c |   14 ++++++++++++++
 drivers/gpu/drm/radeon/radeon_display.c |    6 ++++++
 2 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index 4fdecc2..8b64bf1 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -143,6 +143,13 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
 
 	WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
 
+	/*
+	 * At this point fglrx reads following regs:
+	 * DCE41: 0x49c
+	 * DCE5: 0x480 0x484 0x488
+	 * Is that something audio related?
+	 */
+
 	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 	if (err < 0) {
 		DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
@@ -158,6 +165,13 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
 	evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
 	evergreen_hdmi_update_ACR(encoder, mode->clock);
 
+	/*
+	 * At this point fglrx changes following regs:
+	 * DCE41: 0x7a70
+	 * DCE5: 0x7a70 and 0x64ec
+	 * Is that something audio related?
+	 */
+
 	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
 	WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
 	WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index e38fd55..376c4e4 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -1261,6 +1261,12 @@ static void radeon_afmt_init(struct radeon_device *rdev)
 			rdev->mode_info.afmt[1]->offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
 			rdev->mode_info.afmt[1]->id = 1;
 		}
+
+		/*
+		 * According to the comments above we should use !DCE41 || DCE5
+		 * condition, however there isn't any DCE5 that is DCE41, so
+		 * DCE5 check is not needed.
+		 */
 		if (!ASIC_IS_DCE41(rdev)) {
 			rdev->mode_info.afmt[2] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
 			if (rdev->mode_info.afmt[2]) {
-- 
1.7.10.4

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Re: [PATCH 3/6] drm/radeon: add some HDMI comments

[Alex Deucher]

On Sat, Apr 13, 2013 at 7:26 PM, Rafał Miłecki <zajec5@gmail.com> wrote:
>
> Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
> ---
>  drivers/gpu/drm/radeon/evergreen_hdmi.c |   14 ++++++++++++++
>  drivers/gpu/drm/radeon/radeon_display.c |    5 +++++
>  2 files changed, 19 insertions(+)
>
> diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> index 4fdecc2..8b64bf1 100644
> --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
> +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> @@ -143,6 +143,13 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
>
>         WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
>
> +       /*
> +        * At this point fglrx reads following regs:
> +        * DCE41: 0x49c
> +        * DCE5: 0x480 0x484 0x488
> +        * Is that something audio related?
> +        */
> +

Those are DCPLL dividers.  Nothing to do with audio.  That's just the
driver setting the display engine PLL (probably calling
SetPixelClock).

>         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
>         if (err < 0) {
>                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
> @@ -158,6 +165,13 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
>         evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
>         evergreen_hdmi_update_ACR(encoder, mode->clock);
>
> +       /*
> +        * At this point fglrx changes following regs:
> +        * DCE41: 0x7a70
> +        * DCE5: 0x7a70 and 0x64ec
> +        * Is that something audio related?
> +        */
> +

Ox7a70 is CRTC_CONTROL for crtc1 (CRTC_CONTRL + crtc_offset[1]).

>         /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
>         WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
>         WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
> diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
> index e38fd55..a83c272 100644
> --- a/drivers/gpu/drm/radeon/radeon_display.c
> +++ b/drivers/gpu/drm/radeon/radeon_display.c
> @@ -1261,6 +1261,11 @@ static void radeon_afmt_init(struct radeon_device *rdev)
>                         rdev->mode_info.afmt[1]->offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
>                         rdev->mode_info.afmt[1]->id = 1;
>                 }
> +               /*
> +                * According to the commens above we should use !DCE41 || DCE5,
> +                * condition, however there isn't any DCE5 that is DCE41, so
> +                * DCE5 check is not needed.
> +                */

It would probably be more obvious to just loop over rdev->num_crtc
since the number of hdmi blocks matches the number of crtcs.

Alex

>                 if (!ASIC_IS_DCE41(rdev)) {
>                         rdev->mode_info.afmt[2] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
>                         if (rdev->mode_info.afmt[2]) {
> --
> 1.7.10.4
>
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Re: [PATCH 3/6] drm/radeon: add some HDMI comments

[Rafał Miłecki]

2013/4/14 Alex Deucher <alexdeucher@gmail.com>:
>> +               /*
>> +                * According to the commens above we should use !DCE41 || DCE5,
>> +                * condition, however there isn't any DCE5 that is DCE41, so
>> +                * DCE5 check is not needed.
>> +                */
>
> It would probably be more obvious to just loop over rdev->num_crtc
> since the number of hdmi blocks matches the number of crtcs.

Not really.

1) CHIP_CAICOS
It has 4 CRTCs but is DCE5, so has 6 AFMTs

2) CHIP_CEDAR
It has 4 CRTCs but is DCE4, so also has 6 AFMTs

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Re: [PATCH 3/6] drm/radeon: add some HDMI comments

[Alex Deucher]

On Sun, Apr 14, 2013 at 1:58 PM, Rafał Miłecki <zajec5@gmail.com> wrote:
> 2013/4/14 Alex Deucher <alexdeucher@gmail.com>:
>>> +               /*
>>> +                * According to the commens above we should use !DCE41 || DCE5,
>>> +                * condition, however there isn't any DCE5 that is DCE41, so
>>> +                * DCE5 check is not needed.
>>> +                */
>>
>> It would probably be more obvious to just loop over rdev->num_crtc
>> since the number of hdmi blocks matches the number of crtcs.
>
> Not really.
>
> 1) CHIP_CAICOS
> It has 4 CRTCs but is DCE5, so has 6 AFMTs
>
> 2) CHIP_CEDAR
> It has 4 CRTCs but is DCE4, so also has 6 AFMTs
>

Oh, right.  I forgot about the 4 crtc parts.

Alex
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[PATCH 4/6] drm/radeon/evergreen: setup HDMI before enabling it

[Rafał Miłecki]

Closed source driver fglrx seems to enable infoframes and audio packets
at the end, which makes sense, do the same.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/gpu/drm/radeon/evergreen_hdmi.c |   15 +++++++++++----
 drivers/gpu/drm/radeon/evergreend.h     |    1 +
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index 8b64bf1..6b25c1b 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -116,7 +116,6 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
 	       HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
 
 	WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
-	       AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
 	       AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
 
 	WREG32(HDMI_ACR_PACKET_CONTROL + offset,
@@ -129,8 +128,6 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
 	       HDMI_GC_CONT); /* send general control packets every frame */
 
 	WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
-	       HDMI_AVI_INFO_SEND | /* enable AVI info frames */
-	       HDMI_AVI_INFO_CONT | /* send AVI info frames every frame/field */
 	       HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
 	       HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
 
@@ -138,7 +135,6 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
 	       AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
 
 	WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
-	       HDMI_AVI_INFO_LINE(2) | /* anything other than 0 */
 	       HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
 
 	WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
@@ -165,6 +161,14 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
 	evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
 	evergreen_hdmi_update_ACR(encoder, mode->clock);
 
+	WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset,
+		  HDMI_AVI_INFO_SEND | /* enable AVI info frames */
+		  HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */
+
+	WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
+		 HDMI_AVI_INFO_LINE(2), /* anything other than 0 */
+		 ~HDMI_AVI_INFO_LINE_MASK);
+
 	/*
 	 * At this point fglrx changes following regs:
 	 * DCE41: 0x7a70
@@ -172,6 +176,9 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
 	 * Is that something audio related?
 	 */
 
+	WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
+		  AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */
+
 	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
 	WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
 	WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 982d25a..e39e4f4 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -197,6 +197,7 @@
 #       define HDMI_MPEG_INFO_CONT           (1 << 9)
 #define HDMI_INFOFRAME_CONTROL1              0x7048
 #       define HDMI_AVI_INFO_LINE(x)         (((x) & 0x3f) << 0)
+#       define HDMI_AVI_INFO_LINE_MASK       (0x3f << 0)
 #       define HDMI_AUDIO_INFO_LINE(x)       (((x) & 0x3f) << 8)
 #       define HDMI_MPEG_INFO_LINE(x)        (((x) & 0x3f) << 16)
 #define HDMI_GENERIC_PACKET_CONTROL          0x704c
-- 
1.7.10.4

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Re: [PATCH 4/6] drm/radeon/evergreen: setup HDMI before enabling it

[Paul Menzel]

[-- Attachment #1.1: Type: text/plain, Size: 4096 bytes --]

Am Sonntag, den 14.04.2013, 01:26 +0200 schrieb Rafał Miłecki:
> Closed source driver fglrx seems to enable infoframes and audio packets
> at the end, which makes sense, do the same.

Any functionality change? Does not sound like it, but being unambiguous
is better.

> Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
> ---
>  drivers/gpu/drm/radeon/evergreen_hdmi.c |   15 +++++++++++----
>  drivers/gpu/drm/radeon/evergreend.h     |    1 +
>  2 files changed, 12 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> index 8b64bf1..6b25c1b 100644
> --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
> +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> @@ -116,7 +116,6 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
>  	       HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
>  
>  	WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
> -	       AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
>  	       AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
>  
>  	WREG32(HDMI_ACR_PACKET_CONTROL + offset,
> @@ -129,8 +128,6 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
>  	       HDMI_GC_CONT); /* send general control packets every frame */
>  
>  	WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
> -	       HDMI_AVI_INFO_SEND | /* enable AVI info frames */
> -	       HDMI_AVI_INFO_CONT | /* send AVI info frames every frame/field */
>  	       HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
>  	       HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
>  
> @@ -138,7 +135,6 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
>  	       AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
>  
>  	WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
> -	       HDMI_AVI_INFO_LINE(2) | /* anything other than 0 */
>  	       HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
>  
>  	WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
> @@ -165,6 +161,14 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
>  	evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
>  	evergreen_hdmi_update_ACR(encoder, mode->clock);
>  
> +	WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset,
> +		  HDMI_AVI_INFO_SEND | /* enable AVI info frames */
> +		  HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */
> +
> +	WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
> +		 HDMI_AVI_INFO_LINE(2), /* anything other than 0 */
> +		 ~HDMI_AVI_INFO_LINE_MASK);
> +
>  	/*
>  	 * At this point fglrx changes following regs:
>  	 * DCE41: 0x7a70
> @@ -172,6 +176,9 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
>  	 * Is that something audio related?
>  	 */
>  
> +	WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
> +		  AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */
> +
>  	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
>  	WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
>  	WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
> diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
> index 982d25a..e39e4f4 100644
> --- a/drivers/gpu/drm/radeon/evergreend.h
> +++ b/drivers/gpu/drm/radeon/evergreend.h
> @@ -197,6 +197,7 @@
>  #       define HDMI_MPEG_INFO_CONT           (1 << 9)
>  #define HDMI_INFOFRAME_CONTROL1              0x7048
>  #       define HDMI_AVI_INFO_LINE(x)         (((x) & 0x3f) << 0)
> +#       define HDMI_AVI_INFO_LINE_MASK       (0x3f << 0)

Is this in a data sheet?

>  #       define HDMI_AUDIO_INFO_LINE(x)       (((x) & 0x3f) << 8)
>  #       define HDMI_MPEG_INFO_LINE(x)        (((x) & 0x3f) << 16)
>  #define HDMI_GENERIC_PACKET_CONTROL          0x704c


Thanks,

Paul

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Re: [PATCH 4/6] drm/radeon/evergreen: setup HDMI before enabling it

[Rafał Miłecki]

2013/4/14 Paul Menzel <paulepanter@users.sourceforge.net>:
> Am Sonntag, den 14.04.2013, 01:26 +0200 schrieb Rafał Miłecki:
>> Closed source driver fglrx seems to enable infoframes and audio packets
>> at the end, which makes sense, do the same.
>
> Any functionality change? Does not sound like it, but being unambiguous
> is better.

No, just changing the order.


>> diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
>> index 982d25a..e39e4f4 100644
>> --- a/drivers/gpu/drm/radeon/evergreend.h
>> +++ b/drivers/gpu/drm/radeon/evergreend.h
>> @@ -197,6 +197,7 @@
>>  #       define HDMI_MPEG_INFO_CONT           (1 << 9)
>>  #define HDMI_INFOFRAME_CONTROL1              0x7048
>>  #       define HDMI_AVI_INFO_LINE(x)         (((x) & 0x3f) << 0)
>> +#       define HDMI_AVI_INFO_LINE_MASK       (0x3f << 0)
>
> Is this in a data sheet?

We don't have any HDMI related specs released. Just common sense.

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[PATCH 5/6] drm/radeon/evergreen: reorder HDMI setup

[Rafał Miłecki]

Driver fglrx setups audio and ACR packets after basic initialization,
which sounds sane, do the same.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/gpu/drm/radeon/evergreen_hdmi.c |   27 +++++++++++++++------------
 1 file changed, 15 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index 6b25c1b..24d13ac 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -111,17 +111,6 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
 
 	WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
 
-	WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
-	       HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
-	       HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
-
-	WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
-	       AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
-
-	WREG32(HDMI_ACR_PACKET_CONTROL + offset,
-	       HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
-	       HDMI_ACR_SOURCE); /* select SW CTS value */
-
 	WREG32(HDMI_VBI_PACKET_CONTROL + offset,
 	       HDMI_NULL_SEND | /* send null packets when required */
 	       HDMI_GC_SEND | /* send general control packets */
@@ -146,6 +135,21 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
 	 * Is that something audio related?
 	 */
 
+	WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
+	       HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
+	       HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
+
+	WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
+	       AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
+
+	/* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
+
+	WREG32(HDMI_ACR_PACKET_CONTROL + offset,
+	       HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
+	       HDMI_ACR_SOURCE); /* select SW CTS value */
+
+	evergreen_hdmi_update_ACR(encoder, mode->clock);
+
 	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 	if (err < 0) {
 		DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
@@ -159,7 +163,6 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
 	}
 
 	evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
-	evergreen_hdmi_update_ACR(encoder, mode->clock);
 
 	WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset,
 		  HDMI_AVI_INFO_SEND | /* enable AVI info frames */
-- 
1.7.10.4

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Re: [PATCH 5/6] drm/radeon/evergreen: reorder HDMI setup

[Paul Menzel]

[-- Attachment #1.1: Type: text/plain, Size: 3209 bytes --]

Am Sonntag, den 14.04.2013, 01:26 +0200 schrieb Rafał Miłecki:

Maybe use the following for a more descriptive summary:

drm/radeon/evergreen: Set up audio and ACR packets after basic init

> Driver fglrx setups audio and ACR packets after basic initialization,
> which sounds sane, do the same.

Could you also fix the typo?

»While doing so fix the typo suff*ic*ient in the comment (see below).«

Again, how should this be tested?

> Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
> ---
>  drivers/gpu/drm/radeon/evergreen_hdmi.c |   27 +++++++++++++++------------
>  1 file changed, 15 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> index 6b25c1b..24d13ac 100644
> --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
> +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> @@ -111,17 +111,6 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
>  
>  	WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
>  
> -	WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
> -	       HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
> -	       HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
> -
> -	WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
> -	       AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
> -
> -	WREG32(HDMI_ACR_PACKET_CONTROL + offset,
> -	       HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
> -	       HDMI_ACR_SOURCE); /* select SW CTS value */
> -
>  	WREG32(HDMI_VBI_PACKET_CONTROL + offset,
>  	       HDMI_NULL_SEND | /* send null packets when required */
>  	       HDMI_GC_SEND | /* send general control packets */
> @@ -146,6 +135,21 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
>  	 * Is that something audio related?
>  	 */
>  
> +	WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
> +	       HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
> +	       HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */

sufficient

> +
> +	WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
> +	       AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
> +
> +	/* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
> +
> +	WREG32(HDMI_ACR_PACKET_CONTROL + offset,
> +	       HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
> +	       HDMI_ACR_SOURCE); /* select SW CTS value */
> +
> +	evergreen_hdmi_update_ACR(encoder, mode->clock);
> +
>  	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
>  	if (err < 0) {
>  		DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
> @@ -159,7 +163,6 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
>  	}
>  
>  	evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
> -	evergreen_hdmi_update_ACR(encoder, mode->clock);
>  
>  	WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset,
>  		  HDMI_AVI_INFO_SEND | /* enable AVI info frames */


Thanks,

Paul

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Re: [PATCH 5/6] drm/radeon/evergreen: reorder HDMI setup

[Rafał Miłecki]

2013/4/14 Paul Menzel <paulepanter@users.sourceforge.net>:
> Am Sonntag, den 14.04.2013, 01:26 +0200 schrieb Rafał Miłecki:
>
> Maybe use the following for a more descriptive summary:
>
> drm/radeon/evergreen: Set up audio and ACR packets after basic init

That extra message you can see in my patch:
> Driver fglrx setups audio and ACR packets after basic initialization,
> which sounds sane, do the same.
isn't ignored by git and is also visible in "git log". So that should be fine.

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[PATCH V2 5/6] drm/radeon/evergreen: reorder HDMI setup

[Rafał Miłecki]

Driver fglrx setups audio and ACR packets after basic initialization,
which sounds sane, do the same.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
V2: typo in "sufficient"
---
 drivers/gpu/drm/radeon/evergreen_hdmi.c |   27 +++++++++++++++------------
 1 file changed, 15 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index 6b25c1b..f5e7bf3 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -111,17 +111,6 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
 
 	WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
 
-	WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
-	       HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
-	       HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
-
-	WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
-	       AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
-
-	WREG32(HDMI_ACR_PACKET_CONTROL + offset,
-	       HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
-	       HDMI_ACR_SOURCE); /* select SW CTS value */
-
 	WREG32(HDMI_VBI_PACKET_CONTROL + offset,
 	       HDMI_NULL_SEND | /* send null packets when required */
 	       HDMI_GC_SEND | /* send general control packets */
@@ -146,6 +135,21 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
 	 * Is that something audio related?
 	 */
 
+	WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
+	       HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
+	       HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be sufficient for all audio modes and small enough for all hblanks */
+
+	WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
+	       AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
+
+	/* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
+
+	WREG32(HDMI_ACR_PACKET_CONTROL + offset,
+	       HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
+	       HDMI_ACR_SOURCE); /* select SW CTS value */
+
+	evergreen_hdmi_update_ACR(encoder, mode->clock);
+
 	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 	if (err < 0) {
 		DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
@@ -159,7 +163,6 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
 	}
 
 	evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
-	evergreen_hdmi_update_ACR(encoder, mode->clock);
 
 	WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset,
 		  HDMI_AVI_INFO_SEND | /* enable AVI info frames */
-- 
1.7.10.4

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[PATCH 6/6] drm/radeon/evergreen: write default channel numbers

[Rafał Miłecki]

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/gpu/drm/radeon/evergreen_hdmi.c |   21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index 24d13ac..ed46dad 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -150,6 +150,27 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
 
 	evergreen_hdmi_update_ACR(encoder, mode->clock);
 
+	WREG32(AFMT_60958_0 + offset,
+	       AFMT_60958_CS_CHANNEL_NUMBER_L(1));
+
+	WREG32(AFMT_60958_1 + offset,
+	       AFMT_60958_CS_CHANNEL_NUMBER_R(2));
+
+	WREG32(AFMT_60958_2 + offset,
+	       AFMT_60958_CS_CHANNEL_NUMBER_2(3) |
+	       AFMT_60958_CS_CHANNEL_NUMBER_3(4) |
+	       AFMT_60958_CS_CHANNEL_NUMBER_4(5) |
+	       AFMT_60958_CS_CHANNEL_NUMBER_5(6) |
+	       AFMT_60958_CS_CHANNEL_NUMBER_6(7) |
+	       AFMT_60958_CS_CHANNEL_NUMBER_7(8));
+
+	/* fglrx sets 0x0001005f | (x & 0x00fc0000) in 0x5f78 here */
+
+	WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
+	       AFMT_AUDIO_CHANNEL_ENABLE(0xff));
+
+	/* fglrx sets 0x40 in 0x5f80 here */
+
 	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 	if (err < 0) {
 		DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
-- 
1.7.10.4

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Re: [PATCH 0/6] drm/radeon: minor HDMI improvements

[Alex Deucher]

[-- Attachment #1: Type: text/plain, Size: 1731 bytes --]

On Sat, Apr 13, 2013 at 7:26 PM, Rafał Miłecki <zajec5@gmail.com> wrote:
> I've managed to track fglrx operations on HDMI regs, so we can finally setup
> everything in (hopefully) the correct way and order.
>
> This changes HDMI setup on Evergreen to mostly match fglrx and was tested on:
> 1) AMD Radeon HD 6320 (PALM == DCE41)
> 2) AMD Radeon HD 6970M (BARTS == DCE5)
> No regressions noticed, I can still play audio, including LPCM, AC3 and DTS.
>
> Unfortunately I don't have any DCE4 hardware to test this, but that changes
> shouldn't cause any regressions. I hope that with such improvements we will
> finally able to enable audio by default.

I've applied patches 1, 4, 5, 6.  For patch 2, I'd prefer we just not
enable the interrupts rather than removing the code altogether at this
point.  See the attached patch.  For patch 3, none of the registers
mentioned are directly related to audio setup.

Alex

>
> Rafał Miłecki (6):
>   drm/radeon: add helpers for masking and setting bits in regs
>   drm/radeon: remove HDMI interrupts on Evergreen
>   drm/radeon: add some HDMI comments
>   drm/radeon/evergreen: setup HDMI before enabling it
>   drm/radeon/evergreen: reorder HDMI setup
>   drm/radeon/evergreen: write default channel numbers
>
>  drivers/gpu/drm/radeon/evergreen.c      |  127 +------------------------------
>  drivers/gpu/drm/radeon/evergreen_hdmi.c |   77 +++++++++++++++----
>  drivers/gpu/drm/radeon/evergreend.h     |    1 +
>  drivers/gpu/drm/radeon/r600_hdmi.c      |   16 ++--
>  drivers/gpu/drm/radeon/radeon.h         |    2 +
>  drivers/gpu/drm/radeon/radeon_display.c |    5 ++
>  6 files changed, 76 insertions(+), 152 deletions(-)
>
> --
> 1.7.10.4
>

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From 2a011eb7d763257e75b08c98adfb70a8d35ec6ae Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Thu, 18 Apr 2013 09:42:13 -0400
Subject: [PATCH] drm/radeon: disable audio format interrupts on Evergreen

The audio format change interrupts are an aid in debugging,
but not required for operation.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/radeon/r600_hdmi.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index e419b98..95397b2 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -461,7 +461,9 @@ void r600_hdmi_enable(struct drm_encoder *encoder)
 
 	if (rdev->irq.installed) {
 		/* if irq is available use it */
-		radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
+		/* XXX: shouldn't need this on any asics.  Double check DCE2/3 */
+		if (!ASIC_IS_DCE4(rdev))
+			radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
 	}
 
 	dig->afmt->enabled = true;
-- 
1.7.7.5


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Re: [PATCH 0/6] drm/radeon: minor HDMI improvements

[Rafał Miłecki]

2013/4/18 Alex Deucher <alexdeucher@gmail.com>:
> On Sat, Apr 13, 2013 at 7:26 PM, Rafał Miłecki <zajec5@gmail.com> wrote:
>> I've managed to track fglrx operations on HDMI regs, so we can finally setup
>> everything in (hopefully) the correct way and order.
>>
>> This changes HDMI setup on Evergreen to mostly match fglrx and was tested on:
>> 1) AMD Radeon HD 6320 (PALM == DCE41)
>> 2) AMD Radeon HD 6970M (BARTS == DCE5)
>> No regressions noticed, I can still play audio, including LPCM, AC3 and DTS.
>>
>> Unfortunately I don't have any DCE4 hardware to test this, but that changes
>> shouldn't cause any regressions. I hope that with such improvements we will
>> finally able to enable audio by default.
>
> I've applied patches 1, 4, 5, 6.  For patch 2, I'd prefer we just not
> enable the interrupts rather than removing the code altogether at this
> point.  See the attached patch.  For patch 3, none of the registers
> mentioned are directly related to audio setup.

I agree with that, thanks a lot for handling this patchset!

Your change from r600_hdmi.c should be probably also made in
r600_audio_chipset_supported.

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