[PATCH 1/7] MIPS: add detect_memory_region()

[PATCH 1/7] MIPS: add detect_memory_region()

[John Crispin]

Add a generic way of detecting the available RAM. This function is based on the
implementation already used by ath79.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/include/asm/bootinfo.h |    1 +
 arch/mips/kernel/setup.c         |   20 ++++++++++++++++++++
 2 files changed, 21 insertions(+)

diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index b71dd5b..4d2cdea 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -104,6 +104,7 @@ struct boot_mem_map {
 extern struct boot_mem_map boot_mem_map;
 
 extern void add_memory_region(phys_t start, phys_t size, long type);
+extern void detect_memory_region(phys_t start, phys_t sz_min,  phys_t sz_max);
 
 extern void prom_init(void);
 extern void prom_free_prom_memory(void);
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 4c774d5..dfe776a 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -23,6 +23,7 @@
 #include <linux/pfn.h>
 #include <linux/debugfs.h>
 #include <linux/kexec.h>
+#include <linux/sizes.h>
 
 #include <asm/addrspace.h>
 #include <asm/bootinfo.h>
@@ -122,6 +123,25 @@ void __init add_memory_region(phys_t start, phys_t size, long type)
 	boot_mem_map.nr_map++;
 }
 
+void __init detect_memory_region(phys_t start, phys_t sz_min,  phys_t sz_max)
+{
+	phys_t size;
+
+	for (size = sz_min; size < sz_max; size <<= 1) {
+		if (!memcmp(detect_memory_region,
+				detect_memory_region + size, 1024))
+			break;
+	}
+
+	pr_debug("Memory: %lluMB of RAM detected at 0x%llx (min: %lluMB, max: %lluMB)\n",
+		((unsigned long long) size) / SZ_1M,
+		(unsigned long long) start,
+		((unsigned long long) sz_min) / SZ_1M,
+		((unsigned long long) sz_max) / SZ_1M);
+
+	add_memory_region(start, size, BOOT_MEM_RAM);
+}
+
 static void __init print_memory_map(void)
 {
 	int i;
-- 
1.7.10.4

[PATCH 2/7] MIPS: ralink: add memory definition to struct ralink_soc_info

[John Crispin]

Depending on the actual SoC we have a different base address as well as minimum
and maximum size for RAM. Add these fields to the per SoC structure.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/ralink/common.h |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/mips/ralink/common.h b/arch/mips/ralink/common.h
index 299119b..83144c3 100644
--- a/arch/mips/ralink/common.h
+++ b/arch/mips/ralink/common.h
@@ -33,6 +33,11 @@ extern struct ralink_pinmux rt_gpio_pinmux;
 struct ralink_soc_info {
 	unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
 	unsigned char *compatible;
+
+	unsigned long mem_base;
+	unsigned long mem_size;
+	unsigned long mem_size_min;
+	unsigned long mem_size_max;
 };
 extern struct ralink_soc_info soc_info;
 
-- 
1.7.10.4

[PATCH 3/7] MIPS: ralink: add memory definition for RT305x

[John Crispin]

Populate struct soc_info with the data that describes our RAM window.

As memory detection fails on RT5350 we read the amount of available memory
from the system controller.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/include/asm/mach-ralink/rt305x.h |    6 ++++
 arch/mips/ralink/rt305x.c                  |   45 ++++++++++++++++++++++++++++
 2 files changed, 51 insertions(+)

diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h
index 80cda8a..e68afef 100644
--- a/arch/mips/include/asm/mach-ralink/rt305x.h
+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
@@ -157,4 +157,10 @@ static inline int soc_is_rt5350(void)
 #define RT3352_RSTCTRL_UDEV		BIT(25)
 #define RT3352_SYSCFG1_USB0_HOST_MODE	BIT(10)
 
+#define RT305X_SDRAM_BASE		0x00000000
+#define RT305X_MEM_SIZE_MIN		(2 * 1024 * 1024)
+#define RT305X_MEM_SIZE_MAX		(64 * 1024 * 1024)
+#define RT3352_MEM_SIZE_MIN		(2 * 1024 * 1024)
+#define RT3352_MEM_SIZE_MAX		(256 * 1024 * 1024)
+
 #endif
diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
index e9dbf8c..da85f10 100644
--- a/arch/mips/ralink/rt305x.c
+++ b/arch/mips/ralink/rt305x.c
@@ -122,6 +122,40 @@ struct ralink_pinmux rt_gpio_pinmux = {
 	.wdt_reset = rt305x_wdt_reset,
 };
 
+static unsigned long rt5350_get_mem_size(void)
+{
+	void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
+	unsigned long ret;
+	u32 t;
+
+	t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG);
+	t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) &
+		RT5350_SYSCFG0_DRAM_SIZE_MASK;
+
+	switch (t) {
+	case RT5350_SYSCFG0_DRAM_SIZE_2M:
+		ret = 2 * 1024 * 1024;
+		break;
+	case RT5350_SYSCFG0_DRAM_SIZE_8M:
+		ret = 8 * 1024 * 1024;
+		break;
+	case RT5350_SYSCFG0_DRAM_SIZE_16M:
+		ret = 16 * 1024 * 1024;
+		break;
+	case RT5350_SYSCFG0_DRAM_SIZE_32M:
+		ret = 32 * 1024 * 1024;
+		break;
+	case RT5350_SYSCFG0_DRAM_SIZE_64M:
+		ret = 64 * 1024 * 1024;
+		break;
+	default:
+		panic("rt5350: invalid DRAM size: %u", t);
+		break;
+	}
+
+	return ret;
+}
+
 void __init ralink_clk_init(void)
 {
 	unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
@@ -252,4 +286,15 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
 		name,
 		(id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
 		(id & CHIP_ID_REV_MASK));
+
+	soc_info->mem_base = RT305X_SDRAM_BASE;
+	if (soc_is_rt5350()) {
+		soc_info->mem_size = rt5350_get_mem_size();
+	} else if (soc_is_rt305x() || soc_is_rt3350()) {
+		soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
+		soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
+	} else if (soc_is_rt3352()) {
+		soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
+		soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
+	}
 }
-- 
1.7.10.4

[PATCH 4/7] MIPS: ralink: add memory definition for RT2880

[John Crispin]

Populate struct soc_info with the data that describes our RAM window.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/include/asm/mach-ralink/rt288x.h |    4 ++++
 arch/mips/ralink/rt288x.c                  |    4 ++++
 2 files changed, 8 insertions(+)

diff --git a/arch/mips/include/asm/mach-ralink/rt288x.h b/arch/mips/include/asm/mach-ralink/rt288x.h
index ad8b42d..459059b 100644
--- a/arch/mips/include/asm/mach-ralink/rt288x.h
+++ b/arch/mips/include/asm/mach-ralink/rt288x.h
@@ -46,4 +46,8 @@
 
 #define CLKCFG_SRAM_CS_N_WDT		BIT(9)
 
+#define RT2880_SDRAM_BASE		0x08000000
+#define RT2880_MEM_SIZE_MIN		(2 * 1024 * 1024)
+#define RT2880_MEM_SIZE_MAX		(128 * 1024 * 1024)
+
 #endif
diff --git a/arch/mips/ralink/rt288x.c b/arch/mips/ralink/rt288x.c
index 1e0788e..f87de1a 100644
--- a/arch/mips/ralink/rt288x.c
+++ b/arch/mips/ralink/rt288x.c
@@ -136,4 +136,8 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
 		name,
 		(id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
 		(id & CHIP_ID_REV_MASK));
+
+	soc_info->mem_base = RT2880_SDRAM_BASE;
+	soc_info->mem_size_min = RT2880_MEM_SIZE_MIN;
+	soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;
 }
-- 
1.7.10.4

[PATCH 5/7] MIPS: ralink: add memory definition for RT3883

[John Crispin]

Populate struct soc_info with the data that describes our RAM window.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/include/asm/mach-ralink/rt3883.h |    4 ++++
 arch/mips/ralink/rt3883.c                  |    4 ++++
 2 files changed, 8 insertions(+)

diff --git a/arch/mips/include/asm/mach-ralink/rt3883.h b/arch/mips/include/asm/mach-ralink/rt3883.h
index b91c6c1..7336cb6 100644
--- a/arch/mips/include/asm/mach-ralink/rt3883.h
+++ b/arch/mips/include/asm/mach-ralink/rt3883.h
@@ -244,4 +244,8 @@
 #define RT3883_FLASH_CFG_WIDTH_16BIT	0x1
 #define RT3883_FLASH_CFG_WIDTH_32BIT	0x2
 
+#define RT3883_SDRAM_BASE		0x00000000
+#define RT3883_MEM_SIZE_MIN		(2 * 1024 * 1024)
+#define RT3883_MEM_SIZE_MAX		(256 * 1024 * 1024)
+
 #endif /* _RT3883_REGS_H_ */
diff --git a/arch/mips/ralink/rt3883.c b/arch/mips/ralink/rt3883.c
index 2d90aa9..afbf2ce 100644
--- a/arch/mips/ralink/rt3883.c
+++ b/arch/mips/ralink/rt3883.c
@@ -239,4 +239,8 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
 		name,
 		(id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK,
 		(id & RT3883_REVID_ECO_ID_MASK));
+
+	soc_info->mem_base = RT3883_SDRAM_BASE;
+	soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
+	soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
 }
-- 
1.7.10.4

[PATCH 6/7] MIPS: ralink: add memory definition for MT7620

[John Crispin]

Populate struct soc_info with the data that describes our RAM window.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/include/asm/mach-ralink/mt7620.h |    8 ++++++++
 arch/mips/ralink/mt7620.c                  |   20 ++++++++++++++++++++
 2 files changed, 28 insertions(+)

diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
index b272649..915cedb 100644
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
@@ -50,6 +50,14 @@
 #define SYSCFG0_DRAM_TYPE_DDR1		1
 #define SYSCFG0_DRAM_TYPE_DDR2		2
 
+#define MT7620_DRAM_BASE		0x0
+#define MT7620_SDRAM_SIZE_MIN		(2 * 1024 * 1024)
+#define MT7620_SDRAM_SIZE_MAX		(64 * 1024 * 1024)
+#define MT7620_DDR1_SIZE_MIN		(32 * 1024 * 1024)
+#define MT7620_DDR1_SIZE_MAX		(128 * 1024 * 1024)
+#define MT7620_DDR2_SIZE_MIN		(32 * 1024 * 1024)
+#define MT7620_DDR2_SIZE_MAX		(256 * 1024 * 1024)
+
 #define MT7620_GPIO_MODE_I2C		BIT(0)
 #define MT7620_GPIO_MODE_UART0_SHIFT	2
 #define MT7620_GPIO_MODE_UART0_MASK	0x7
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
index eb00ab8..98ddb93 100644
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -211,4 +211,24 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
 
 	cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
 	dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
+
+	switch (dram_type) {
+	case SYSCFG0_DRAM_TYPE_SDRAM:
+		soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
+		soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
+		break;
+
+	case SYSCFG0_DRAM_TYPE_DDR1:
+		soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
+		soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
+		break;
+
+	case SYSCFG0_DRAM_TYPE_DDR2:
+		soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
+		soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
+		break;
+	default:
+		BUG();
+	}
+	soc_info->mem_base = MT7620_DRAM_BASE;
 }
-- 
1.7.10.4

[PATCH 7/7] MIPS: ralink: make use of the new memory detection code

[John Crispin]

Call detect_memory_region() from plat_mem_setup() unless the size was already
read from the system controller.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/ralink/of.c |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c
index 4165e70..d285ea8 100644
--- a/arch/mips/ralink/of.c
+++ b/arch/mips/ralink/of.c
@@ -85,6 +85,13 @@ void __init plat_mem_setup(void)
 	 * parsed resulting in our memory appearing
 	 */
 	__dt_setup_arch(&__dtb_start);
+
+	if (soc_info.mem_size)
+		add_memory_region(soc_info.mem_base, soc_info.mem_size,
+				  BOOT_MEM_RAM);
+	else
+		detect_memory_region(soc_info.mem_base, soc_info.mem_size_min,
+				     soc_info.mem_size_max);
 }
 
 static int __init plat_of_setup(void)
-- 
1.7.10.4

Re: [PATCH 1/7] MIPS: add detect_memory_region()

[Sergei Shtylyov]

Hello.

On 15-04-2013 14:41, John Crispin wrote:

> Add a generic way of detecting the available RAM. This function is based on the
> implementation already used by ath79.

> Signed-off-by: John Crispin <blogic@openwrt.org>
[...]

> diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
> index 4c774d5..dfe776a 100644
> --- a/arch/mips/kernel/setup.c
> +++ b/arch/mips/kernel/setup.c
[...]
> @@ -122,6 +123,25 @@ void __init add_memory_region(phys_t start, phys_t size, long type)
>   	boot_mem_map.nr_map++;
>   }
>
> +void __init detect_memory_region(phys_t start, phys_t sz_min,  phys_t sz_max)

    Minor formatting nit: too many spaces after the last comma.

WBR, Sergei

Re: [PATCH 3/7] MIPS: ralink: add memory definition for RT305x

[Sergei Shtylyov]

Hello.

On 15-04-2013 14:41, John Crispin wrote:

> Populate struct soc_info with the data that describes our RAM window.

> As memory detection fails on RT5350 we read the amount of available memory
> from the system controller.

> Signed-off-by: John Crispin <blogic@openwrt.org>
> ---
>   arch/mips/include/asm/mach-ralink/rt305x.h |    6 ++++
>   arch/mips/ralink/rt305x.c                  |   45 ++++++++++++++++++++++++++++
>   2 files changed, 51 insertions(+)

> diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h
> index 80cda8a..e68afef 100644
> --- a/arch/mips/include/asm/mach-ralink/rt305x.h
> +++ b/arch/mips/include/asm/mach-ralink/rt305x.h
> @@ -157,4 +157,10 @@ static inline int soc_is_rt5350(void)
>   #define RT3352_RSTCTRL_UDEV		BIT(25)
>   #define RT3352_SYSCFG1_USB0_HOST_MODE	BIT(10)
>
> +#define RT305X_SDRAM_BASE		0x00000000
> +#define RT305X_MEM_SIZE_MIN		(2 * 1024 * 1024)
> +#define RT305X_MEM_SIZE_MAX		(64 * 1024 * 1024)
> +#define RT3352_MEM_SIZE_MIN		(2 * 1024 * 1024)
> +#define RT3352_MEM_SIZE_MAX		(256 * 1024 * 1024)
> +
>   #endif
> diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
> index e9dbf8c..da85f10 100644
> --- a/arch/mips/ralink/rt305x.c
> +++ b/arch/mips/ralink/rt305x.c
> @@ -122,6 +122,40 @@ struct ralink_pinmux rt_gpio_pinmux = {
>   	.wdt_reset = rt305x_wdt_reset,
>   };
>
> +static unsigned long rt5350_get_mem_size(void)
> +{
> +	void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
> +	unsigned long ret;
> +	u32 t;
> +
> +	t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG);
> +	t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) &
> +		RT5350_SYSCFG0_DRAM_SIZE_MASK;
> +
> +	switch (t) {
> +	case RT5350_SYSCFG0_DRAM_SIZE_2M:
> +		ret = 2 * 1024 * 1024;
> +		break;
> +	case RT5350_SYSCFG0_DRAM_SIZE_8M:
> +		ret = 8 * 1024 * 1024;
> +		break;
> +	case RT5350_SYSCFG0_DRAM_SIZE_16M:
> +		ret = 16 * 1024 * 1024;
> +		break;
> +	case RT5350_SYSCFG0_DRAM_SIZE_32M:
> +		ret = 32 * 1024 * 1024;
> +		break;
> +	case RT5350_SYSCFG0_DRAM_SIZE_64M:
> +		ret = 64 * 1024 * 1024;
> +		break;
> +	default:

    Maybe it's worth including <linux/sizes.h> as well?

WBR, Sergei