* PMECC capability
@ 2013-04-26 10:17 Richard Genoud
2013-04-26 11:01 ` Josh Wu
0 siblings, 1 reply; 3+ messages in thread
From: Richard Genoud @ 2013-04-26 10:17 UTC (permalink / raw)
To: Josh Wu; +Cc: linux-mtd
Hi,
I've got a (dumb?) question about the error correct capability of atmel PMECC:
Do we have to use the exact error capability required by the nand
chipset or we can use a bigger one ?
use case:
I'm working on at91sam9g35-cm board which require 1 bit per 512bytes
correction and also on a at91sam9g35-cm+phy which require 4bits per
512bytes correction.
If I use for both a 4b/512B correction, this won't hurt ?
There won't be any strange side effect ?
Moreover, as I don't use the OOB data, I could set a 8b/512B correction.
Will it be completely useless ?
Regards,
Richard.
--
for me, ck means con kolivas and not calvin klein... does it mean I'm a geek ?
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: PMECC capability
2013-04-26 10:17 PMECC capability Richard Genoud
@ 2013-04-26 11:01 ` Josh Wu
2013-04-26 11:18 ` Richard Genoud
0 siblings, 1 reply; 3+ messages in thread
From: Josh Wu @ 2013-04-26 11:01 UTC (permalink / raw)
To: Richard Genoud; +Cc: linux-mtd
Hi, Richard
On 4/26/2013 6:17 PM, Richard Genoud wrote:
> Hi,
>
> I've got a (dumb?) question about the error correct capability of atmel PMECC:
> Do we have to use the exact error capability required by the nand
> chipset or we can use a bigger one ?
I think it is a very good question and I don't have answer yet.
And it bring up another question: Can the nand flash will got much error
bits than the ONFI minimum require?
Or the filesystem will make sure this situation rarely happen?
>
> use case:
> I'm working on at91sam9g35-cm board which require 1 bit per 512bytes
> correction and also on a at91sam9g35-cm+phy which require 4bits per
> 512bytes correction.
>
> If I use for both a 4b/512B correction, this won't hurt ?
> There won't be any strange side effect ?
I think it will not hurt. And since PMECC is hardware calculation,
performance should have no big impaction (I am not test that)
>
> Moreover, as I don't use the OOB data, I could set a 8b/512B correction.
> Will it be completely useless ?
I've seen one of mtd/nand driver (I don't remember the exact name), the
ECC capability is set as the max one base on the OOB valid size (exclude
the some used by filesystem).
Just in the moment, I think use the max error correct capability base on
valid OOB is safer for long time using.
Best Regards,
Josh Wu
>
>
> Regards,
>
> Richard.
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: PMECC capability
2013-04-26 11:01 ` Josh Wu
@ 2013-04-26 11:18 ` Richard Genoud
0 siblings, 0 replies; 3+ messages in thread
From: Richard Genoud @ 2013-04-26 11:18 UTC (permalink / raw)
To: Josh Wu; +Cc: linux-mtd
2013/4/26 Josh Wu <josh.wu@atmel.com>:
> Hi, Richard
>
>
> On 4/26/2013 6:17 PM, Richard Genoud wrote:
>>
>> Hi,
>>
>> I've got a (dumb?) question about the error correct capability of atmel
>> PMECC:
>> Do we have to use the exact error capability required by the nand
>> chipset or we can use a bigger one ?
>
>
> I think it is a very good question and I don't have answer yet.
> And it bring up another question: Can the nand flash will got much error
> bits than the ONFI minimum require?
I checked on the datasheet I've got, and in this case, they call it a
bad block :
"An invalid block is one that contains at least
one page that has more bad bits than can be corrected by the minimum
required ECC."
And I found also this sentence :
"Under typical conditions, use the minimum required ECC"
But it doesn't say that using a stronger ECC will kill kittens or not.
> Or the filesystem will make sure this situation rarely happen?
>
>
>>
>> use case:
>> I'm working on at91sam9g35-cm board which require 1 bit per 512bytes
>> correction and also on a at91sam9g35-cm+phy which require 4bits per
>> 512bytes correction.
>>
>> If I use for both a 4b/512B correction, this won't hurt ?
>> There won't be any strange side effect ?
>
>
> I think it will not hurt. And since PMECC is hardware calculation,
> performance should have no big impaction (I am not test that)
>
>
>>
>> Moreover, as I don't use the OOB data, I could set a 8b/512B correction.
>> Will it be completely useless ?
>
>
> I've seen one of mtd/nand driver (I don't remember the exact name), the ECC
> capability is set as the max one base on the OOB valid size (exclude the
> some used by filesystem).
>
> Just in the moment, I think use the max error correct capability base on
> valid OOB is safer for long time using.
>
> Best Regards,
> Josh Wu
>
>>
>>
>> Regards,
>>
>> Richard.
>>
>
Thanks for your replies !
Richard.
--
for me, ck means con kolivas and not calvin klein... does it mean I'm a geek ?
^ permalink raw reply [flat|nested] 3+ messages in thread
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