From: Richard Henderson <rth@twiddle.net>
To: Alexander Graf <agraf@suse.de>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
Torbjorn Granlund <tg@gmplib.org>
Subject: Re: [Qemu-devel] [PATCH] PPC: Depend behavior of cmp instructions only on instruction encoding
Date: Wed, 08 May 2013 08:30:26 -0500 [thread overview]
Message-ID: <518A5372.6040408@twiddle.net> (raw)
In-Reply-To: <1368019560-25218-1-git-send-email-agraf@suse.de>
On 2013-05-08 08:26, Alexander Graf wrote:
> However, the situation is more complex than that. On 32bit CPUs, L=1
> instructions are either treated identical to L=0 instructions (G4) or
> treated as illegal instructions (e500mc). Differenciating these cases
> is out of scope for the 1.5 release and will follow afterwards. For now
> just treat the 32bit CPU, 64bit cmp case as undefined.
Ah ha. Interesting g4/e500 difference.
Reviewed-by: Richard Henderson <rth@twiddle.net>
r~
next prev parent reply other threads:[~2013-05-08 13:31 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-05-08 13:26 [Qemu-devel] [PATCH] PPC: Depend behavior of cmp instructions only on instruction encoding Alexander Graf
2013-05-08 13:30 ` Richard Henderson [this message]
2013-05-08 13:49 ` Torbjorn Granlund
2013-05-08 13:51 ` Alexander Graf
2013-05-08 14:25 ` Aurelien Jarno
2013-05-08 14:48 ` Torbjorn Granlund
2013-05-08 15:04 ` Aurelien Jarno
2013-05-08 15:54 ` Torbjorn Granlund
2013-05-08 16:16 ` Aurelien Jarno
2013-05-08 16:31 ` Torbjorn Granlund
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