From: b32955@freescale.com (Huang Shijie)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/6] drivers: bus: add a new driver for WEIM
Date: Wed, 22 May 2013 16:30:03 +0800 [thread overview]
Message-ID: <519C820B.2080800@freescale.com> (raw)
In-Reply-To: <20130520131827.GB32299@pengutronix.de>
? 2013?05?20? 21:18, Sascha Hauer ??:
> On Mon, May 20, 2013 at 04:48:57PM +0800, Huang Shijie wrote:
>> weim-cs-index.
>> +
>> +Example for an i.MX6q-sabreauto board:
>> + weim: weim at 021b8000 {
>> + compatible = "fsl,imx6q-weim";
>> + reg =<0x021b8000 0x4000>;
>> + interrupts =<0 14 0x04>;
>> + clocks =<&clks 196>;
>> + #address-cells =<2>;
> Why is address cells 2 in this example?
Must be set to 2 to allow memory address translation.
>> + #size-cells =<1>;
>> + ranges =<0 0 0x08000000 0x08000000>;
>> +
>> + nor at 0,0 {
>> + compatible = "cfi-flash";
>> + reg =<0 0 0x02000000>;
>> + #address-cells =<1>;
>> + #size-cells =<1>;
>> + bank-width =<2>;
>> +
>> + weim-cs-index =<0>;
>> + weim-cs-timing =<0x00620081 0x00000001 0x1C022000
>> + 0x0000C000 0x1404a38e 0x00000000>;
>> + partition at 0 {
>> + label = "U-Boot";
>> + reg =<0x0 0x40000>;
>> + };
>> +
>> + partition at 40000 {
>> + label = "U-Boot-ENV";
>> + reg =<0x40000 0x10000>;
>> + read-only;
>> + };
>> +
>> + partition at 50000 {
>> + label = "Kernel";
>> + reg =<0x50000 0x3b0000>;
>> + };
> The partitions are unnecessary to understand the example. Please drop them.
okay.
>> +#define CS_TIMING_LEN 6
>> +#define CS_REG_RANGE 0x18
>> +/* Parse and set the timing for this device. */
>> +static int weim_timing(struct platform_device *pdev, struct device_node *np)
>> +{
>> + struct imx_weim *weim = platform_get_drvdata(pdev);
>> + u32 value[CS_TIMING_LEN];
>> + u32 cs_idx;
>> + int ret;
>> + int i;
>> +
>> + ret = of_property_read_u32(np, "weim-cs-index",&cs_idx);
>> + if (ret)
>> + goto weim_parse_err;
> It would be nice to check for cs_idx being valid.
>
>> +
>> + ret = of_property_read_u32_array(np, "weim-cs-timing",
>> + value, CS_TIMING_LEN);
>> + if (ret)
>> + goto weim_parse_err;
>> +
>> + /* set the timing for WEIM */
>> + for (i = 0; i< CS_TIMING_LEN; i++)
>> + writel(value[i], weim->base + cs_idx * CS_REG_RANGE + i * 4);
>> + return 0;
>> +
>> +weim_parse_err:
>> + return ret;
>> +}
>> +
>> +static int weim_parse_dt(struct platform_device *pdev)
>> +{
>> + struct device_node *child;
>> + int ret;
>> +
>> + /* We only support the Parallel NOR now. We may add more in future. */
>> + child = of_find_node_by_name(NULL, "nor");
>> + if (child) {
>> + ret = weim_timing(pdev, child);
>> + if (ret)
>> + goto parse_fail;
>> +
>> + if (!of_platform_device_create(child, NULL,&pdev->dev)) {
>> + ret = -EINVAL;
>> + goto parse_fail;
>> + }
>> + }
> What you want to do here is:
>
> - iterate over your child nodes
> - call weim_timing() for each of them
> - call of_platform_device_create for each child (or even
> of_platform_populate() with the parent node)
>
yes.
>> + return 0;
>> +
>> +parse_fail:
>> + return ret;
>> +}
>> +
>> +static int weim_probe(struct platform_device *pdev)
>> +{
>> + struct imx_weim *weim;
>> + struct resource *res;
>> + int ret = -EINVAL;
>> +
>> + weim = devm_kzalloc(&pdev->dev, sizeof(*weim), GFP_KERNEL);
>> + if (!weim) {
>> + ret = -ENOMEM;
>> + goto weim_err;
>> + }
>> + platform_set_drvdata(pdev, weim);
>> +
>> + /* get the resource */
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + if (!res) {
>> + ret = -ENOENT;
>> + goto weim_err;
>> + }
> No need to do error checking here. devm_ioremap_resource() will do this
> for you and also print an error message.
>
>> +
>> + weim->base = devm_ioremap_resource(&pdev->dev, res);
>> + if (IS_ERR(weim->base)) {
>> + ret = PTR_ERR(weim->base);
>> + goto weim_err;
>> + }
>> +
>> + /* get the clock */
>> + weim->clk = devm_clk_get(&pdev->dev, NULL);
>> + if (IS_ERR(weim->clk))
>> + goto weim_err;
>> +
>> + clk_prepare_enable(weim->clk);
> what is this clock used for? Is it necessary for the register access or
> is it necessary for the chipselects on the WEIM to work?
>
>
yes. We need this clock.
in actually, this clock is just a clock gate for several clocks,
including clock for register access, and
other necessary clocks.
thanks
Huang Shijie
.
WARNING: multiple messages have this Message-ID (diff)
From: Huang Shijie <b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
To: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Cc: grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: Re: [PATCH 1/6] drivers: bus: add a new driver for WEIM
Date: Wed, 22 May 2013 16:30:03 +0800 [thread overview]
Message-ID: <519C820B.2080800@freescale.com> (raw)
In-Reply-To: <20130520131827.GB32299-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
于 2013年05月20日 21:18, Sascha Hauer 写道:
> On Mon, May 20, 2013 at 04:48:57PM +0800, Huang Shijie wrote:
>> weim-cs-index.
>> +
>> +Example for an i.MX6q-sabreauto board:
>> + weim: weim@021b8000 {
>> + compatible = "fsl,imx6q-weim";
>> + reg =<0x021b8000 0x4000>;
>> + interrupts =<0 14 0x04>;
>> + clocks =<&clks 196>;
>> + #address-cells =<2>;
> Why is address cells 2 in this example?
Must be set to 2 to allow memory address translation.
>> + #size-cells =<1>;
>> + ranges =<0 0 0x08000000 0x08000000>;
>> +
>> + nor@0,0 {
>> + compatible = "cfi-flash";
>> + reg =<0 0 0x02000000>;
>> + #address-cells =<1>;
>> + #size-cells =<1>;
>> + bank-width =<2>;
>> +
>> + weim-cs-index =<0>;
>> + weim-cs-timing =<0x00620081 0x00000001 0x1C022000
>> + 0x0000C000 0x1404a38e 0x00000000>;
>> + partition@0 {
>> + label = "U-Boot";
>> + reg =<0x0 0x40000>;
>> + };
>> +
>> + partition@40000 {
>> + label = "U-Boot-ENV";
>> + reg =<0x40000 0x10000>;
>> + read-only;
>> + };
>> +
>> + partition@50000 {
>> + label = "Kernel";
>> + reg =<0x50000 0x3b0000>;
>> + };
> The partitions are unnecessary to understand the example. Please drop them.
okay.
>> +#define CS_TIMING_LEN 6
>> +#define CS_REG_RANGE 0x18
>> +/* Parse and set the timing for this device. */
>> +static int weim_timing(struct platform_device *pdev, struct device_node *np)
>> +{
>> + struct imx_weim *weim = platform_get_drvdata(pdev);
>> + u32 value[CS_TIMING_LEN];
>> + u32 cs_idx;
>> + int ret;
>> + int i;
>> +
>> + ret = of_property_read_u32(np, "weim-cs-index",&cs_idx);
>> + if (ret)
>> + goto weim_parse_err;
> It would be nice to check for cs_idx being valid.
>
>> +
>> + ret = of_property_read_u32_array(np, "weim-cs-timing",
>> + value, CS_TIMING_LEN);
>> + if (ret)
>> + goto weim_parse_err;
>> +
>> + /* set the timing for WEIM */
>> + for (i = 0; i< CS_TIMING_LEN; i++)
>> + writel(value[i], weim->base + cs_idx * CS_REG_RANGE + i * 4);
>> + return 0;
>> +
>> +weim_parse_err:
>> + return ret;
>> +}
>> +
>> +static int weim_parse_dt(struct platform_device *pdev)
>> +{
>> + struct device_node *child;
>> + int ret;
>> +
>> + /* We only support the Parallel NOR now. We may add more in future. */
>> + child = of_find_node_by_name(NULL, "nor");
>> + if (child) {
>> + ret = weim_timing(pdev, child);
>> + if (ret)
>> + goto parse_fail;
>> +
>> + if (!of_platform_device_create(child, NULL,&pdev->dev)) {
>> + ret = -EINVAL;
>> + goto parse_fail;
>> + }
>> + }
> What you want to do here is:
>
> - iterate over your child nodes
> - call weim_timing() for each of them
> - call of_platform_device_create for each child (or even
> of_platform_populate() with the parent node)
>
yes.
>> + return 0;
>> +
>> +parse_fail:
>> + return ret;
>> +}
>> +
>> +static int weim_probe(struct platform_device *pdev)
>> +{
>> + struct imx_weim *weim;
>> + struct resource *res;
>> + int ret = -EINVAL;
>> +
>> + weim = devm_kzalloc(&pdev->dev, sizeof(*weim), GFP_KERNEL);
>> + if (!weim) {
>> + ret = -ENOMEM;
>> + goto weim_err;
>> + }
>> + platform_set_drvdata(pdev, weim);
>> +
>> + /* get the resource */
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + if (!res) {
>> + ret = -ENOENT;
>> + goto weim_err;
>> + }
> No need to do error checking here. devm_ioremap_resource() will do this
> for you and also print an error message.
>
>> +
>> + weim->base = devm_ioremap_resource(&pdev->dev, res);
>> + if (IS_ERR(weim->base)) {
>> + ret = PTR_ERR(weim->base);
>> + goto weim_err;
>> + }
>> +
>> + /* get the clock */
>> + weim->clk = devm_clk_get(&pdev->dev, NULL);
>> + if (IS_ERR(weim->clk))
>> + goto weim_err;
>> +
>> + clk_prepare_enable(weim->clk);
> what is this clock used for? Is it necessary for the register access or
> is it necessary for the chipselects on the WEIM to work?
>
>
yes. We need this clock.
in actually, this clock is just a clock gate for several clocks,
including clock for register access, and
other necessary clocks.
thanks
Huang Shijie
.
_______________________________________________
devicetree-discuss mailing list
devicetree-discuss@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/devicetree-discuss
WARNING: multiple messages have this Message-ID (diff)
From: Huang Shijie <b32955@freescale.com>
To: Sascha Hauer <s.hauer@pengutronix.de>
Cc: <grant.likely@linaro.org>, <devicetree-discuss@lists.ozlabs.org>,
<linux-kernel@vger.kernel.org>, <rob.herring@calxeda.com>,
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 1/6] drivers: bus: add a new driver for WEIM
Date: Wed, 22 May 2013 16:30:03 +0800 [thread overview]
Message-ID: <519C820B.2080800@freescale.com> (raw)
In-Reply-To: <20130520131827.GB32299@pengutronix.de>
于 2013年05月20日 21:18, Sascha Hauer 写道:
> On Mon, May 20, 2013 at 04:48:57PM +0800, Huang Shijie wrote:
>> weim-cs-index.
>> +
>> +Example for an i.MX6q-sabreauto board:
>> + weim: weim@021b8000 {
>> + compatible = "fsl,imx6q-weim";
>> + reg =<0x021b8000 0x4000>;
>> + interrupts =<0 14 0x04>;
>> + clocks =<&clks 196>;
>> + #address-cells =<2>;
> Why is address cells 2 in this example?
Must be set to 2 to allow memory address translation.
>> + #size-cells =<1>;
>> + ranges =<0 0 0x08000000 0x08000000>;
>> +
>> + nor@0,0 {
>> + compatible = "cfi-flash";
>> + reg =<0 0 0x02000000>;
>> + #address-cells =<1>;
>> + #size-cells =<1>;
>> + bank-width =<2>;
>> +
>> + weim-cs-index =<0>;
>> + weim-cs-timing =<0x00620081 0x00000001 0x1C022000
>> + 0x0000C000 0x1404a38e 0x00000000>;
>> + partition@0 {
>> + label = "U-Boot";
>> + reg =<0x0 0x40000>;
>> + };
>> +
>> + partition@40000 {
>> + label = "U-Boot-ENV";
>> + reg =<0x40000 0x10000>;
>> + read-only;
>> + };
>> +
>> + partition@50000 {
>> + label = "Kernel";
>> + reg =<0x50000 0x3b0000>;
>> + };
> The partitions are unnecessary to understand the example. Please drop them.
okay.
>> +#define CS_TIMING_LEN 6
>> +#define CS_REG_RANGE 0x18
>> +/* Parse and set the timing for this device. */
>> +static int weim_timing(struct platform_device *pdev, struct device_node *np)
>> +{
>> + struct imx_weim *weim = platform_get_drvdata(pdev);
>> + u32 value[CS_TIMING_LEN];
>> + u32 cs_idx;
>> + int ret;
>> + int i;
>> +
>> + ret = of_property_read_u32(np, "weim-cs-index",&cs_idx);
>> + if (ret)
>> + goto weim_parse_err;
> It would be nice to check for cs_idx being valid.
>
>> +
>> + ret = of_property_read_u32_array(np, "weim-cs-timing",
>> + value, CS_TIMING_LEN);
>> + if (ret)
>> + goto weim_parse_err;
>> +
>> + /* set the timing for WEIM */
>> + for (i = 0; i< CS_TIMING_LEN; i++)
>> + writel(value[i], weim->base + cs_idx * CS_REG_RANGE + i * 4);
>> + return 0;
>> +
>> +weim_parse_err:
>> + return ret;
>> +}
>> +
>> +static int weim_parse_dt(struct platform_device *pdev)
>> +{
>> + struct device_node *child;
>> + int ret;
>> +
>> + /* We only support the Parallel NOR now. We may add more in future. */
>> + child = of_find_node_by_name(NULL, "nor");
>> + if (child) {
>> + ret = weim_timing(pdev, child);
>> + if (ret)
>> + goto parse_fail;
>> +
>> + if (!of_platform_device_create(child, NULL,&pdev->dev)) {
>> + ret = -EINVAL;
>> + goto parse_fail;
>> + }
>> + }
> What you want to do here is:
>
> - iterate over your child nodes
> - call weim_timing() for each of them
> - call of_platform_device_create for each child (or even
> of_platform_populate() with the parent node)
>
yes.
>> + return 0;
>> +
>> +parse_fail:
>> + return ret;
>> +}
>> +
>> +static int weim_probe(struct platform_device *pdev)
>> +{
>> + struct imx_weim *weim;
>> + struct resource *res;
>> + int ret = -EINVAL;
>> +
>> + weim = devm_kzalloc(&pdev->dev, sizeof(*weim), GFP_KERNEL);
>> + if (!weim) {
>> + ret = -ENOMEM;
>> + goto weim_err;
>> + }
>> + platform_set_drvdata(pdev, weim);
>> +
>> + /* get the resource */
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + if (!res) {
>> + ret = -ENOENT;
>> + goto weim_err;
>> + }
> No need to do error checking here. devm_ioremap_resource() will do this
> for you and also print an error message.
>
>> +
>> + weim->base = devm_ioremap_resource(&pdev->dev, res);
>> + if (IS_ERR(weim->base)) {
>> + ret = PTR_ERR(weim->base);
>> + goto weim_err;
>> + }
>> +
>> + /* get the clock */
>> + weim->clk = devm_clk_get(&pdev->dev, NULL);
>> + if (IS_ERR(weim->clk))
>> + goto weim_err;
>> +
>> + clk_prepare_enable(weim->clk);
> what is this clock used for? Is it necessary for the register access or
> is it necessary for the chipselects on the WEIM to work?
>
>
yes. We need this clock.
in actually, this clock is just a clock gate for several clocks,
including clock for register access, and
other necessary clocks.
thanks
Huang Shijie
.
next prev parent reply other threads:[~2013-05-22 8:30 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-05-20 8:48 [PATCH 0/6] ARM: imx6q{dl}: add the WEIM driver Huang Shijie
2013-05-20 8:48 ` Huang Shijie
2013-05-20 8:48 ` Huang Shijie
2013-05-20 8:48 ` [PATCH 1/6] drivers: bus: add a new driver for WEIM Huang Shijie
2013-05-20 8:48 ` Huang Shijie
2013-05-20 8:48 ` Huang Shijie
2013-05-20 13:18 ` Sascha Hauer
2013-05-20 13:18 ` Sascha Hauer
2013-05-20 13:18 ` Sascha Hauer
2013-05-22 8:30 ` Huang Shijie [this message]
2013-05-22 8:30 ` Huang Shijie
2013-05-22 8:30 ` Huang Shijie
2013-05-21 5:43 ` Shawn Guo
2013-05-21 5:43 ` Shawn Guo
2013-05-21 5:43 ` Shawn Guo
2013-05-22 8:16 ` Huang Shijie
2013-05-22 8:16 ` Huang Shijie
2013-05-22 8:16 ` Huang Shijie
2013-05-22 12:59 ` Arnd Bergmann
2013-05-22 12:59 ` Arnd Bergmann
2013-05-22 12:59 ` Arnd Bergmann
2013-05-23 2:17 ` Huang Shijie
2013-05-23 2:17 ` Huang Shijie
2013-05-23 2:17 ` Huang Shijie
2013-05-20 8:48 ` [PATCH 2/6] ARM: dts: imx6q{dl}: fix the pin conflict between SPI and WEIM Huang Shijie
2013-05-20 8:48 ` Huang Shijie
2013-05-20 8:48 ` Huang Shijie
2013-05-21 5:49 ` Shawn Guo
2013-05-21 5:49 ` Shawn Guo
2013-05-21 5:49 ` Shawn Guo
2013-05-21 5:53 ` Huang Shijie
2013-05-21 5:53 ` Huang Shijie
2013-05-21 5:53 ` Huang Shijie
2013-05-20 8:48 ` [PATCH 3/6] ARM: dts: imx6qdl: add more information for WEIM Huang Shijie
2013-05-20 8:48 ` Huang Shijie
2013-05-20 8:48 ` Huang Shijie
2013-05-20 8:49 ` [PATCH 4/6] ARM: dts: imx6q: add pinctrl for WEIM NOR Huang Shijie
2013-05-20 8:49 ` Huang Shijie
2013-05-20 8:49 ` Huang Shijie
2013-05-20 8:49 ` [PATCH 5/6] ARM: dts: imx6ql: add a " Huang Shijie
2013-05-20 8:49 ` Huang Shijie
2013-05-20 8:49 ` Huang Shijie
2013-05-20 8:49 ` [PATCH 6/6] ARM: dts: imx6qdl: enable the " Huang Shijie
2013-05-20 8:49 ` Huang Shijie
2013-05-20 8:49 ` Huang Shijie
-- strict thread matches above, loose matches on Subject: below --
2013-05-21 16:29 [PATCH 1/6] drivers: bus: add a new driver for WEIM Chaiken, Alison
[not found] ` <60BA5429A0E1584BA3633194F6F993B50252C924-0dz9ie/QGrnnlEkxMdpx1dQH9K4/4qFeAL8bYrjMMd8@public.gmane.org>
2013-05-22 8:01 ` Huang Shijie
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=519C820B.2080800@freescale.com \
--to=b32955@freescale.com \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.