[PATCH] drm/nouveau: perform a bar flush when flushing vm

[PATCH] drm/nouveau: perform a bar flush when flushing vm

[Maarten Lankhorst]

Appears to fix the regression from "drm/nvc0/vm: handle bar tlb flushes internally".
nvidia always seems to do this flush after writing values.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
---
diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c
index 83c62a7..5de0756 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c
@@ -27,6 +27,7 @@
 
 #include <subdev/timer.h>
 #include <subdev/fb.h>
+#include <subdev/bar.h>
 #include <subdev/vm.h>
 
 struct nv50_vmmgr_priv {
@@ -151,9 +152,12 @@ static void
 nv50_vm_flush(struct nouveau_vm *vm)
 {
 	struct nv50_vmmgr_priv *priv = (void *)vm->vmm;
+	struct nouveau_bar *bar = nouveau_bar(priv);
 	struct nouveau_engine *engine;
 	int i, vme;
 
+	bar->flush(bar);
+
 	mutex_lock(&nv_subdev(priv)->mutex);
 	for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
 		if (!atomic_read(&vm->engref[i]))
diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c
index 6c3aea5..668cf96 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c
@@ -29,6 +29,7 @@
 #include <subdev/fb.h>
 #include <subdev/vm.h>
 #include <subdev/ltcg.h>
+#include <subdev/bar.h>
 
 struct nvc0_vmmgr_priv {
 	struct nouveau_vmmgr base;
@@ -163,9 +164,12 @@ static void
 nvc0_vm_flush(struct nouveau_vm *vm)
 {
 	struct nvc0_vmmgr_priv *priv = (void *)vm->vmm;
+	struct nouveau_bar *bar = nouveau_bar(priv);
 	struct nouveau_vm_pgd *vpgd;
 	u32 type;
 
+	bar->flush(bar);
+
 	type = 0x00000001; /* PAGE_ALL */
 	if (atomic_read(&vm->engref[NVDEV_SUBDEV_BAR]))
 		type |= 0x00000004; /* HUB_ONLY */

Re: [PATCH] drm/nouveau: perform a bar flush when flushing vm

[Ben Skeggs]

On Tue, Jun 11, 2013 at 10:17 PM, Maarten Lankhorst
<maarten.lankhorst@canonical.com> wrote:
> Appears to fix the regression from "drm/nvc0/vm: handle bar tlb flushes internally".
> nvidia always seems to do this flush after writing values.
Thanks, patch applied.

>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
> ---
> diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c
> index 83c62a7..5de0756 100644
> --- a/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c
> +++ b/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c
> @@ -27,6 +27,7 @@
>
>  #include <subdev/timer.h>
>  #include <subdev/fb.h>
> +#include <subdev/bar.h>
>  #include <subdev/vm.h>
>
>  struct nv50_vmmgr_priv {
> @@ -151,9 +152,12 @@ static void
>  nv50_vm_flush(struct nouveau_vm *vm)
>  {
>         struct nv50_vmmgr_priv *priv = (void *)vm->vmm;
> +       struct nouveau_bar *bar = nouveau_bar(priv);
>         struct nouveau_engine *engine;
>         int i, vme;
>
> +       bar->flush(bar);
> +
>         mutex_lock(&nv_subdev(priv)->mutex);
>         for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
>                 if (!atomic_read(&vm->engref[i]))
> diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c
> index 6c3aea5..668cf96 100644
> --- a/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c
> +++ b/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c
> @@ -29,6 +29,7 @@
>  #include <subdev/fb.h>
>  #include <subdev/vm.h>
>  #include <subdev/ltcg.h>
> +#include <subdev/bar.h>
>
>  struct nvc0_vmmgr_priv {
>         struct nouveau_vmmgr base;
> @@ -163,9 +164,12 @@ static void
>  nvc0_vm_flush(struct nouveau_vm *vm)
>  {
>         struct nvc0_vmmgr_priv *priv = (void *)vm->vmm;
> +       struct nouveau_bar *bar = nouveau_bar(priv);
>         struct nouveau_vm_pgd *vpgd;
>         u32 type;
>
> +       bar->flush(bar);
> +
>         type = 0x00000001; /* PAGE_ALL */
>         if (atomic_read(&vm->engref[NVDEV_SUBDEV_BAR]))
>                 type |= 0x00000004; /* HUB_ONLY */
>
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