From: Suravee Suthikulanit <suravee.suthikulpanit@amd.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: Tim Deegan <tim@xen.org>,
xen-devel@lists.xen.org, Jacob Shin <Jacob.Shin@amd.com>,
Sherry Hurwitz <sherry.hurwitz@amd.com>
Subject: Re: [PATCH 1/2 v5] iommu/amd: Fix logic for clearing the IOMMU interrupt bits
Date: Thu, 13 Jun 2013 11:34:09 -0500 [thread overview]
Message-ID: <51B9F481.50204@amd.com> (raw)
In-Reply-To: <51BA082C02000078000DE0C0@nat28.tlf.novell.com>
On 6/13/2013 10:58 AM, Jan Beulich wrote:
>>>> On 13.06.13 at 03:44, Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> wrote:
>> The following commit broke the IOMMU MSI interrupt:
>>
>> 2012-11-28 899110e3f6d2a191638e8b50a981c551eeec49e6 AMD IOMMU:
>> include IOMMU interrupt information in 'M' debug key output
>> (http://xenbits.xen.org/gitweb/?p=xen.git;a=commit;h=899110e3f6d2a191638e8b5
>> 0a981c551eeec49e6)
> Having gone over the changes again, this still looks pretty innocent/
> mechanical to me - I can't see what may have got broken.
> Considering that this is the change adding respective information to
> 'M' output - what does 'M' show for the IOMMU entry/entries?
>
> Jan
>
>
Basically, the only different is this line that only appears in the "Bad" version.
(XEN) MSI 56 vec=28 fixed edge deassert phys cpu dest=00000001 mask=0/0/1
"xl debug-key i" also show the following information
(XEN) IRQ: 56 affinity:1 vec:28 type=AMD-IOMMU-MSI status=00000000 mapped, unbound
Not sure what "status=0" means.
Before: (Good)
(XEN) MSI information:
(XEN) MSI 57 vec=c0 lowest edge assert log lowest dest=00000001 mask=0/1/1
(XEN) MSI 58 vec=c8 lowest edge assert log lowest dest=00000001 mask=0/1/1
(XEN) MSI 59 vec=d0 lowest edge assert log lowest dest=00000001 mask=0/1/1
(XEN) MSI 60 vec=d8 lowest edge assert log lowest dest=00000001 mask=0/1/1
(XEN) MSI 61 vec=29 lowest edge assert log lowest dest=00000001 mask=0/1/1
(XEN) MSI-X 62 vec=31 lowest edge assert log lowest dest=00000001 mask=1/0/0
(XEN) MSI-X 63 vec=39 lowest edge assert log lowest dest=00000001 mask=1/0/0
(XEN) MSI-X 64 vec=41 lowest edge assert log lowest dest=00000001 mask=1/0/0
(XEN) MSI-X 65 vec=49 lowest edge assert log lowest dest=00000001 mask=1/0/0
(XEN) MSI-X 66 vec=51 lowest edge assert log lowest dest=00000001 mask=1/0/0
(XEN) MSI-X 67 vec=59 lowest edge assert log lowest dest=00000001 mask=1/0/0
(XEN) MSI 68 vec=69 lowest edge assert log lowest dest=00000001 mask=0/1/1
(XEN) MSI-X 69 vec=79 lowest edge assert log lowest dest=00000003 mask=1/1/1
(XEN) MSI-X 70 vec=81 lowest edge assert log lowest dest=00000003 mask=1/1/1
(XEN) MSI-X 71 vec=89 lowest edge assert log lowest dest=00000003 mask=1/1/1
(XEN) MSI-X 72 vec=99 lowest edge assert log lowest dest=00000001 mask=1/0/0
(XEN) MSI-X 73 vec=a1 lowest edge assert log lowest dest=00000002 mask=1/0/0
(XEN) MSI-X 74 vec=a9 lowest edge assert log lowest dest=00000001 mask=1/0/0
(XEN) MSI 75 vec=b9 lowest edge assert log lowest dest=00000001 mask=0/1/1
(XEN) MSI 76 vec=c1 lowest edge assert log lowest dest=00000001 mask=0/1/1
After: (Bad)
(XEN) MSI information:
(XEN) MSI 56 vec=28 fixed edge deassert phys cpu dest=00000001 mask=0/0/1
(XEN) MSI 57 vec=c0 lowest edge assert log lowest dest=00000001 mask=0/1/1
(XEN) MSI 58 vec=c8 lowest edge assert log lowest dest=00000001 mask=0/1/1
(XEN) MSI 59 vec=d0 lowest edge assert log lowest dest=00000001 mask=0/1/1
(XEN) MSI 60 vec=d8 lowest edge assert log lowest dest=00000001 mask=0/1/1
(XEN) MSI 61 vec=29 lowest edge assert log lowest dest=00000001 mask=0/1/1
(XEN) MSI-X 62 vec=31 lowest edge assert log lowest dest=00000001 mask=1/0/0
(XEN) MSI-X 63 vec=39 lowest edge assert log lowest dest=00000001 mask=1/0/0
(XEN) MSI-X 64 vec=41 lowest edge assert log lowest dest=00000001 mask=1/0/0
(XEN) MSI-X 65 vec=49 lowest edge assert log lowest dest=00000001 mask=1/0/0
(XEN) MSI-X 66 vec=51 lowest edge assert log lowest dest=00000001 mask=1/0/0
(XEN) MSI-X 67 vec=59 lowest edge assert log lowest dest=00000001 mask=1/0/0
(XEN) MSI 68 vec=71 lowest edge assert log lowest dest=00000001 mask=0/1/1
(XEN) MSI-X 69 vec=79 lowest edge assert log lowest dest=00000003 mask=1/1/1
(XEN) MSI-X 70 vec=81 lowest edge assert log lowest dest=00000003 mask=1/1/1
(XEN) MSI-X 71 vec=89 lowest edge assert log lowest dest=00000003 mask=1/1/1
(XEN) MSI-X 72 vec=99 lowest edge assert log lowest dest=00000001 mask=1/0/0
(XEN) MSI-X 73 vec=a1 lowest edge assert log lowest dest=00000002 mask=1/0/0
(XEN) MSI-X 74 vec=a9 lowest edge assert log lowest dest=00000001 mask=1/0/0
(XEN) MSI 75 vec=b9 lowest edge assert log lowest dest=00000001 mask=0/1/1
(XEN) MSI 76 vec=c1 lowest edge assert log lowest dest=00000001 mask=0/1/1
Suravee
next prev parent reply other threads:[~2013-06-13 16:34 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-10 5:05 [PATCH 1/2 V2] iommu/amd: Fix logic for clearing the IOMMU interrupt bits suravee.suthikulpanit
2013-06-10 5:05 ` [PATCH 2/2 V2] iommu/amd: Workaround for erratum 787 suravee.suthikulpanit
2013-06-10 9:35 ` Tim Deegan
2013-06-10 9:47 ` Jan Beulich
2013-06-10 10:40 ` Tim Deegan
2013-06-10 10:53 ` Jan Beulich
2013-06-10 12:43 ` Tim Deegan
2013-06-10 13:23 ` Jan Beulich
2013-06-10 13:41 ` Jan Beulich
2013-06-10 13:56 ` Tim Deegan
2013-06-10 13:55 ` Jan Beulich
2013-06-10 15:03 ` Jan Beulich
2013-06-10 16:31 ` Tim Deegan
2013-06-10 23:13 ` Suravee Suthikulanit
2013-06-11 6:45 ` Jan Beulich
2013-06-11 6:40 ` Jan Beulich
2013-06-11 8:53 ` Tim Deegan
2013-06-10 13:53 ` Suravee Suthikulanit
2013-06-10 13:59 ` Jan Beulich
2013-06-10 15:11 ` Suravee Suthikulanit
2013-06-10 15:21 ` Jan Beulich
2013-06-10 10:59 ` [PATCH 2/2 v3] " Jan Beulich
2013-06-11 6:47 ` [PATCH 2/2 v5] " Jan Beulich
2013-06-17 18:57 ` Suravee Suthikulanit
2013-06-10 10:05 ` [PATCH 1/2 V2] iommu/amd: Fix logic for clearing the IOMMU interrupt bits Jan Beulich
2013-06-10 10:56 ` [PATCH 1/2 v3] " Jan Beulich
2013-06-10 11:02 ` Jan Beulich
2013-06-10 12:18 ` Tim Deegan
2013-06-10 12:31 ` Jan Beulich
2013-06-10 13:58 ` Suravee Suthikulanit
2013-06-10 12:41 ` [PATCH 1/2 v4] " Jan Beulich
2013-06-10 12:46 ` Tim Deegan
2013-06-10 13:49 ` George Dunlap
2013-06-10 14:08 ` Jan Beulich
2013-06-11 6:47 ` [PATCH 1/2 v5] " Jan Beulich
2013-06-11 23:03 ` Suravee Suthikulanit
2013-06-12 6:24 ` Jan Beulich
2013-06-12 22:37 ` Suravee Suthikulpanit
2013-06-13 1:44 ` Suravee Suthikulpanit
2013-06-13 7:54 ` Jan Beulich
2013-06-13 13:48 ` Suravee Suthikulpanit
2013-06-13 14:20 ` George Dunlap
2013-06-13 14:30 ` Processed: " xen
2013-06-13 15:58 ` Jan Beulich
2013-06-13 16:34 ` Suravee Suthikulanit [this message]
2013-06-14 6:27 ` Jan Beulich
2013-06-14 6:40 ` Jan Beulich
2013-06-14 7:14 ` [PATCH] AMD IOMMU: make interrupt work again Jan Beulich
2013-06-14 16:10 ` Suravee Suthikulanit
2013-06-17 18:59 ` [PATCH 1/2 v5] iommu/amd: Fix logic for clearing the IOMMU interrupt bits Suravee Suthikulanit
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