* [PATCH 1/3] clk: exynos4: Staticize local symbols
@ 2013-04-16 10:05 Sachin Kamat
2013-04-16 10:05 ` [PATCH 2/3] clk: exynos5250: " Sachin Kamat
` (5 more replies)
0 siblings, 6 replies; 13+ messages in thread
From: Sachin Kamat @ 2013-04-16 10:05 UTC (permalink / raw)
To: linux-samsung-soc
Cc: kgene.kim, mturquette, thomas.abraham, sachin.kamat, patches
These symbols are used only in this file and hence should be
static.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
---
drivers/clk/samsung/clk-exynos4.c | 26 ++++++++++++++------------
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 7104669..26f2a85 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -339,24 +339,26 @@ PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
/* fixed rate clocks generated outside the soc */
-struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
+static struct
+samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0),
FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0),
};
/* fixed rate clocks generated inside the soc */
-struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
+static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
FRATE(none, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
FRATE(none, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
};
-struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
+static struct
+samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
};
/* list of mux clocks supported in all exynos4 soc's */
-struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
+static struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
MUX_F(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
CLK_SET_RATE_PARENT, 0),
MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
@@ -373,7 +375,7 @@ struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
};
/* list of mux clocks supported in exynos4210 soc */
-struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
+static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
MUX(none, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
MUX(none, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
MUX(none, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
@@ -424,7 +426,7 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
};
/* list of mux clocks supported in exynos4x12 soc */
-struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
+static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
MUX(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12,
SRC_CPU, 24, 1),
MUX(none, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
@@ -488,7 +490,7 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
};
/* list of divider clocks supported in all exynos4 soc's */
-struct samsung_div_clock exynos4_div_clks[] __initdata = {
+static struct samsung_div_clock exynos4_div_clks[] __initdata = {
DIV(none, "div_core", "mout_core", DIV_CPU0, 0, 3),
DIV(none, "div_core2", "div_core", DIV_CPU0, 28, 3),
DIV(none, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
@@ -551,7 +553,7 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = {
};
/* list of divider clocks supported in exynos4210 soc */
-struct samsung_div_clock exynos4210_div_clks[] __initdata = {
+static struct samsung_div_clock exynos4210_div_clks[] __initdata = {
DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
DIV(none, "div_g2d", "mout_g2d", DIV_IMAGE, 0, 4),
DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
@@ -562,7 +564,7 @@ struct samsung_div_clock exynos4210_div_clks[] __initdata = {
};
/* list of divider clocks supported in exynos4x12 soc */
-struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
+static struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
DIV(none, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),
DIV(none, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),
DIV(none, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
@@ -586,7 +588,7 @@ struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
};
/* list of gate clocks supported in all exynos4 soc's */
-struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
+static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
/*
* After all Exynos4 based platforms are migrated to use device tree,
* the device name and clock alias names specified below for some
@@ -778,7 +780,7 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
};
/* list of gate clocks supported in exynos4210 soc */
-struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
+static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
GATE(tvenc, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),
GATE(g2d, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),
GATE(rotator, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
@@ -812,7 +814,7 @@ struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
};
/* list of gate clocks supported in exynos4x12 soc */
-struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
+static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
GATE(audss, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
GATE(mdnie0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
GATE(rotator, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
--
1.7.9.5
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/3] clk: exynos5250: Staticize local symbols
2013-04-16 10:05 [PATCH 1/3] clk: exynos4: Staticize local symbols Sachin Kamat
@ 2013-04-16 10:05 ` Sachin Kamat
2013-06-05 12:16 ` Kukjin Kim
2013-04-16 10:05 ` [PATCH 3/3] clk: exynos5440: " Sachin Kamat
` (4 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Sachin Kamat @ 2013-04-16 10:05 UTC (permalink / raw)
To: linux-samsung-soc
Cc: kgene.kim, mturquette, thomas.abraham, sachin.kamat, patches
These symbols are used only in this file and hence should
be static.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
---
drivers/clk/samsung/clk-exynos5250.c | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 7290faa..9cdee2b 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -191,24 +191,27 @@ PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
"spdif_extclk" };
/* fixed rate clocks generated outside the soc */
-struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
+static struct
+samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0),
};
/* fixed rate clocks generated inside the soc */
-struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = {
+static struct
+samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = {
FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
FRATE(none, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000),
FRATE(none, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000),
FRATE(none, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000),
};
-struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {
+static struct
+samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {
FFACTOR(none, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
FFACTOR(none, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
};
-struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
+static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
MUX(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
MUX(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
@@ -254,7 +257,7 @@ struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
MUX(none, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4),
};
-struct samsung_div_clock exynos5250_div_clks[] __initdata = {
+static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
DIV(none, "aclk66_pre", "sclk_mpll_user", DIV_TOP1, 24, 3),
@@ -314,7 +317,7 @@ struct samsung_div_clock exynos5250_div_clks[] __initdata = {
DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
};
-struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
+static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
GATE(gscl0, "gscl0", "none", GATE_IP_GSCL, 0, 0, 0),
GATE(gscl1, "gscl1", "none", GATE_IP_GSCL, 1, 0, 0),
GATE(gscl2, "gscl2", "aclk266", GATE_IP_GSCL, 2, 0, 0),
@@ -471,7 +474,7 @@ static __initdata struct of_device_id ext_clk_match[] = {
};
/* register exynox5250 clocks */
-void __init exynos5250_clk_init(struct device_node *np)
+static void __init exynos5250_clk_init(struct device_node *np)
{
void __iomem *reg_base;
struct clk *apll, *mpll, *epll, *vpll, *bpll, *gpll, *cpll;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 3/3] clk: exynos5440: Staticize local symbols
2013-04-16 10:05 [PATCH 1/3] clk: exynos4: Staticize local symbols Sachin Kamat
2013-04-16 10:05 ` [PATCH 2/3] clk: exynos5250: " Sachin Kamat
@ 2013-04-16 10:05 ` Sachin Kamat
2013-06-05 12:18 ` Kukjin Kim
2013-04-29 10:33 ` [PATCH 1/3] clk: exynos4: " Sachin Kamat
` (3 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Sachin Kamat @ 2013-04-16 10:05 UTC (permalink / raw)
To: linux-samsung-soc
Cc: kgene.kim, mturquette, thomas.abraham, sachin.kamat, patches
These symbols are used only in this file and hence should be
static.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
---
drivers/clk/samsung/clk-exynos5440.c | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c
index a0a094c..ac6c95f 100644
--- a/drivers/clk/samsung/clk-exynos5440.c
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -42,12 +42,14 @@ PNAME(mout_armclk_p) = { "cplla", "cpllb" };
PNAME(mout_spi_p) = { "div125", "div200" };
/* fixed rate clocks generated outside the soc */
-struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = {
+static struct
+samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = {
FRATE(none, "xtal", NULL, CLK_IS_ROOT, 0),
};
/* fixed rate clocks */
-struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = {
+static struct
+samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = {
FRATE(none, "ppll", NULL, CLK_IS_ROOT, 1000000000),
FRATE(none, "usb_phy0", NULL, CLK_IS_ROOT, 60000000),
FRATE(none, "usb_phy1", NULL, CLK_IS_ROOT, 60000000),
@@ -56,26 +58,27 @@ struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = {
};
/* fixed factor clocks */
-struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = {
+static struct
+samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = {
FFACTOR(none, "div250", "ppll", 1, 4, 0),
FFACTOR(none, "div200", "ppll", 1, 5, 0),
FFACTOR(none, "div125", "div250", 1, 2, 0),
};
/* mux clocks */
-struct samsung_mux_clock exynos5440_mux_clks[] __initdata = {
+static struct samsung_mux_clock exynos5440_mux_clks[] __initdata = {
MUX(none, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
MUX_A(arm_clk, "arm_clk", mout_armclk_p,
CPU_CLK_STATUS, 0, 1, "armclk"),
};
/* divider clocks */
-struct samsung_div_clock exynos5440_div_clks[] __initdata = {
+static struct samsung_div_clock exynos5440_div_clks[] __initdata = {
DIV(spi_baud, "div_spi", "mout_spi", MISC_DOUT1, 3, 2),
};
/* gate clocks */
-struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
+static struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
GATE(pb0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0),
GATE(pr0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0),
GATE(pr1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0),
@@ -104,7 +107,7 @@ static __initdata struct of_device_id ext_clk_match[] = {
};
/* register exynos5440 clocks */
-void __init exynos5440_clk_init(struct device_node *np)
+static void __init exynos5440_clk_init(struct device_node *np)
{
void __iomem *reg_base;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 1/3] clk: exynos4: Staticize local symbols
2013-04-16 10:05 [PATCH 1/3] clk: exynos4: Staticize local symbols Sachin Kamat
2013-04-16 10:05 ` [PATCH 2/3] clk: exynos5250: " Sachin Kamat
2013-04-16 10:05 ` [PATCH 3/3] clk: exynos5440: " Sachin Kamat
@ 2013-04-29 10:33 ` Sachin Kamat
2013-05-27 12:02 ` Sachin Kamat
` (2 subsequent siblings)
5 siblings, 0 replies; 13+ messages in thread
From: Sachin Kamat @ 2013-04-29 10:33 UTC (permalink / raw)
To: linux-samsung-soc
Cc: kgene.kim, mturquette, thomas.abraham, sachin.kamat, patches
Ping Kukjin.
Can you please add this series to your tree?
On 16 April 2013 15:35, Sachin Kamat <sachin.kamat@linaro.org> wrote:
> These symbols are used only in this file and hence should be
> static.
>
> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
> ---
> drivers/clk/samsung/clk-exynos4.c | 26 ++++++++++++++------------
> 1 file changed, 14 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
> index 7104669..26f2a85 100644
> --- a/drivers/clk/samsung/clk-exynos4.c
> +++ b/drivers/clk/samsung/clk-exynos4.c
> @@ -339,24 +339,26 @@ PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
> PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
>
> /* fixed rate clocks generated outside the soc */
> -struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
> +static struct
> +samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
> FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0),
> FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0),
> };
>
> /* fixed rate clocks generated inside the soc */
> -struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
> +static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
> FRATE(none, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
> FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
> FRATE(none, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
> };
>
> -struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
> +static struct
> +samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
> FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
> };
>
> /* list of mux clocks supported in all exynos4 soc's */
> -struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
> +static struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
> MUX_F(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
> CLK_SET_RATE_PARENT, 0),
> MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
> @@ -373,7 +375,7 @@ struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
> };
>
> /* list of mux clocks supported in exynos4210 soc */
> -struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
> +static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
> MUX(none, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
> MUX(none, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
> MUX(none, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
> @@ -424,7 +426,7 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
> };
>
> /* list of mux clocks supported in exynos4x12 soc */
> -struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
> +static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
> MUX(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12,
> SRC_CPU, 24, 1),
> MUX(none, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
> @@ -488,7 +490,7 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
> };
>
> /* list of divider clocks supported in all exynos4 soc's */
> -struct samsung_div_clock exynos4_div_clks[] __initdata = {
> +static struct samsung_div_clock exynos4_div_clks[] __initdata = {
> DIV(none, "div_core", "mout_core", DIV_CPU0, 0, 3),
> DIV(none, "div_core2", "div_core", DIV_CPU0, 28, 3),
> DIV(none, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
> @@ -551,7 +553,7 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = {
> };
>
> /* list of divider clocks supported in exynos4210 soc */
> -struct samsung_div_clock exynos4210_div_clks[] __initdata = {
> +static struct samsung_div_clock exynos4210_div_clks[] __initdata = {
> DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
> DIV(none, "div_g2d", "mout_g2d", DIV_IMAGE, 0, 4),
> DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
> @@ -562,7 +564,7 @@ struct samsung_div_clock exynos4210_div_clks[] __initdata = {
> };
>
> /* list of divider clocks supported in exynos4x12 soc */
> -struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
> +static struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
> DIV(none, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),
> DIV(none, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),
> DIV(none, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
> @@ -586,7 +588,7 @@ struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
> };
>
> /* list of gate clocks supported in all exynos4 soc's */
> -struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
> +static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
> /*
> * After all Exynos4 based platforms are migrated to use device tree,
> * the device name and clock alias names specified below for some
> @@ -778,7 +780,7 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
> };
>
> /* list of gate clocks supported in exynos4210 soc */
> -struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
> +static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
> GATE(tvenc, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),
> GATE(g2d, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),
> GATE(rotator, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
> @@ -812,7 +814,7 @@ struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
> };
>
> /* list of gate clocks supported in exynos4x12 soc */
> -struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
> +static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
> GATE(audss, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
> GATE(mdnie0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
> GATE(rotator, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
> --
> 1.7.9.5
>
--
With warm regards,
Sachin
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/3] clk: exynos4: Staticize local symbols
2013-04-16 10:05 [PATCH 1/3] clk: exynos4: Staticize local symbols Sachin Kamat
` (2 preceding siblings ...)
2013-04-29 10:33 ` [PATCH 1/3] clk: exynos4: " Sachin Kamat
@ 2013-05-27 12:02 ` Sachin Kamat
2013-06-05 12:02 ` Sachin Kamat
2013-06-05 12:14 ` Kukjin Kim
5 siblings, 0 replies; 13+ messages in thread
From: Sachin Kamat @ 2013-05-27 12:02 UTC (permalink / raw)
To: Kukjin Kim, linux-samsung-soc
Hi Kukjin,
Can you please apply this series pending since a long time?
On 16 April 2013 15:35, Sachin Kamat <sachin.kamat@linaro.org> wrote:
> These symbols are used only in this file and hence should be
> static.
>
> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
> ---
> drivers/clk/samsung/clk-exynos4.c | 26 ++++++++++++++------------
> 1 file changed, 14 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
> index 7104669..26f2a85 100644
> --- a/drivers/clk/samsung/clk-exynos4.c
> +++ b/drivers/clk/samsung/clk-exynos4.c
> @@ -339,24 +339,26 @@ PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
> PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
>
> /* fixed rate clocks generated outside the soc */
> -struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
> +static struct
> +samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
> FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0),
> FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0),
> };
>
> /* fixed rate clocks generated inside the soc */
> -struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
> +static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
> FRATE(none, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
> FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
> FRATE(none, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
> };
>
> -struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
> +static struct
> +samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
> FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
> };
>
> /* list of mux clocks supported in all exynos4 soc's */
> -struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
> +static struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
> MUX_F(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
> CLK_SET_RATE_PARENT, 0),
> MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
> @@ -373,7 +375,7 @@ struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
> };
>
> /* list of mux clocks supported in exynos4210 soc */
> -struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
> +static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
> MUX(none, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
> MUX(none, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
> MUX(none, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
> @@ -424,7 +426,7 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
> };
>
> /* list of mux clocks supported in exynos4x12 soc */
> -struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
> +static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
> MUX(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12,
> SRC_CPU, 24, 1),
> MUX(none, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
> @@ -488,7 +490,7 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
> };
>
> /* list of divider clocks supported in all exynos4 soc's */
> -struct samsung_div_clock exynos4_div_clks[] __initdata = {
> +static struct samsung_div_clock exynos4_div_clks[] __initdata = {
> DIV(none, "div_core", "mout_core", DIV_CPU0, 0, 3),
> DIV(none, "div_core2", "div_core", DIV_CPU0, 28, 3),
> DIV(none, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
> @@ -551,7 +553,7 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = {
> };
>
> /* list of divider clocks supported in exynos4210 soc */
> -struct samsung_div_clock exynos4210_div_clks[] __initdata = {
> +static struct samsung_div_clock exynos4210_div_clks[] __initdata = {
> DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
> DIV(none, "div_g2d", "mout_g2d", DIV_IMAGE, 0, 4),
> DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
> @@ -562,7 +564,7 @@ struct samsung_div_clock exynos4210_div_clks[] __initdata = {
> };
>
> /* list of divider clocks supported in exynos4x12 soc */
> -struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
> +static struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
> DIV(none, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),
> DIV(none, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),
> DIV(none, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
> @@ -586,7 +588,7 @@ struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
> };
>
> /* list of gate clocks supported in all exynos4 soc's */
> -struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
> +static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
> /*
> * After all Exynos4 based platforms are migrated to use device tree,
> * the device name and clock alias names specified below for some
> @@ -778,7 +780,7 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
> };
>
> /* list of gate clocks supported in exynos4210 soc */
> -struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
> +static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
> GATE(tvenc, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),
> GATE(g2d, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),
> GATE(rotator, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
> @@ -812,7 +814,7 @@ struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
> };
>
> /* list of gate clocks supported in exynos4x12 soc */
> -struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
> +static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
> GATE(audss, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
> GATE(mdnie0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
> GATE(rotator, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
> --
> 1.7.9.5
>
--
With warm regards,
Sachin
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/3] clk: exynos4: Staticize local symbols
2013-04-16 10:05 [PATCH 1/3] clk: exynos4: Staticize local symbols Sachin Kamat
` (3 preceding siblings ...)
2013-05-27 12:02 ` Sachin Kamat
@ 2013-06-05 12:02 ` Sachin Kamat
2013-06-05 12:14 ` Kukjin Kim
5 siblings, 0 replies; 13+ messages in thread
From: Sachin Kamat @ 2013-06-05 12:02 UTC (permalink / raw)
To: linux-samsung-soc; +Cc: kgene.kim
Ping..
On 16 April 2013 15:35, Sachin Kamat <sachin.kamat@linaro.org> wrote:
> These symbols are used only in this file and hence should be
> static.
>
> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
> ---
> drivers/clk/samsung/clk-exynos4.c | 26 ++++++++++++++------------
> 1 file changed, 14 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
> index 7104669..26f2a85 100644
> --- a/drivers/clk/samsung/clk-exynos4.c
> +++ b/drivers/clk/samsung/clk-exynos4.c
> @@ -339,24 +339,26 @@ PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
> PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
>
> /* fixed rate clocks generated outside the soc */
> -struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
> +static struct
> +samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
> FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0),
> FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0),
> };
>
> /* fixed rate clocks generated inside the soc */
> -struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
> +static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
> FRATE(none, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
> FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
> FRATE(none, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
> };
>
> -struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
> +static struct
> +samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
> FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
> };
>
> /* list of mux clocks supported in all exynos4 soc's */
> -struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
> +static struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
> MUX_F(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
> CLK_SET_RATE_PARENT, 0),
> MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
> @@ -373,7 +375,7 @@ struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
> };
>
> /* list of mux clocks supported in exynos4210 soc */
> -struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
> +static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
> MUX(none, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
> MUX(none, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
> MUX(none, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
> @@ -424,7 +426,7 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
> };
>
> /* list of mux clocks supported in exynos4x12 soc */
> -struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
> +static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
> MUX(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12,
> SRC_CPU, 24, 1),
> MUX(none, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
> @@ -488,7 +490,7 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
> };
>
> /* list of divider clocks supported in all exynos4 soc's */
> -struct samsung_div_clock exynos4_div_clks[] __initdata = {
> +static struct samsung_div_clock exynos4_div_clks[] __initdata = {
> DIV(none, "div_core", "mout_core", DIV_CPU0, 0, 3),
> DIV(none, "div_core2", "div_core", DIV_CPU0, 28, 3),
> DIV(none, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
> @@ -551,7 +553,7 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = {
> };
>
> /* list of divider clocks supported in exynos4210 soc */
> -struct samsung_div_clock exynos4210_div_clks[] __initdata = {
> +static struct samsung_div_clock exynos4210_div_clks[] __initdata = {
> DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
> DIV(none, "div_g2d", "mout_g2d", DIV_IMAGE, 0, 4),
> DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
> @@ -562,7 +564,7 @@ struct samsung_div_clock exynos4210_div_clks[] __initdata = {
> };
>
> /* list of divider clocks supported in exynos4x12 soc */
> -struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
> +static struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
> DIV(none, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),
> DIV(none, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),
> DIV(none, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
> @@ -586,7 +588,7 @@ struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
> };
>
> /* list of gate clocks supported in all exynos4 soc's */
> -struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
> +static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
> /*
> * After all Exynos4 based platforms are migrated to use device tree,
> * the device name and clock alias names specified below for some
> @@ -778,7 +780,7 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
> };
>
> /* list of gate clocks supported in exynos4210 soc */
> -struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
> +static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
> GATE(tvenc, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),
> GATE(g2d, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),
> GATE(rotator, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
> @@ -812,7 +814,7 @@ struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
> };
>
> /* list of gate clocks supported in exynos4x12 soc */
> -struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
> +static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
> GATE(audss, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
> GATE(mdnie0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
> GATE(rotator, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
> --
> 1.7.9.5
>
--
With warm regards,
Sachin
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 1/3] clk: exynos4: Staticize local symbols
2013-04-16 10:05 [PATCH 1/3] clk: exynos4: Staticize local symbols Sachin Kamat
` (4 preceding siblings ...)
2013-06-05 12:02 ` Sachin Kamat
@ 2013-06-05 12:14 ` Kukjin Kim
2013-06-11 4:16 ` Sachin Kamat
5 siblings, 1 reply; 13+ messages in thread
From: Kukjin Kim @ 2013-06-05 12:14 UTC (permalink / raw)
To: 'Sachin Kamat', linux-samsung-soc
Cc: mturquette, thomas.abraham, patches
Sachin Kamat wrote:
>
> These symbols are used only in this file and hence should be
> static.
>
> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
> ---
> drivers/clk/samsung/clk-exynos4.c | 26 ++++++++++++++------------
> 1 file changed, 14 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-
> exynos4.c
> index 7104669..26f2a85 100644
> --- a/drivers/clk/samsung/clk-exynos4.c
> +++ b/drivers/clk/samsung/clk-exynos4.c
> @@ -339,24 +339,26 @@ PNAME(mout_user_aclk200_p4x12) = {"fin_pll",
> "div_aclk200", };
> PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
>
> /* fixed rate clocks generated outside the soc */
> -struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata
> = {
> +static struct
> +samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
Any reason to use double lines?
> FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0),
> FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0),
> };
[...]
> -struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata =
> {
> +static struct
> +samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
Same as above.
> FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
> };
>
[...]
Others look good to me,
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Mike, please pick this into the clk tree if you're ok.
Thanks.
- Kukjin
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 2/3] clk: exynos5250: Staticize local symbols
2013-04-16 10:05 ` [PATCH 2/3] clk: exynos5250: " Sachin Kamat
@ 2013-06-05 12:16 ` Kukjin Kim
0 siblings, 0 replies; 13+ messages in thread
From: Kukjin Kim @ 2013-06-05 12:16 UTC (permalink / raw)
To: 'Sachin Kamat', linux-samsung-soc
Cc: mturquette, thomas.abraham, patches
Sachin Kamat wrote:
>
> These symbols are used only in this file and hence should
> be static.
>
> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
> ---
> drivers/clk/samsung/clk-exynos5250.c | 17 ++++++++++-------
> 1 file changed, 10 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5250.c
> b/drivers/clk/samsung/clk-exynos5250.c
> index 7290faa..9cdee2b 100644
> --- a/drivers/clk/samsung/clk-exynos5250.c
> +++ b/drivers/clk/samsung/clk-exynos5250.c
> @@ -191,24 +191,27 @@ PNAME(mout_spdif_p) = { "sclk_audio0",
> "sclk_audio1", "sclk_audio2",
> "spdif_extclk" };
>
> /* fixed rate clocks generated outside the soc */
> -struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[]
> __initdata = {
> +static struct
> +samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
> FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0),
> };
>
> /* fixed rate clocks generated inside the soc */
> -struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata =
> {
> +static struct
> +samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = {
> FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
> FRATE(none, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000),
> FRATE(none, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000),
> FRATE(none, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000),
> };
>
> -struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[]
> __initdata = {
> +static struct
> +samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {
> FFACTOR(none, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
> FFACTOR(none, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
> };
>
> -struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
> +static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
> MUX(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
> MUX(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
> MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
> @@ -254,7 +257,7 @@ struct samsung_mux_clock exynos5250_mux_clks[]
> __initdata = {
> MUX(none, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4),
> };
>
> -struct samsung_div_clock exynos5250_div_clks[] __initdata = {
> +static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
> DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
> DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
> DIV(none, "aclk66_pre", "sclk_mpll_user", DIV_TOP1, 24, 3),
> @@ -314,7 +317,7 @@ struct samsung_div_clock exynos5250_div_clks[]
> __initdata = {
> DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
> };
>
> -struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
> +static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
> GATE(gscl0, "gscl0", "none", GATE_IP_GSCL, 0, 0, 0),
> GATE(gscl1, "gscl1", "none", GATE_IP_GSCL, 1, 0, 0),
> GATE(gscl2, "gscl2", "aclk266", GATE_IP_GSCL, 2, 0, 0),
> @@ -471,7 +474,7 @@ static __initdata struct of_device_id ext_clk_match[]
> = {
> };
>
> /* register exynox5250 clocks */
> -void __init exynos5250_clk_init(struct device_node *np)
> +static void __init exynos5250_clk_init(struct device_node *np)
> {
> void __iomem *reg_base;
> struct clk *apll, *mpll, *epll, *vpll, *bpll, *gpll, *cpll;
> --
> 1.7.9.5
Same comments with 1/3.
Others look good to me,
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Thanks.
- Kukjin
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 3/3] clk: exynos5440: Staticize local symbols
2013-04-16 10:05 ` [PATCH 3/3] clk: exynos5440: " Sachin Kamat
@ 2013-06-05 12:18 ` Kukjin Kim
0 siblings, 0 replies; 13+ messages in thread
From: Kukjin Kim @ 2013-06-05 12:18 UTC (permalink / raw)
To: 'Sachin Kamat', linux-samsung-soc
Cc: mturquette, thomas.abraham, patches
Sachin Kamat wrote:
>
> These symbols are used only in this file and hence should be
> static.
>
> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
> ---
> drivers/clk/samsung/clk-exynos5440.c | 17 ++++++++++-------
> 1 file changed, 10 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5440.c
> b/drivers/clk/samsung/clk-exynos5440.c
> index a0a094c..ac6c95f 100644
> --- a/drivers/clk/samsung/clk-exynos5440.c
> +++ b/drivers/clk/samsung/clk-exynos5440.c
> @@ -42,12 +42,14 @@ PNAME(mout_armclk_p) = { "cplla", "cpllb" };
> PNAME(mout_spi_p) = { "div125", "div200" };
>
> /* fixed rate clocks generated outside the soc */
> -struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[]
> __initdata = {
> +static struct
> +samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = {
> FRATE(none, "xtal", NULL, CLK_IS_ROOT, 0),
> };
>
> /* fixed rate clocks */
> -struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata =
> {
> +static struct
> +samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = {
> FRATE(none, "ppll", NULL, CLK_IS_ROOT, 1000000000),
> FRATE(none, "usb_phy0", NULL, CLK_IS_ROOT, 60000000),
> FRATE(none, "usb_phy1", NULL, CLK_IS_ROOT, 60000000),
> @@ -56,26 +58,27 @@ struct samsung_fixed_rate_clock
> exynos5440_fixed_rate_clks[] __initdata = {
> };
>
> /* fixed factor clocks */
> -struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[]
> __initdata = {
> +static struct
> +samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = {
> FFACTOR(none, "div250", "ppll", 1, 4, 0),
> FFACTOR(none, "div200", "ppll", 1, 5, 0),
> FFACTOR(none, "div125", "div250", 1, 2, 0),
> };
>
> /* mux clocks */
> -struct samsung_mux_clock exynos5440_mux_clks[] __initdata = {
> +static struct samsung_mux_clock exynos5440_mux_clks[] __initdata = {
> MUX(none, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
> MUX_A(arm_clk, "arm_clk", mout_armclk_p,
> CPU_CLK_STATUS, 0, 1, "armclk"),
> };
>
> /* divider clocks */
> -struct samsung_div_clock exynos5440_div_clks[] __initdata = {
> +static struct samsung_div_clock exynos5440_div_clks[] __initdata = {
> DIV(spi_baud, "div_spi", "mout_spi", MISC_DOUT1, 3, 2),
> };
>
> /* gate clocks */
> -struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
> +static struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
> GATE(pb0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0),
> GATE(pr0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0),
> GATE(pr1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0),
> @@ -104,7 +107,7 @@ static __initdata struct of_device_id ext_clk_match[]
> = {
> };
>
> /* register exynos5440 clocks */
> -void __init exynos5440_clk_init(struct device_node *np)
> +static void __init exynos5440_clk_init(struct device_node *np)
> {
> void __iomem *reg_base;
>
> --
> 1.7.9.5
Same...
Other look good to me,
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Thanks.
- Kukjin
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/3] clk: exynos4: Staticize local symbols
2013-06-05 12:14 ` Kukjin Kim
@ 2013-06-11 4:16 ` Sachin Kamat
2013-06-13 15:36 ` Sachin Kamat
0 siblings, 1 reply; 13+ messages in thread
From: Sachin Kamat @ 2013-06-11 4:16 UTC (permalink / raw)
To: Kukjin Kim, Mike Turquette; +Cc: linux-samsung-soc
On 5 June 2013 17:44, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Sachin Kamat wrote:
>>
>> These symbols are used only in this file and hence should be
>> static.
>>
>> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
>> ---
>> drivers/clk/samsung/clk-exynos4.c | 26 ++++++++++++++------------
>> 1 file changed, 14 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-
>> exynos4.c
>> index 7104669..26f2a85 100644
>> --- a/drivers/clk/samsung/clk-exynos4.c
>> +++ b/drivers/clk/samsung/clk-exynos4.c
>> @@ -339,24 +339,26 @@ PNAME(mout_user_aclk200_p4x12) = {"fin_pll",
>> "div_aclk200", };
>> PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
>>
>> /* fixed rate clocks generated outside the soc */
>> -struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata
>> = {
>> +static struct
>> +samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
>
> Any reason to use double lines?
This is one of the ways to avoid exceeding 80 column limit.
>
>> FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0),
>> FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0),
>> };
>
> [...]
>
>> -struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata =
>> {
>> +static struct
>> +samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
>
> Same as above.
>
>> FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
>> };
>>
> [...]
>
> Others look good to me,
> Acked-by: Kukjin Kim <kgene.kim@samsung.com>
>
> Mike, please pick this into the clk tree if you're ok.
>
Mike,
If you are taking this through your tree, please also take the below
patch [1] as it is dependent on this series.
[1] https://patchwork.kernel.org/patch/2469891/
--
With warm regards,
Sachin
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/3] clk: exynos4: Staticize local symbols
2013-06-11 4:16 ` Sachin Kamat
@ 2013-06-13 15:36 ` Sachin Kamat
2013-06-17 3:14 ` Sachin Kamat
0 siblings, 1 reply; 13+ messages in thread
From: Sachin Kamat @ 2013-06-13 15:36 UTC (permalink / raw)
To: Kukjin Kim, Mike Turquette; +Cc: linux-samsung-soc
On 11 June 2013 09:46, Sachin Kamat <sachin.kamat@linaro.org> wrote:
> On 5 June 2013 17:44, Kukjin Kim <kgene.kim@samsung.com> wrote:
>> Sachin Kamat wrote:
>>>
>>> These symbols are used only in this file and hence should be
>>> static.
>>>
>>> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
>>> ---
>>> drivers/clk/samsung/clk-exynos4.c | 26 ++++++++++++++------------
>>> 1 file changed, 14 insertions(+), 12 deletions(-)
>>>
>>> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-
>>> exynos4.c
>>> index 7104669..26f2a85 100644
>>> --- a/drivers/clk/samsung/clk-exynos4.c
>>> +++ b/drivers/clk/samsung/clk-exynos4.c
>>> @@ -339,24 +339,26 @@ PNAME(mout_user_aclk200_p4x12) = {"fin_pll",
>>> "div_aclk200", };
>>> PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
>>>
>>> /* fixed rate clocks generated outside the soc */
>>> -struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata
>>> = {
>>> +static struct
>>> +samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
>>
>> Any reason to use double lines?
>
> This is one of the ways to avoid exceeding 80 column limit.
>
>>
>>> FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0),
>>> FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0),
>>> };
>>
>> [...]
>>
>>> -struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata =
>>> {
>>> +static struct
>>> +samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
>>
>> Same as above.
>>
>>> FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
>>> };
>>>
>> [...]
>>
>> Others look good to me,
>> Acked-by: Kukjin Kim <kgene.kim@samsung.com>
>>
>> Mike, please pick this into the clk tree if you're ok.
>>
>
> Mike,
> If you are taking this through your tree, please also take the below
> patch [1] as it is dependent on this series.
> [1] https://patchwork.kernel.org/patch/2469891/
Ping Mike..
--
With warm regards,
Sachin
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/3] clk: exynos4: Staticize local symbols
2013-06-13 15:36 ` Sachin Kamat
@ 2013-06-17 3:14 ` Sachin Kamat
2013-06-19 14:24 ` Kukjin Kim
0 siblings, 1 reply; 13+ messages in thread
From: Sachin Kamat @ 2013-06-17 3:14 UTC (permalink / raw)
To: Kukjin Kim, Mike Turquette; +Cc: linux-samsung-soc
On 13 June 2013 21:06, Sachin Kamat <sachin.kamat@linaro.org> wrote:
> On 11 June 2013 09:46, Sachin Kamat <sachin.kamat@linaro.org> wrote:
>> On 5 June 2013 17:44, Kukjin Kim <kgene.kim@samsung.com> wrote:
>>> Sachin Kamat wrote:
>>>>
>>>> These symbols are used only in this file and hence should be
>>>> static.
>>>>
>>>> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
>>>> ---
>>>> drivers/clk/samsung/clk-exynos4.c | 26 ++++++++++++++------------
>>>> 1 file changed, 14 insertions(+), 12 deletions(-)
>>>>
>>>> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-
>>>> exynos4.c
>>>> index 7104669..26f2a85 100644
>>>> --- a/drivers/clk/samsung/clk-exynos4.c
>>>> +++ b/drivers/clk/samsung/clk-exynos4.c
>>>> @@ -339,24 +339,26 @@ PNAME(mout_user_aclk200_p4x12) = {"fin_pll",
>>>> "div_aclk200", };
>>>> PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
>>>>
>>>> /* fixed rate clocks generated outside the soc */
>>>> -struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata
>>>> = {
>>>> +static struct
>>>> +samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
>>>
>>> Any reason to use double lines?
>>
>> This is one of the ways to avoid exceeding 80 column limit.
>>
>>>
>>>> FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0),
>>>> FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0),
>>>> };
>>>
>>> [...]
>>>
>>>> -struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata =
>>>> {
>>>> +static struct
>>>> +samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
>>>
>>> Same as above.
>>>
>>>> FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
>>>> };
>>>>
>>> [...]
>>>
>>> Others look good to me,
>>> Acked-by: Kukjin Kim <kgene.kim@samsung.com>
>>>
>>> Mike, please pick this into the clk tree if you're ok.
>>>
>>
>> Mike,
>> If you are taking this through your tree, please also take the below
>> patch [1] as it is dependent on this series.
>> [1] https://patchwork.kernel.org/patch/2469891/
>
>
> Ping Mike..
Kukjin,
Haven't heard back from Mike regarding this. Can you please take this
through your tree?
--
With warm regards,
Sachin
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/3] clk: exynos4: Staticize local symbols
2013-06-17 3:14 ` Sachin Kamat
@ 2013-06-19 14:24 ` Kukjin Kim
0 siblings, 0 replies; 13+ messages in thread
From: Kukjin Kim @ 2013-06-19 14:24 UTC (permalink / raw)
To: Sachin Kamat; +Cc: Kukjin Kim, Mike Turquette, linux-samsung-soc
On 06/17/13 12:14, Sachin Kamat wrote:
> On 13 June 2013 21:06, Sachin Kamat<sachin.kamat@linaro.org> wrote:
>> On 11 June 2013 09:46, Sachin Kamat<sachin.kamat@linaro.org> wrote:
>>> On 5 June 2013 17:44, Kukjin Kim<kgene.kim@samsung.com> wrote:
>>>> Sachin Kamat wrote:
>>>>>
>>>>> These symbols are used only in this file and hence should be
>>>>> static.
>>>>>
>>>>> Signed-off-by: Sachin Kamat<sachin.kamat@linaro.org>
>>>>> ---
>>>>> drivers/clk/samsung/clk-exynos4.c | 26 ++++++++++++++------------
>>>>> 1 file changed, 14 insertions(+), 12 deletions(-)
>>>>>
>>>>> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-
>>>>> exynos4.c
>>>>> index 7104669..26f2a85 100644
>>>>> --- a/drivers/clk/samsung/clk-exynos4.c
>>>>> +++ b/drivers/clk/samsung/clk-exynos4.c
>>>>> @@ -339,24 +339,26 @@ PNAME(mout_user_aclk200_p4x12) = {"fin_pll",
>>>>> "div_aclk200", };
>>>>> PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
>>>>>
>>>>> /* fixed rate clocks generated outside the soc */
>>>>> -struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata
>>>>> = {
>>>>> +static struct
>>>>> +samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
>>>>
>>>> Any reason to use double lines?
>>>
>>> This is one of the ways to avoid exceeding 80 column limit.
>>>
>>>>
>>>>> FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0),
>>>>> FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0),
>>>>> };
>>>>
>>>> [...]
>>>>
>>>>> -struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata =
>>>>> {
>>>>> +static struct
>>>>> +samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
>>>>
>>>> Same as above.
>>>>
>>>>> FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
>>>>> };
>>>>>
>>>> [...]
>>>>
>>>> Others look good to me,
>>>> Acked-by: Kukjin Kim<kgene.kim@samsung.com>
>>>>
>>>> Mike, please pick this into the clk tree if you're ok.
>>>>
>>>
>>> Mike,
>>> If you are taking this through your tree, please also take the below
>>> patch [1] as it is dependent on this series.
>>> [1] https://patchwork.kernel.org/patch/2469891/
>>
>>
>> Ping Mike..
>
>
> Kukjin,
>
> Haven't heard back from Mike regarding this. Can you please take this
> through your tree?
>
OK, I will. BTW, Sachin, let me modify the line added static for
regarding 80 columns...I think, just one like is better...
Anyway, Mike, if you have any objection, please kindly let me know
before pulling into arm-soc tree.
Thanks,
- Kukjin
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2013-06-19 14:24 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-04-16 10:05 [PATCH 1/3] clk: exynos4: Staticize local symbols Sachin Kamat
2013-04-16 10:05 ` [PATCH 2/3] clk: exynos5250: " Sachin Kamat
2013-06-05 12:16 ` Kukjin Kim
2013-04-16 10:05 ` [PATCH 3/3] clk: exynos5440: " Sachin Kamat
2013-06-05 12:18 ` Kukjin Kim
2013-04-29 10:33 ` [PATCH 1/3] clk: exynos4: " Sachin Kamat
2013-05-27 12:02 ` Sachin Kamat
2013-06-05 12:02 ` Sachin Kamat
2013-06-05 12:14 ` Kukjin Kim
2013-06-11 4:16 ` Sachin Kamat
2013-06-13 15:36 ` Sachin Kamat
2013-06-17 3:14 ` Sachin Kamat
2013-06-19 14:24 ` Kukjin Kim
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