[PATCH] MIPS: Add missing hazard barrier in TLB load handler.

[PATCH] MIPS: Add missing hazard barrier in TLB load handler.

[Steven J. Hill]

From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>

MIPS R2 documents state that an execution hazard barrier is needed
after a TLBR before reading EntryLo.

Change-Id: Idef3b6abbb63a1bbd5e153c6110a979fa7bd5896
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Acked-by: Steven J. Hill <Steven.Hill@imgtec.com>
---
 arch/mips/mm/tlbex.c |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index d9969d2..5ef426c 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -1922,6 +1922,11 @@ static void build_r4000_tlb_load_handler(void)
 		uasm_i_nop(&p);
 
 		uasm_i_tlbr(&p);
+#if !defined(CONFIG_CPU_CAVIUM_OCTEON)
+		/* hazard barrier after TLBR but before read EntryLo */
+		if (cpu_has_mips_r2)
+			uasm_i_ehb(&p);
+#endif
 		/* Examine  entrylo 0 or 1 based on ptr. */
 		if (use_bbit_insns()) {
 			uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
@@ -1976,6 +1981,11 @@ static void build_r4000_tlb_load_handler(void)
 		uasm_i_nop(&p);
 
 		uasm_i_tlbr(&p);
+#if !defined(CONFIG_CPU_CAVIUM_OCTEON)
+		/* hazard barrier after TLBR but before read EntryLo */
+		if (cpu_has_mips_r2)
+			uasm_i_ehb(&p);
+#endif
 		/* Examine  entrylo 0 or 1 based on ptr. */
 		if (use_bbit_insns()) {
 			uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
-- 
1.7.2.5

Re: [PATCH] MIPS: Add missing hazard barrier in TLB load handler.

[Ralf Baechle]

On Thu, Jun 20, 2013 at 12:57:54AM -0500, Steven J. Hill wrote:

> MIPS R2 documents state that an execution hazard barrier is needed
> after a TLBR before reading EntryLo.
> 
> Change-Id: Idef3b6abbb63a1bbd5e153c6110a979fa7bd5896
> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
> Acked-by: Steven J. Hill <Steven.Hill@imgtec.com>
> ---
>  arch/mips/mm/tlbex.c |   10 ++++++++++
>  1 files changed, 10 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
> index d9969d2..5ef426c 100644
> --- a/arch/mips/mm/tlbex.c
> +++ b/arch/mips/mm/tlbex.c
> @@ -1922,6 +1922,11 @@ static void build_r4000_tlb_load_handler(void)
>  		uasm_i_nop(&p);
>  
>  		uasm_i_tlbr(&p);
> +#if !defined(CONFIG_CPU_CAVIUM_OCTEON)
> +		/* hazard barrier after TLBR but before read EntryLo */
> +		if (cpu_has_mips_r2)
> +			uasm_i_ehb(&p);
> +#endif
>  		/* Examine  entrylo 0 or 1 based on ptr. */
>  		if (use_bbit_insns()) {
>  			uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
> @@ -1976,6 +1981,11 @@ static void build_r4000_tlb_load_handler(void)
>  		uasm_i_nop(&p);
>  
>  		uasm_i_tlbr(&p);
> +#if !defined(CONFIG_CPU_CAVIUM_OCTEON)
> +		/* hazard barrier after TLBR but before read EntryLo */
> +		if (cpu_has_mips_r2)
> +			uasm_i_ehb(&p);
> +#endif
>  		/* Examine  entrylo 0 or 1 based on ptr. */
>  		if (use_bbit_insns()) {
>  			uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);

And guess which lines the sulphur smell in this patch is coming from.

  Ralf

Re: [PATCH] MIPS: Add missing hazard barrier in TLB load handler.

[Sergei Shtylyov]

Hello.

On 20-06-2013 9:57, Steven J. Hill wrote:

> From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>

> MIPS R2 documents state that an execution hazard barrier is needed
> after a TLBR before reading EntryLo.

> Change-Id: Idef3b6abbb63a1bbd5e153c6110a979fa7bd5896

    Sigh...

> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
> Acked-by: Steven J. Hill <Steven.Hill@imgtec.com>
> ---
>   arch/mips/mm/tlbex.c |   10 ++++++++++
>   1 files changed, 10 insertions(+), 0 deletions(-)

> diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
> index d9969d2..5ef426c 100644
> --- a/arch/mips/mm/tlbex.c
> +++ b/arch/mips/mm/tlbex.c
> @@ -1922,6 +1922,11 @@ static void build_r4000_tlb_load_handler(void)
>   		uasm_i_nop(&p);
>
>   		uasm_i_tlbr(&p);
> +#if !defined(CONFIG_CPU_CAVIUM_OCTEON)

     Suggesting to use if (!IS_ENABLED(CONFIG_CPU_CAVIUM_OCTEON)) to 
avoid #ifdef...

> +		/* hazard barrier after TLBR but before read EntryLo */
> +		if (cpu_has_mips_r2)
> +			uasm_i_ehb(&p);
> +#endif
>   		/* Examine  entrylo 0 or 1 based on ptr. */
>   		if (use_bbit_insns()) {
>   			uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
> @@ -1976,6 +1981,11 @@ static void build_r4000_tlb_load_handler(void)
>   		uasm_i_nop(&p);
>
>   		uasm_i_tlbr(&p);
> +#if !defined(CONFIG_CPU_CAVIUM_OCTEON)

    Same here.

> +		/* hazard barrier after TLBR but before read EntryLo */
> +		if (cpu_has_mips_r2)
> +			uasm_i_ehb(&p);
> +#endif

WBR, Sergei

Re: [PATCH] MIPS: Add missing hazard barrier in TLB load handler.

[Ralf Baechle]

On Thu, Jun 20, 2013 at 03:13:57PM +0400, Sergei Shtylyov wrote:

> >+#if !defined(CONFIG_CPU_CAVIUM_OCTEON)
> 
>     Suggesting to use if (!IS_ENABLED(CONFIG_CPU_CAVIUM_OCTEON)) to
> avoid #ifdef...

An ifdef in disguise.  IS_ENABLED() gives better coverage in build tests
but that's about it, it allows more readable formatting.  But that's
about it's advantages.

Never use CONFIG_CPU_* to conditionally execute code only on certain
CPU types.  It's not consistently used like this everywhere but it's meant
to select optimization for a particular processor type.

For example on the Malta, a system that's notorious for supporting
particularly man processor types CONFIG_CPU_R4X00 might be set but the
actual core core be a lowly R4Kc or the latest 666Kfc MIPS64 R6 core from
hell.

CONFIG_SYS_HAS_CPU_* only expresses that a system _might_ be equipped
with a particular processor, that is support for this core should be
compiled in.  An arbitrary number of CONFIG_SYS_HAS_CPU_* may be enabled.

If you really need to test for a processor at runtime, use current_cpu_type().
Typically that's done in a switch and there are plenty of example scattered
around arch/mips/mm/.

It's possible to replace the current current_cpu_type() with a platform-
specific version that looks (example for Cavium Octeon) like:

static inline int __pure current_cpu_type(void)
{
	const int cpu_type = current_cpu_data.cputype;

	switch (cpu_type) {
	case CPU_CAVIUM_OCTEON:
	case CPU_CAVIUM_OCTEON_PLUS:
	case CPU_CAVIUM_OCTEON2:
		break;

	default:
		unreachable();
	}

	return cpu_type;
}

Modern GCC will then notice that current_cpu_type() may only ever return
the values CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS and CPU_CAVIUM_OCTEON2
and will discard all the non-Octeon code from a switch construct like this:

	switch (current_cpu_type()) {
	case CPU_R2000:
	case CPU_R3000:
		...
		break;

	case CPU_CAVIUM_OCTEON:
	case CPU_CAVIUM_OCTEON_PLUS:
	case CPU_CAVIUM_OCTEON2:
		break;
	}

Result: sane, clean code.

  Ralf

MIPS: Fix TLBR-use hazards for R2 cores in the TLB reload handlers

MIPS R2 documents state that an execution hazard barrier is needed
after a TLBR before reading EntryLo.

Original patch by Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
 arch/mips/mm/tlbex.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index bfff8fe..34c882c 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -1932,6 +1932,19 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
 		uasm_i_nop(&p);
 
 		uasm_i_tlbr(&p);
+
+		switch (current_cpu_type()) {
+		default:
+			if (cpu_has_mips_r2) {
+				uasm_i_ehb(&p);
+
+		case CPU_CAVIUM_OCTEON:
+		case CPU_CAVIUM_OCTEON_PLUS:
+		case CPU_CAVIUM_OCTEON2:
+				break;
+			}
+		}
+
 		/* Examine  entrylo 0 or 1 based on ptr. */
 		if (use_bbit_insns()) {
 			uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
@@ -1986,6 +1999,19 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
 		uasm_i_nop(&p);
 
 		uasm_i_tlbr(&p);
+
+		switch (current_cpu_type()) {
+		default:
+			if (cpu_has_mips_r2) {
+				uasm_i_ehb(&p);
+
+		case CPU_CAVIUM_OCTEON:
+		case CPU_CAVIUM_OCTEON_PLUS:
+		case CPU_CAVIUM_OCTEON2:
+				break;
+			}
+		}
+
 		/* Examine  entrylo 0 or 1 based on ptr. */
 		if (use_bbit_insns()) {
 			uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);