From: mkl@pengutronix.de (Marc Kleine-Budde)
To: linux-arm-kernel@lists.infradead.org
Subject: BUG: commit "ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on pre-ARMv6 CPUs" breaks armv5 with CONFIG_PREEMPT
Date: Thu, 20 Jun 2013 14:48:22 +0200 [thread overview]
Message-ID: <51C2FA16.2080807@pengutronix.de> (raw)
In-Reply-To: <51C2EBCD.4070206@pengutronix.de>
On 06/20/2013 01:47 PM, Marc Kleine-Budde wrote:
> On 06/20/2013 01:39 PM, Marc Kleine-Budde wrote:
>> On 06/20/2013 01:35 PM, Marc Kleine-Budde wrote:
>>> On 06/20/2013 01:12 PM, Catalin Marinas wrote:
>>>> On Thu, Jun 20, 2013 at 11:28:56AM +0100, Catalin Marinas wrote:
>>>>> We may need to place the preempt disable/enable at a higher level in the
>>>>> scheduler. My theory is that we have a context switch from prev to next.
>>>>> We get preempted just before finish_arch_post_lock_switch(), so the MMU
>>>>> hasn't been switched yet. The new switch during preemption happens to a
>>>>> thread with the same next mm, so the scheduler no longer switch_mm() and
>>>>> the TIF_SWITCH_MM isn't set for the new thread.
>>>>>
>>>>> I'll come back with another patch shortly.
>>>>
>>>> Here's another attempt (as before, only compile-tested):
>>>
>>> booting kernel from /image
>>> zImage: concatenated oftree detected
>>> booting Linux kernel with devicetree
>>>
>>> ...dead...
>>>
>>> Does every process have a "mm"? Even Kernel threads?
>
> I've added a check for "mm". Boots now and my test runs stable for 3
> minutes now.
>
> I'm not sure if we have to check for "mm" in
> check_and_switch_context(), too.
>
> Thanks,
> Marc
> ---
>
> From 306d84d5f0645a86e86d539be0546c4ac758d3d4 Mon Sep 17 00:00:00 2001
> From: Catalin Marinas <catalin.marinas@arm.com>
> Date: Thu, 20 Jun 2013 12:12:55 +0100
> Subject: [PATCH] arm: Fix deferred mm switch on VIVT processors
>
> As of commit b9d4d42ad9 (ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on
> pre-ARMv6 CPUs), the mm switching on VIVT processors is done in the
> finish_arch_post_lock_switch() function to avoid whole cache flushing
> with interrupts disabled. The need for deferred mm switch is stored as a
> thread flag (TIF_SWITCH_MM). However, with preemption enabled, we can
> have another thread switch before finish_arch_post_lock_switch(). If the
> new thread has the same mm as the previous 'next' thread, the scheduler
> will not call switch_mm() and the TIF_SWITCH_MM flag won't be set for
> the new thread.
>
> This patch moves the switch pending flag to the mm_context_t structure
> since this is specific to the mm rather than thread.
>
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> Reported-by: Marc Kleine-Budde <mkl@pengutronix.de>
> [mkl: add check for mm]
> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
The test program works for 1 hour without problems. I'm going to push
the patch to our customer, if it fixes the problem there, I'll add my
Tested-by.
regards,
Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Industrial Linux Solutions | Phone: +49-231-2826-924 |
Vertretung West/Dortmund | Fax: +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |
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next prev parent reply other threads:[~2013-06-20 12:48 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-20 8:43 BUG: commit "ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on pre-ARMv6 CPUs" breaks armv5 with CONFIG_PREEMPT Marc Kleine-Budde
2013-06-20 9:25 ` Will Deacon
2013-06-20 9:51 ` Marc Kleine-Budde
2013-06-20 9:57 ` Catalin Marinas
2013-06-20 10:08 ` Marc Kleine-Budde
2013-06-20 10:14 ` Marc Kleine-Budde
2013-06-20 10:28 ` Catalin Marinas
2013-06-20 11:12 ` Catalin Marinas
2013-06-20 11:35 ` Marc Kleine-Budde
2013-06-20 11:39 ` Marc Kleine-Budde
2013-06-20 11:47 ` Marc Kleine-Budde
2013-06-20 12:48 ` Marc Kleine-Budde [this message]
2013-06-20 13:01 ` Catalin Marinas
2013-06-20 13:05 ` Marc Kleine-Budde
2013-06-21 10:28 ` Marc Kleine-Budde
2013-06-21 13:52 ` Catalin Marinas
2013-07-17 8:41 ` Marc Kleine-Budde
2013-07-17 8:51 ` Russell King - ARM Linux
2013-07-17 11:48 ` Marc Kleine-Budde
2013-07-17 19:41 ` Catalin Marinas
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