[Qemu-devel] [PATCH 3/5] tcg-arm: Make use of conditional availability of opcodes for divide

[Qemu-devel] [PATCH 3/5] tcg-arm: Make use of conditional availability of opcodes for divide

[Richard Henderson]

We can now detect and use divide instructions at runtime, rather than
having to restrict their availability to compile-time.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/arm/tcg-target.c | 16 ++++++++++++++--
 tcg/arm/tcg-target.h | 14 ++++++++------
 2 files changed, 22 insertions(+), 8 deletions(-)

diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 3d43412..f6bc165 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -67,6 +67,13 @@ static const int use_armv7_instructions = 0;
 #endif
 #undef USE_ARMV7_INSTRUCTIONS
 
+#ifndef use_idiv_instructions
+bool use_idiv_instructions;
+#endif
+#ifdef CONFIG_GETAUXVAL
+# include <sys/auxv.h>
+#endif
+
 #ifndef NDEBUG
 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
     "%r0",
@@ -2041,18 +2048,23 @@ static const TCGTargetOpDef arm_op_defs[] = {
 
     { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
 
-#if TCG_TARGET_HAS_div_i32
     { INDEX_op_div_i32, { "r", "r", "r" } },
     { INDEX_op_rem_i32, { "r", "r", "r" } },
     { INDEX_op_divu_i32, { "r", "r", "r" } },
     { INDEX_op_remu_i32, { "r", "r", "r" } },
-#endif
 
     { -1 },
 };
 
 static void tcg_target_init(TCGContext *s)
 {
+#if defined(CONFIG_GETAUXVAL) && !defined(use_idiv_instructions)
+    {
+        unsigned long hwcap = getauxval(AT_HWCAP);
+        use_idiv_instructions = hwcap & (HWCAP_ARM_IDIVA | HWCAP_ARM_IDIVT);
+    }
+#endif
+
 #if !defined(CONFIG_USER_ONLY)
     /* fail safe */
     if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 3be41cc..4e1a88f 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -49,6 +49,13 @@ typedef enum {
 
 #define TCG_TARGET_NB_REGS 16
 
+#ifdef __ARM_ARCH_EXT_IDIV__
+#define use_idiv_instructions  1
+#else
+extern bool use_idiv_instructions;
+#endif
+
+
 /* used for function call generation */
 #define TCG_REG_CALL_STACK		TCG_REG_R13
 #define TCG_TARGET_STACK_ALIGN		8
@@ -73,12 +80,7 @@ typedef enum {
 #define TCG_TARGET_HAS_deposit_i32      1
 #define TCG_TARGET_HAS_movcond_i32      1
 #define TCG_TARGET_HAS_muls2_i32        1
-
-#ifdef __ARM_ARCH_EXT_IDIV__
-#define TCG_TARGET_HAS_div_i32          1
-#else
-#define TCG_TARGET_HAS_div_i32          0
-#endif
+#define TCG_TARGET_HAS_div_i32          use_idiv_instructions
 
 extern bool tcg_target_deposit_valid(int ofs, int len);
 #define TCG_TARGET_deposit_i32_valid  tcg_target_deposit_valid
-- 
1.8.1.4

Re: [Qemu-devel] [PATCH 3/5] tcg-arm: Make use of conditional availability of opcodes for divide

[Claudio Fontana]

Richard wrote (eons ago):
> We can now detect and use divide instructions at runtime, rather than
> having to restrict their availability to compile-time.
> 
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>  tcg/arm/tcg-target.c | 16 ++++++++++++++--
>  tcg/arm/tcg-target.h | 14 ++++++++------
>  2 files changed, 22 insertions(+), 8 deletions(-)
> 
> diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
> index 3d43412..f6bc165 100644
> --- a/tcg/arm/tcg-target.c
> +++ b/tcg/arm/tcg-target.c
> @@ -67,6 +67,13 @@ static const int use_armv7_instructions = 0;
>  #endif
>  #undef USE_ARMV7_INSTRUCTIONS
>  
> +#ifndef use_idiv_instructions
> +bool use_idiv_instructions;
> +#endif
> +#ifdef CONFIG_GETAUXVAL
> +# include <sys/auxv.h>
> +#endif
> +
>  #ifndef NDEBUG
>  static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
>      "%r0",
> @@ -2041,18 +2048,23 @@ static const TCGTargetOpDef arm_op_defs[] = {
>  
>      { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
>  
> -#if TCG_TARGET_HAS_div_i32
>      { INDEX_op_div_i32, { "r", "r", "r" } },
>      { INDEX_op_rem_i32, { "r", "r", "r" } },
>      { INDEX_op_divu_i32, { "r", "r", "r" } },
>      { INDEX_op_remu_i32, { "r", "r", "r" } },
> -#endif
>  
>      { -1 },
>  };
>  
>  static void tcg_target_init(TCGContext *s)
>  {
> +#if defined(CONFIG_GETAUXVAL) && !defined(use_idiv_instructions)
> +    {
> +        unsigned long hwcap = getauxval(AT_HWCAP);
> +        use_idiv_instructions = hwcap & (HWCAP_ARM_IDIVA | HWCAP_ARM_IDIVT);
> +    }
> +#endif
> +
>  #if !defined(CONFIG_USER_ONLY)
>      /* fail safe */
>      if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
> diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
> index 3be41cc..4e1a88f 100644
> --- a/tcg/arm/tcg-target.h
> +++ b/tcg/arm/tcg-target.h
> @@ -49,6 +49,13 @@ typedef enum {
>  
>  #define TCG_TARGET_NB_REGS 16
>  
> +#ifdef __ARM_ARCH_EXT_IDIV__
> +#define use_idiv_instructions  1
> +#else
> +extern bool use_idiv_instructions;
> +#endif
> +
> +
>  /* used for function call generation */
>  #define TCG_REG_CALL_STACK             TCG_REG_R13
>  #define TCG_TARGET_STACK_ALIGN         8
> @@ -73,12 +80,7 @@ typedef enum {
>  #define TCG_TARGET_HAS_deposit_i32      1
>  #define TCG_TARGET_HAS_movcond_i32      1
>  #define TCG_TARGET_HAS_muls2_i32        1
> -
> -#ifdef __ARM_ARCH_EXT_IDIV__
> -#define TCG_TARGET_HAS_div_i32          1
> -#else
> -#define TCG_TARGET_HAS_div_i32          0
> -#endif
> +#define TCG_TARGET_HAS_div_i32          use_idiv_instructions
>  
>  extern bool tcg_target_deposit_valid(int ofs, int len);
>  #define TCG_TARGET_deposit_i32_valid  tcg_target_deposit_valid
> -- 
> 1.8.1.4

this should probably be rebased on latest git imo, because it fails to apply at the moment due to the removal of the assertions on (1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry) etc.

Claudio