* [Qemu-devel] [PATCH] q35 chipset: Extend support of SMBUS(module pm_smbus.c) HST_STS register v2.
@ 2013-06-27 23:14 Maksim Ratnikov
2013-06-28 19:04 ` Anthony Liguori
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Maksim Ratnikov @ 2013-06-27 23:14 UTC (permalink / raw)
To: qemu-devel; +Cc: Anthony Liguori
From b4c324b42b488aca76aae06c8fa23a45acd91fcf Mon Sep 17 00:00:00 2001
From: MRatnikov <m.o.ratnikov@gmail.com>
Date: Fri, 28 Jun 2013 02:57:51 +0400
Subject: [PATCH] Extend support of SMBUS(module pm_smbus.c) HST_STS
register v2
Signed-off-by: MRatnikov <m.o.ratnikov@gmail.com>
---
Previous realization doesn't consider flags in the status register.
Add DS and INTR bits of HST_STS register set after transaction execution.
Update bits resetting in HST_STS register. Update error processing:
if DEV_ERR bit set transaction isn't execution.
hw/i2c/pm_smbus.c | 25 +++++++++++++++++++++++--
1 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/hw/i2c/pm_smbus.c b/hw/i2c/pm_smbus.c
index 0b5bb89..35f154e 100644
--- a/hw/i2c/pm_smbus.c
+++ b/hw/i2c/pm_smbus.c
@@ -32,6 +32,18 @@
#define SMBHSTDAT1 0x06
#define SMBBLKDAT 0x07
+#define STS_HOST_BUSY (1)
+#define STS_INTR (1<<1)
+#define STS_DEV_ERR (1<<2)
+#define STS_BUS_ERR (1<<3)
+#define STS_FAILED (1<<4)
+#define STS_SMBALERT (1<<5)
+#define STS_INUSE_STS (1<<6)
+#define STS_BYTE_DONE (1<<7)
+/* Signs of successfully transaction end :
+* ByteDoneStatus = 1 (STS_BYTE_DONE) and INTR = 1 (STS_INTR )
+*/
+
//#define DEBUG
#ifdef DEBUG
@@ -50,9 +62,14 @@ static void smb_transaction(PMSMBus *s)
i2c_bus *bus = s->smbus;
SMBUS_DPRINTF("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
+ /* Transaction isn't exec if STS_DEV_ERR bit set */
+ if ((s->smb_stat & STS_DEV_ERR) != 0) {
+ goto error;
+ }
switch(prot) {
case 0x0:
smbus_quick_command(bus, addr, read);
+ s->smb_stat |= STS_BYTE_DONE | STS_INTR;
break;
case 0x1:
if (read) {
@@ -60,6 +77,7 @@ static void smb_transaction(PMSMBus *s)
} else {
smbus_send_byte(bus, addr, cmd);
}
+ s->smb_stat |= STS_BYTE_DONE | STS_INTR;
break;
case 0x2:
if (read) {
@@ -67,6 +85,7 @@ static void smb_transaction(PMSMBus *s)
} else {
smbus_write_byte(bus, addr, cmd, s->smb_data0);
}
+ s->smb_stat |= STS_BYTE_DONE | STS_INTR;
break;
case 0x3:
if (read) {
@@ -77,6 +96,7 @@ static void smb_transaction(PMSMBus *s)
} else {
smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) |
s->smb_data0);
}
+ s->smb_stat |= STS_BYTE_DONE | STS_INTR;
break;
case 0x5:
if (read) {
@@ -84,6 +104,7 @@ static void smb_transaction(PMSMBus *s)
} else {
smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
}
+ s->smb_stat |= STS_BYTE_DONE | STS_INTR;
break;
default:
goto error;
@@ -91,7 +112,7 @@ static void smb_transaction(PMSMBus *s)
return;
error:
- s->smb_stat |= 0x04;
+ s->smb_stat |= STS_DEV_ERR;
}
static void smb_ioport_writeb(void *opaque, hwaddr addr, uint64_t val,
@@ -102,7 +123,7 @@ static void smb_ioport_writeb(void *opaque, hwaddr
addr, uint64_t val,
SMBUS_DPRINTF("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
switch(addr) {
case SMBHSTSTS:
- s->smb_stat = 0;
+ s->smb_stat = (~(val & 0xff)) & s->smb_stat;
s->smb_index = 0;
break;
case SMBHSTCNT:
--
1.7.3.4
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [Qemu-devel] [PATCH] q35 chipset: Extend support of SMBUS(module pm_smbus.c) HST_STS register v2.
2013-06-27 23:14 [Qemu-devel] [PATCH] q35 chipset: Extend support of SMBUS(module pm_smbus.c) HST_STS register v2 Maksim Ratnikov
@ 2013-06-28 19:04 ` Anthony Liguori
2013-07-01 22:29 ` [Qemu-devel] [PATCH] [PATCH] Extend support of SMBUS(module pm_smbus.c) HST_STS register MRatnikov
2013-07-10 19:33 ` [Qemu-devel] [PATCH] q35 chipset: Extend support of SMBUS(module pm_smbus.c) HST_STS register v2 Anthony Liguori
2 siblings, 0 replies; 4+ messages in thread
From: Anthony Liguori @ 2013-06-28 19:04 UTC (permalink / raw)
To: Maksim Ratnikov, qemu-devel
Maksim Ratnikov <m.o.ratnikov@gmail.com> writes:
> From b4c324b42b488aca76aae06c8fa23a45acd91fcf Mon Sep 17 00:00:00 2001
> From: MRatnikov <m.o.ratnikov@gmail.com>
> Date: Fri, 28 Jun 2013 02:57:51 +0400
> Subject: [PATCH] Extend support of SMBUS(module pm_smbus.c) HST_STS
> register v2
Patch is corrupted. Please send with git-send-email.
Regards,
Anthony Liguori
>
> Signed-off-by: MRatnikov <m.o.ratnikov@gmail.com>
> ---
> Previous realization doesn't consider flags in the status register.
> Add DS and INTR bits of HST_STS register set after transaction execution.
> Update bits resetting in HST_STS register. Update error processing:
> if DEV_ERR bit set transaction isn't execution.
>
> hw/i2c/pm_smbus.c | 25 +++++++++++++++++++++++--
> 1 files changed, 23 insertions(+), 2 deletions(-)
>
> diff --git a/hw/i2c/pm_smbus.c b/hw/i2c/pm_smbus.c
> index 0b5bb89..35f154e 100644
> --- a/hw/i2c/pm_smbus.c
> +++ b/hw/i2c/pm_smbus.c
> @@ -32,6 +32,18 @@
> #define SMBHSTDAT1 0x06
> #define SMBBLKDAT 0x07
>
> +#define STS_HOST_BUSY (1)
> +#define STS_INTR (1<<1)
> +#define STS_DEV_ERR (1<<2)
> +#define STS_BUS_ERR (1<<3)
> +#define STS_FAILED (1<<4)
> +#define STS_SMBALERT (1<<5)
> +#define STS_INUSE_STS (1<<6)
> +#define STS_BYTE_DONE (1<<7)
> +/* Signs of successfully transaction end :
> +* ByteDoneStatus = 1 (STS_BYTE_DONE) and INTR = 1 (STS_INTR )
> +*/
> +
> //#define DEBUG
>
> #ifdef DEBUG
> @@ -50,9 +62,14 @@ static void smb_transaction(PMSMBus *s)
> i2c_bus *bus = s->smbus;
>
> SMBUS_DPRINTF("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
> + /* Transaction isn't exec if STS_DEV_ERR bit set */
> + if ((s->smb_stat & STS_DEV_ERR) != 0) {
> + goto error;
> + }
> switch(prot) {
> case 0x0:
> smbus_quick_command(bus, addr, read);
> + s->smb_stat |= STS_BYTE_DONE | STS_INTR;
> break;
> case 0x1:
> if (read) {
> @@ -60,6 +77,7 @@ static void smb_transaction(PMSMBus *s)
> } else {
> smbus_send_byte(bus, addr, cmd);
> }
> + s->smb_stat |= STS_BYTE_DONE | STS_INTR;
> break;
> case 0x2:
> if (read) {
> @@ -67,6 +85,7 @@ static void smb_transaction(PMSMBus *s)
> } else {
> smbus_write_byte(bus, addr, cmd, s->smb_data0);
> }
> + s->smb_stat |= STS_BYTE_DONE | STS_INTR;
> break;
> case 0x3:
> if (read) {
> @@ -77,6 +96,7 @@ static void smb_transaction(PMSMBus *s)
> } else {
> smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) |
> s->smb_data0);
> }
> + s->smb_stat |= STS_BYTE_DONE | STS_INTR;
> break;
> case 0x5:
> if (read) {
> @@ -84,6 +104,7 @@ static void smb_transaction(PMSMBus *s)
> } else {
> smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
> }
> + s->smb_stat |= STS_BYTE_DONE | STS_INTR;
> break;
> default:
> goto error;
> @@ -91,7 +112,7 @@ static void smb_transaction(PMSMBus *s)
> return;
>
> error:
> - s->smb_stat |= 0x04;
> + s->smb_stat |= STS_DEV_ERR;
> }
>
> static void smb_ioport_writeb(void *opaque, hwaddr addr, uint64_t val,
> @@ -102,7 +123,7 @@ static void smb_ioport_writeb(void *opaque, hwaddr
> addr, uint64_t val,
> SMBUS_DPRINTF("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
> switch(addr) {
> case SMBHSTSTS:
> - s->smb_stat = 0;
> + s->smb_stat = (~(val & 0xff)) & s->smb_stat;
> s->smb_index = 0;
> break;
> case SMBHSTCNT:
> --
> 1.7.3.4
^ permalink raw reply [flat|nested] 4+ messages in thread* [Qemu-devel] [PATCH] [PATCH] Extend support of SMBUS(module pm_smbus.c) HST_STS register.
2013-06-27 23:14 [Qemu-devel] [PATCH] q35 chipset: Extend support of SMBUS(module pm_smbus.c) HST_STS register v2 Maksim Ratnikov
2013-06-28 19:04 ` Anthony Liguori
@ 2013-07-01 22:29 ` MRatnikov
2013-07-10 19:33 ` [Qemu-devel] [PATCH] q35 chipset: Extend support of SMBUS(module pm_smbus.c) HST_STS register v2 Anthony Liguori
2 siblings, 0 replies; 4+ messages in thread
From: MRatnikov @ 2013-07-01 22:29 UTC (permalink / raw)
To: qemu-devel; +Cc: m.o.ratnikov, aliguori
Previous realization doesn't consider flags in the status register.
Add DS and INTR bits of HST_STS register set after transaction execution.
Update bits resetting in HST_STS register. Update error processing:
if DEV_ERR bit set transaction isn't execution.
Signed-off-by: MRatnikov <m.o.ratnikov@gmail.com>
---
hw/i2c/pm_smbus.c | 25 +++++++++++++++++++++++--
1 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/hw/i2c/pm_smbus.c b/hw/i2c/pm_smbus.c
index 0b5bb89..35f154e 100644
--- a/hw/i2c/pm_smbus.c
+++ b/hw/i2c/pm_smbus.c
@@ -32,6 +32,18 @@
#define SMBHSTDAT1 0x06
#define SMBBLKDAT 0x07
+#define STS_HOST_BUSY (1)
+#define STS_INTR (1<<1)
+#define STS_DEV_ERR (1<<2)
+#define STS_BUS_ERR (1<<3)
+#define STS_FAILED (1<<4)
+#define STS_SMBALERT (1<<5)
+#define STS_INUSE_STS (1<<6)
+#define STS_BYTE_DONE (1<<7)
+/* Signs of successfully transaction end :
+* ByteDoneStatus = 1 (STS_BYTE_DONE) and INTR = 1 (STS_INTR )
+*/
+
//#define DEBUG
#ifdef DEBUG
@@ -50,9 +62,14 @@ static void smb_transaction(PMSMBus *s)
i2c_bus *bus = s->smbus;
SMBUS_DPRINTF("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
+ /* Transaction isn't exec if STS_DEV_ERR bit set */
+ if ((s->smb_stat & STS_DEV_ERR) != 0) {
+ goto error;
+ }
switch(prot) {
case 0x0:
smbus_quick_command(bus, addr, read);
+ s->smb_stat |= STS_BYTE_DONE | STS_INTR;
break;
case 0x1:
if (read) {
@@ -60,6 +77,7 @@ static void smb_transaction(PMSMBus *s)
} else {
smbus_send_byte(bus, addr, cmd);
}
+ s->smb_stat |= STS_BYTE_DONE | STS_INTR;
break;
case 0x2:
if (read) {
@@ -67,6 +85,7 @@ static void smb_transaction(PMSMBus *s)
} else {
smbus_write_byte(bus, addr, cmd, s->smb_data0);
}
+ s->smb_stat |= STS_BYTE_DONE | STS_INTR;
break;
case 0x3:
if (read) {
@@ -77,6 +96,7 @@ static void smb_transaction(PMSMBus *s)
} else {
smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
}
+ s->smb_stat |= STS_BYTE_DONE | STS_INTR;
break;
case 0x5:
if (read) {
@@ -84,6 +104,7 @@ static void smb_transaction(PMSMBus *s)
} else {
smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
}
+ s->smb_stat |= STS_BYTE_DONE | STS_INTR;
break;
default:
goto error;
@@ -91,7 +112,7 @@ static void smb_transaction(PMSMBus *s)
return;
error:
- s->smb_stat |= 0x04;
+ s->smb_stat |= STS_DEV_ERR;
}
static void smb_ioport_writeb(void *opaque, hwaddr addr, uint64_t val,
@@ -102,7 +123,7 @@ static void smb_ioport_writeb(void *opaque, hwaddr addr, uint64_t val,
SMBUS_DPRINTF("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
switch(addr) {
case SMBHSTSTS:
- s->smb_stat = 0;
+ s->smb_stat = (~(val & 0xff)) & s->smb_stat;
s->smb_index = 0;
break;
case SMBHSTCNT:
--
1.7.3.4
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [Qemu-devel] [PATCH] q35 chipset: Extend support of SMBUS(module pm_smbus.c) HST_STS register v2.
2013-06-27 23:14 [Qemu-devel] [PATCH] q35 chipset: Extend support of SMBUS(module pm_smbus.c) HST_STS register v2 Maksim Ratnikov
2013-06-28 19:04 ` Anthony Liguori
2013-07-01 22:29 ` [Qemu-devel] [PATCH] [PATCH] Extend support of SMBUS(module pm_smbus.c) HST_STS register MRatnikov
@ 2013-07-10 19:33 ` Anthony Liguori
2 siblings, 0 replies; 4+ messages in thread
From: Anthony Liguori @ 2013-07-10 19:33 UTC (permalink / raw)
To: Maksim Ratnikov, qemu-devel; +Cc: Anthony Liguori
Applied. Thanks.
Regards,
Anthony Liguori
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2013-07-10 19:33 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2013-06-27 23:14 [Qemu-devel] [PATCH] q35 chipset: Extend support of SMBUS(module pm_smbus.c) HST_STS register v2 Maksim Ratnikov
2013-06-28 19:04 ` Anthony Liguori
2013-07-01 22:29 ` [Qemu-devel] [PATCH] [PATCH] Extend support of SMBUS(module pm_smbus.c) HST_STS register MRatnikov
2013-07-10 19:33 ` [Qemu-devel] [PATCH] q35 chipset: Extend support of SMBUS(module pm_smbus.c) HST_STS register v2 Anthony Liguori
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