* [U-Boot] [PATCH v2 1/2] mx6: Factor out common HDMI setup code
@ 2013-07-24 16:31 Pardeep Kumar Singla
2013-07-24 16:31 ` [U-Boot] [PATCH v2 2/2] mx6qsabresd: Add splash screen support via HDMI Pardeep Kumar Singla
2013-07-24 17:02 ` [U-Boot] [PATCH v2 1/2] mx6: Factor out common HDMI setup code Eric Nelson
0 siblings, 2 replies; 3+ messages in thread
From: Pardeep Kumar Singla @ 2013-07-24 16:31 UTC (permalink / raw)
To: u-boot
Instead of duplicating HDMI setup code for every mx6 board, factor out the common code
Signed-off-by: Pardeep Kumar Singla <b45784@freescale.com>
---
Changes since v1:
Remove dev paramter from imx_enable_hdmi_phy function to make interface clearer.
Boards that support auto-detect (mx6qsabrelite/nitrogen6x) are wrapping it.
arch/arm/cpu/armv7/mx6/soc.c | 48 +++++++++++++++++++++++++
arch/arm/include/asm/arch-mx6/mxc_hdmi.h | 6 ++++
board/boundary/nitrogen6x/nitrogen6x.c | 43 ++++------------------
board/freescale/mx6qsabrelite/mx6qsabrelite.c | 45 ++++-------------------
board/wandboard/wandboard.c | 43 ++--------------------
include/configs/mx6qsabrelite.h | 1 +
include/configs/nitrogen6x.h | 1 +
include/configs/wandboard.h | 1 +
8 files changed, 73 insertions(+), 115 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index fc436fb..2c89c59 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -32,6 +32,8 @@
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/dma.h>
#include <stdbool.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
struct scu_regs {
u32 ctrl;
@@ -228,3 +230,49 @@ const struct boot_mode soc_boot_modes[] = {
void s_init(void)
{
}
+
+#ifdef CONFIG_IMX_HDMI
+void imx_enable_hdmi_phy(void)
+{
+ struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+ u8 reg;
+ reg = readb(&hdmi->phy_conf0);
+ reg |= HDMI_PHY_CONF0_PDZ_MASK;
+ writeb(reg, &hdmi->phy_conf0);
+ udelay(3000);
+ reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
+ writeb(reg, &hdmi->phy_conf0);
+ udelay(3000);
+ reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
+ writeb(reg, &hdmi->phy_conf0);
+ writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
+}
+
+void imx_setup_hdmi(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+ int reg;
+
+ /* Turn on IPU clock */
+ reg = readl(&mxc_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
+ writel(reg, &mxc_ccm->CCGR3);
+
+ /* Turn on HDMI PHY clock */
+ reg = readl(&mxc_ccm->CCGR2);
+ reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
+ MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
+ writel(reg, &mxc_ccm->CCGR2);
+ writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
+ reg = readl(&mxc_ccm->chsccdr);
+ reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
+ MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
+ reg |= (CHSCCDR_PODF_DIVIDE_BY_3
+ << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
+ |(CHSCCDR_IPU_PRE_CLK_540M_PFD
+ << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->chsccdr);
+}
+#endif
diff --git a/arch/arm/include/asm/arch-mx6/mxc_hdmi.h b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h
index 9dccb3f..06e2bc4 100644
--- a/arch/arm/include/asm/arch-mx6/mxc_hdmi.h
+++ b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h
@@ -21,6 +21,12 @@
#ifndef __MXC_HDMI_H__
#define __MXC_HDMI_H__
+#ifdef CONFIG_IMX_HDMI
+#include<asm/arch/sys_proto.h>
+void imx_enable_hdmi_phy(void);
+void imx_setup_hdmi(void);
+#endif
+
/*
* Hdmi controller registers
*/
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index 8f0f9b8..45a8f7a 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -480,22 +480,9 @@ static int detect_hdmi(struct display_info_t const *dev)
return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
}
-static void enable_hdmi(struct display_info_t const *dev)
+static void do_enable_hdmi(struct display_info_t const *dev)
{
- struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
- u8 reg;
- printf("%s: setup HDMI monitor\n", __func__);
- reg = readb(&hdmi->phy_conf0);
- reg |= HDMI_PHY_CONF0_PDZ_MASK;
- writeb(reg, &hdmi->phy_conf0);
-
- udelay(3000);
- reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
- writeb(reg, &hdmi->phy_conf0);
- udelay(3000);
- reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
- writeb(reg, &hdmi->phy_conf0);
- writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
+ imx_enable_hdmi_phy();
}
static int detect_i2c(struct display_info_t const *dev)
@@ -528,7 +515,7 @@ static struct display_info_t const displays[] = {{
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB24,
.detect = detect_hdmi,
- .enable = enable_hdmi,
+ .enable = do_enable_hdmi,
.mode = {
.name = "HDMI",
.refresh = 60,
@@ -653,25 +640,14 @@ static void setup_display(void)
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
- struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
-
int reg;
+ imx_setup_hdmi();
/* Turn on LDB0,IPU,IPU DI0 clocks */
reg = __raw_readl(&mxc_ccm->CCGR3);
- reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
- |MXC_CCM_CCGR3_LDB_DI0_MASK;
+ reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
writel(reg, &mxc_ccm->CCGR3);
- /* Turn on HDMI PHY clock */
- reg = __raw_readl(&mxc_ccm->CCGR2);
- reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
- |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
- writel(reg, &mxc_ccm->CCGR2);
-
- /* clear HDMI PHY reset */
- writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
-
/* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
@@ -689,15 +665,8 @@ static void setup_display(void)
writel(reg, &mxc_ccm->cscmr2);
reg = readl(&mxc_ccm->chsccdr);
- reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
- |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
- |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
- <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
- |(CHSCCDR_PODF_DIVIDE_BY_3
- <<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
- |(CHSCCDR_IPU_PRE_CLK_540M_PFD
- <<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+ <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->chsccdr);
reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index 862bc30..cf04312 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -452,24 +452,10 @@ static int detect_hdmi(struct display_info_t const *dev)
return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
}
-static void enable_hdmi(struct display_info_t const *dev)
+static void do_enable_hdmi(struct display_info_t const *dev)
{
- struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
- u8 reg;
- printf("%s: setup HDMI monitor\n", __func__);
- reg = readb(&hdmi->phy_conf0);
- reg |= HDMI_PHY_CONF0_PDZ_MASK;
- writeb(reg, &hdmi->phy_conf0);
-
- udelay(3000);
- reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
- writeb(reg, &hdmi->phy_conf0);
- udelay(3000);
- reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
- writeb(reg, &hdmi->phy_conf0);
- writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
+ imx_enable_hdmi_phy();
}
-
static int detect_i2c(struct display_info_t const *dev)
{
return ((0 == i2c_set_bus_num(dev->bus))
@@ -500,7 +486,7 @@ static struct display_info_t const displays[] = {{
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB24,
.detect = detect_hdmi,
- .enable = enable_hdmi,
+ .enable = do_enable_hdmi,
.mode = {
.name = "HDMI",
.refresh = 60,
@@ -625,25 +611,15 @@ static void setup_display(void)
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
- struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
-
int reg;
+ imx_setup_hdmi();
+
/* Turn on LDB0,IPU,IPU DI0 clocks */
reg = __raw_readl(&mxc_ccm->CCGR3);
- reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
- |MXC_CCM_CCGR3_LDB_DI0_MASK;
+ reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
writel(reg, &mxc_ccm->CCGR3);
- /* Turn on HDMI PHY clock */
- reg = __raw_readl(&mxc_ccm->CCGR2);
- reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
- |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
- writel(reg, &mxc_ccm->CCGR2);
-
- /* clear HDMI PHY reset */
- writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
-
/* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
@@ -661,15 +637,8 @@ static void setup_display(void)
writel(reg, &mxc_ccm->cscmr2);
reg = readl(&mxc_ccm->chsccdr);
- reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
- |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
- |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
- <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
- |(CHSCCDR_PODF_DIVIDE_BY_3
- <<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
- |(CHSCCDR_IPU_PRE_CLK_540M_PFD
- <<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+ <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->chsccdr);
reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 43c02ac..3ff97f3 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -211,23 +211,6 @@ int board_phy_config(struct phy_device *phydev)
}
#if defined(CONFIG_VIDEO_IPUV3)
-static void enable_hdmi(void)
-{
- struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
- u8 reg;
- reg = readb(&hdmi->phy_conf0);
- reg |= HDMI_PHY_CONF0_PDZ_MASK;
- writeb(reg, &hdmi->phy_conf0);
-
- udelay(3000);
- reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
- writeb(reg, &hdmi->phy_conf0);
- udelay(3000);
- reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
- writeb(reg, &hdmi->phy_conf0);
- writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
-}
-
static struct fb_videomode const hdmi = {
.name = "HDMI",
.refresh = 60,
@@ -253,7 +236,7 @@ int board_video_skip(void)
if (ret)
printf("HDMI cannot be configured: %d\n", ret);
- enable_hdmi();
+ imx_enable_hdmi_phy();
return ret;
}
@@ -261,33 +244,13 @@ int board_video_skip(void)
static void setup_display(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
int reg;
- /* Turn on IPU clock */
- reg = readl(&mxc_ccm->CCGR3);
- reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
- writel(reg, &mxc_ccm->CCGR3);
-
- /* Turn on HDMI PHY clock */
- reg = readl(&mxc_ccm->CCGR2);
- reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
- | MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
- writel(reg, &mxc_ccm->CCGR2);
-
- /* clear HDMI PHY reset */
- writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
+ imx_setup_hdmi();
reg = readl(&mxc_ccm->chsccdr);
- reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
- | MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
- | MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
- << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
- | (CHSCCDR_PODF_DIVIDE_BY_3
- << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
- | (CHSCCDR_IPU_PRE_CLK_540M_PFD
- << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+ << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->chsccdr);
}
#endif /* CONFIG_VIDEO_IPUV3 */
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index c7db81d..6127347 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -141,6 +141,7 @@
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
#define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_IMX_HDMI
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index 74df66c..0b665dc 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -154,6 +154,7 @@
#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_CMD_HDMIDETECT
#define CONFIG_CONSOLE_MUX
+#define CONFIG_IMX_HDMI
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index dd06bd7..1f83e89 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -100,6 +100,7 @@
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_IMX_HDMI
#if defined(CONFIG_MX6DL)
#define CONFIG_DEFAULT_FDT_FILE "imx6dl-wandboard.dtb"
--
1.7.9.5
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [U-Boot] [PATCH v2 2/2] mx6qsabresd: Add splash screen support via HDMI
2013-07-24 16:31 [U-Boot] [PATCH v2 1/2] mx6: Factor out common HDMI setup code Pardeep Kumar Singla
@ 2013-07-24 16:31 ` Pardeep Kumar Singla
2013-07-24 17:02 ` [U-Boot] [PATCH v2 1/2] mx6: Factor out common HDMI setup code Eric Nelson
1 sibling, 0 replies; 3+ messages in thread
From: Pardeep Kumar Singla @ 2013-07-24 16:31 UTC (permalink / raw)
To: u-boot
Signed-off-by: Pardeep Kumar Singla <b45784@freescale.com>
---
Changes since v1:
Remove dev paramter from imx_enable_hdmi_phy function to make interface clearer.
Remove display_info_t structure.
board/freescale/mx6sabresd/mx6sabresd.c | 63 ++++++++++++++++++++++++++++++-
include/configs/mx6sabre_common.h | 3 +-
include/configs/mx6sabresd.h | 19 ++++++++++
3 files changed, 83 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 222ee98..faab344 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -29,7 +29,12 @@
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <netdev.h>
-
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
@@ -239,6 +244,59 @@ int board_phy_config(struct phy_device *phydev)
return 0;
}
+#if defined(CONFIG_VIDEO_IPUV3)
+static struct fb_videomode const hdmi = {
+ .name = "HDMI",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+};
+
+int board_video_skip(void)
+{
+ int ret;
+
+ ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24);
+
+ if (ret)
+ printf("HDMI cannot be configured: %d\n", ret);
+
+ imx_enable_hdmi_phy();
+ return ret;
+}
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ int reg;
+
+ imx_setup_hdmi();
+
+ reg = readl(&mxc_ccm->chsccdr);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+ << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->chsccdr);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
int board_eth_init(bd_t *bis)
{
int ret;
@@ -255,6 +313,9 @@ int board_eth_init(bd_t *bis)
int board_early_init_f(void)
{
setup_iomux_uart();
+#if defined(CONFIG_VIDEO_IPUV3)
+ setup_display();
+#endif
return 0;
}
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index 53cc559..dd93fff 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -20,6 +20,7 @@
#define CONFIG_MX6
#include "mx6_common.h"
+#include <asm/sizes.h>
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
@@ -32,7 +33,7 @@
#define CONFIG_REVISION_TAG
/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
index 76675f4..5637c19 100644
--- a/include/configs/mx6sabresd.h
+++ b/include/configs/mx6sabresd.h
@@ -17,6 +17,9 @@
#ifndef __MX6QSABRESD_CONFIG_H
#define __MX6QSABRESD_CONFIG_H
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
#define CONFIG_MACH_TYPE 3980
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_CONSOLE_DEV "ttymxc0"
@@ -31,4 +34,20 @@
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC3 */
#endif
+/* Framebuffer */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_IMX_HDMI
+
#endif /* __MX6QSABRESD_CONFIG_H */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [U-Boot] [PATCH v2 1/2] mx6: Factor out common HDMI setup code
2013-07-24 16:31 [U-Boot] [PATCH v2 1/2] mx6: Factor out common HDMI setup code Pardeep Kumar Singla
2013-07-24 16:31 ` [U-Boot] [PATCH v2 2/2] mx6qsabresd: Add splash screen support via HDMI Pardeep Kumar Singla
@ 2013-07-24 17:02 ` Eric Nelson
1 sibling, 0 replies; 3+ messages in thread
From: Eric Nelson @ 2013-07-24 17:02 UTC (permalink / raw)
To: u-boot
Hi Pardeep,
On 07/24/2013 09:31 AM, Pardeep Kumar Singla wrote:
> Instead of duplicating HDMI setup code for every mx6 board, factor out the common code
>
> Signed-off-by: Pardeep Kumar Singla <b45784@freescale.com>
> ---
> Changes since v1:
> Remove dev paramter from imx_enable_hdmi_phy function to make interface clearer.
> Boards that support auto-detect (mx6qsabrelite/nitrogen6x) are wrapping it.
>
> arch/arm/cpu/armv7/mx6/soc.c | 48 +++++++++++++++++++++++++
> arch/arm/include/asm/arch-mx6/mxc_hdmi.h | 6 ++++
> board/boundary/nitrogen6x/nitrogen6x.c | 43 ++++------------------
> board/freescale/mx6qsabrelite/mx6qsabrelite.c | 45 ++++-------------------
> board/wandboard/wandboard.c | 43 ++--------------------
> include/configs/mx6qsabrelite.h | 1 +
> include/configs/nitrogen6x.h | 1 +
> include/configs/wandboard.h | 1 +
> 8 files changed, 73 insertions(+), 115 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
> index fc436fb..2c89c59 100644
> --- a/arch/arm/cpu/armv7/mx6/soc.c
> +++ b/arch/arm/cpu/armv7/mx6/soc.c
> @@ -32,6 +32,8 @@
> #include <asm/imx-common/boot_mode.h>
> #include <asm/imx-common/dma.h>
> #include <stdbool.h>
> +#include <asm/arch/mxc_hdmi.h>
> +#include <asm/arch/crm_regs.h>
>
> struct scu_regs {
> u32 ctrl;
> @@ -228,3 +230,49 @@ const struct boot_mode soc_boot_modes[] = {
> void s_init(void)
> {
> }
> +
> +#ifdef CONFIG_IMX_HDMI
> +void imx_enable_hdmi_phy(void)
> +{
> + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
> + u8 reg;
> + reg = readb(&hdmi->phy_conf0);
> + reg |= HDMI_PHY_CONF0_PDZ_MASK;
> + writeb(reg, &hdmi->phy_conf0);
> + udelay(3000);
> + reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
> + writeb(reg, &hdmi->phy_conf0);
> + udelay(3000);
> + reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
> + writeb(reg, &hdmi->phy_conf0);
> + writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
> +}
> +
> +void imx_setup_hdmi(void)
> +{
> + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
> + int reg;
> +
This should probably not go here, or at least should
be visible elsewhere because it's needed for boards
which don't have HDMI exposed:
> + /* Turn on IPU clock */
> + reg = readl(&mxc_ccm->CCGR3);
> + reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
> + writel(reg, &mxc_ccm->CCGR3);
> +
If (when) someone builds a board file that doesn't have
HDMI, they'll probably search a while for the
We probably want an 'enable_ipu_clock()' routine in
.../cpu/mx6/clock.c.
> + /* Turn on HDMI PHY clock */
> + reg = readl(&mxc_ccm->CCGR2);
> + reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
> + MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
> + writel(reg, &mxc_ccm->CCGR2);
> + writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
> + reg = readl(&mxc_ccm->chsccdr);
> + reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
> + MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
> + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
> + reg |= (CHSCCDR_PODF_DIVIDE_BY_3
> + << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
> + |(CHSCCDR_IPU_PRE_CLK_540M_PFD
> + << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
> + writel(reg, &mxc_ccm->chsccdr);
> +}
> +#endif
> diff --git a/arch/arm/include/asm/arch-mx6/mxc_hdmi.h b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h
> index 9dccb3f..06e2bc4 100644
> --- a/arch/arm/include/asm/arch-mx6/mxc_hdmi.h
> +++ b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h
> @@ -21,6 +21,12 @@
> #ifndef __MXC_HDMI_H__
> #define __MXC_HDMI_H__
>
> +#ifdef CONFIG_IMX_HDMI
Why sys_proto.h?
> +#include<asm/arch/sys_proto.h>
> +void imx_enable_hdmi_phy(void);
> +void imx_setup_hdmi(void);
> +#endif
> +
The rest looks good to me.
Regards,
Eric
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2013-07-24 17:02 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2013-07-24 16:31 [U-Boot] [PATCH v2 1/2] mx6: Factor out common HDMI setup code Pardeep Kumar Singla
2013-07-24 16:31 ` [U-Boot] [PATCH v2 2/2] mx6qsabresd: Add splash screen support via HDMI Pardeep Kumar Singla
2013-07-24 17:02 ` [U-Boot] [PATCH v2 1/2] mx6: Factor out common HDMI setup code Eric Nelson
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