* [PATCH] arm: zynq: dt: Set correct L2 ram latencies @ 2013-07-31 23:24 ` Soren Brinkmann 0 siblings, 0 replies; 4+ messages in thread From: Soren Brinkmann @ 2013-07-31 23:24 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> --- arch/arm/boot/dts/zynq-7000.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 6f54a64..e32b92b 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -41,8 +41,8 @@ L2: cache-controller { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; - arm,data-latency = <2 3 2>; - arm,tag-latency = <2 3 2>; + arm,data-latency = <3 2 2>; + arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; -- 1.8.3.4 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH] arm: zynq: dt: Set correct L2 ram latencies @ 2013-07-31 23:24 ` Soren Brinkmann 0 siblings, 0 replies; 4+ messages in thread From: Soren Brinkmann @ 2013-07-31 23:24 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Russell King, Michal Simek Cc: linux-kernel, linux-arm-kernel, devicetree, Soren Brinkmann Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> --- arch/arm/boot/dts/zynq-7000.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 6f54a64..e32b92b 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -41,8 +41,8 @@ L2: cache-controller { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; - arm,data-latency = <2 3 2>; - arm,tag-latency = <2 3 2>; + arm,data-latency = <3 2 2>; + arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; -- 1.8.3.4 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH] arm: zynq: dt: Set correct L2 ram latencies 2013-07-31 23:24 ` Soren Brinkmann @ 2013-08-02 11:37 ` Michal Simek -1 siblings, 0 replies; 4+ messages in thread From: Michal Simek @ 2013-08-02 11:37 UTC (permalink / raw) To: linux-arm-kernel On 08/01/2013 01:24 AM, Soren Brinkmann wrote: > Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> > --- > arch/arm/boot/dts/zynq-7000.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi > index 6f54a64..e32b92b 100644 > --- a/arch/arm/boot/dts/zynq-7000.dtsi > +++ b/arch/arm/boot/dts/zynq-7000.dtsi > @@ -41,8 +41,8 @@ > L2: cache-controller { > compatible = "arm,pl310-cache"; > reg = <0xF8F02000 0x1000>; > - arm,data-latency = <2 3 2>; > - arm,tag-latency = <2 3 2>; > + arm,data-latency = <3 2 2>; > + arm,tag-latency = <2 2 2>; > cache-unified; > cache-level = <2>; > }; > Applied to zynq/dt. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 263 bytes Desc: OpenPGP digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20130802/495f5ce3/attachment-0001.sig> ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] arm: zynq: dt: Set correct L2 ram latencies @ 2013-08-02 11:37 ` Michal Simek 0 siblings, 0 replies; 4+ messages in thread From: Michal Simek @ 2013-08-02 11:37 UTC (permalink / raw) To: Soren Brinkmann Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Russell King, Michal Simek, linux-kernel, linux-arm-kernel, devicetree [-- Attachment #1: Type: text/plain, Size: 1095 bytes --] On 08/01/2013 01:24 AM, Soren Brinkmann wrote: > Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> > --- > arch/arm/boot/dts/zynq-7000.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi > index 6f54a64..e32b92b 100644 > --- a/arch/arm/boot/dts/zynq-7000.dtsi > +++ b/arch/arm/boot/dts/zynq-7000.dtsi > @@ -41,8 +41,8 @@ > L2: cache-controller { > compatible = "arm,pl310-cache"; > reg = <0xF8F02000 0x1000>; > - arm,data-latency = <2 3 2>; > - arm,tag-latency = <2 3 2>; > + arm,data-latency = <3 2 2>; > + arm,tag-latency = <2 2 2>; > cache-unified; > cache-level = <2>; > }; > Applied to zynq/dt. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform [-- Attachment #2: OpenPGP digital signature --] [-- Type: application/pgp-signature, Size: 263 bytes --] ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2013-08-02 11:37 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-07-31 23:24 [PATCH] arm: zynq: dt: Set correct L2 ram latencies Soren Brinkmann 2013-07-31 23:24 ` Soren Brinkmann 2013-08-02 11:37 ` Michal Simek 2013-08-02 11:37 ` Michal Simek
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