From: Andy Lutomirski <luto@amacapital.net>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/i915: Use Write-Through cacheing for the display plane on Iris
Date: Fri, 02 Aug 2013 11:45:22 -0700 [thread overview]
Message-ID: <51FBFE42.2000503@amacapital.net> (raw)
In-Reply-To: <1375378795-1869-1-git-send-email-chris@chris-wilson.co.uk>
On 08/01/2013 10:39 AM, Chris Wilson wrote:
> Haswell GT3e has the unique feature of supporting Write-Through cacheing
> of objects within the eLLC/LLC. The purpose of this is to enable the display
> plane to remain coherent whilst objects lie resident in the eLLC/LLC - so
> that we, in theory, get the best of both worlds, perfect display and fast
> access.
>
> However, we still need to be careful as the CPU does not see the WT when
> accessing the cache. In particular, this means that we need to flush the
> cache lines after writing to an object through the CPU, and on
> transitioning from a cached state to WT.
>
I'm planning on adding ioremap_wt, etc sometime soon (for an unrelated
reason). Would this be useful here?
If so, do you need it for real RAM (i.e. pages that the kernel considers
to be direct-mappable RAM) or just for MMIO space?
--Andy
next prev parent reply other threads:[~2013-08-02 18:45 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-08-01 17:39 [PATCH 1/2] drm/i915: Use Write-Through cacheing for the display plane on Iris Chris Wilson
2013-08-01 17:39 ` [PATCH 2/2] drm/i915: Tidy the macro casting by using an inline function Chris Wilson
2013-08-02 16:22 ` Paulo Zanoni
2013-08-05 6:55 ` Daniel Vetter
2013-08-02 14:51 ` [PATCH 1/2] drm/i915: Use Write-Through cacheing for the display plane on Iris Ville Syrjälä
2013-08-02 20:03 ` Chris Wilson
2013-08-04 19:47 ` Daniel Vetter
2013-08-02 18:45 ` Andy Lutomirski [this message]
2013-08-02 19:21 ` Ben Widawsky
2013-08-02 19:47 ` Andy Lutomirski
2013-08-02 20:08 ` Chris Wilson
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