[PATCH 1/5] MIPS: ralink: mt7620: add verbose ram info

[PATCH 1/5] MIPS: ralink: mt7620: add verbose ram info

[John Crispin]

Make the code print which of SDRAM, DDR1 or DDR2 was detected.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/ralink/mt7620.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
index 0018b1a..ccdec5a 100644
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -214,16 +214,19 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
 
 	switch (dram_type) {
 	case SYSCFG0_DRAM_TYPE_SDRAM:
+		pr_info("Board has SDRAM\n");
 		soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
 		soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
 		break;
 
 	case SYSCFG0_DRAM_TYPE_DDR1:
+		pr_info("Board has DDR1\n");
 		soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
 		soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
 		break;
 
 	case SYSCFG0_DRAM_TYPE_DDR2:
+		pr_info("Board has DDR2\n");
 		soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
 		soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
 		break;
-- 
1.7.10.4

[PATCH 2/5] MIPS: ralink: mt7620: add spi clock definition

[John Crispin]

The definition of the spi clock is missing.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/ralink/mt7620.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
index ccdec5a..769296f 100644
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -167,6 +167,7 @@ void __init ralink_clk_init(void)
 	ralink_clk_add("cpu", cpu_rate);
 	ralink_clk_add("10000100.timer", 40000000);
 	ralink_clk_add("10000500.uart", 40000000);
+	ralink_clk_add("10000b00.spi", 40000000);
 	ralink_clk_add("10000c00.uartlite", 40000000);
 }
 
-- 
1.7.10.4

[PATCH 3/5] MIPS: ralink: mt7620: add wdt clock definition

[John Crispin]

The definition of the wdt clock is missing.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/ralink/mt7620.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
index 769296f..7b360a8 100644
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -166,6 +166,7 @@ void __init ralink_clk_init(void)
 
 	ralink_clk_add("cpu", cpu_rate);
 	ralink_clk_add("10000100.timer", 40000000);
+	ralink_clk_add("10000120.watchdog", 40000000);
 	ralink_clk_add("10000500.uart", 40000000);
 	ralink_clk_add("10000b00.spi", 40000000);
 	ralink_clk_add("10000c00.uartlite", 40000000);
-- 
1.7.10.4

[PATCH 4/5] MIPS: ralink: mt7620: fix usb issue during frequency scaling

[John Crispin]

If the USB HCD is running and the cpu is scaled too low, then the USB stops
working. Increase the idle speed of the core to fix this if the kernel is
built with USB support.

The values are taken from the Ralink SDK Kernel.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/include/asm/mach-ralink/mt7620.h |    1 +
 arch/mips/ralink/mt7620.c                  |   19 +++++++++++++++++++
 2 files changed, 20 insertions(+)

diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
index 9809972..d469c69 100644
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
@@ -20,6 +20,7 @@
 #define SYSC_REG_CHIP_REV		0x0c
 #define SYSC_REG_SYSTEM_CONFIG0		0x10
 #define SYSC_REG_SYSTEM_CONFIG1		0x14
+#define SYSC_REG_CPU_SYS_CLKCFG		0x3c
 #define SYSC_REG_CPLL_CONFIG0		0x54
 #define SYSC_REG_CPLL_CONFIG1		0x58
 
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
index 7b360a8..23bb691 100644
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -20,6 +20,12 @@
 
 #include "common.h"
 
+/* clock scaling */
+#define CLKCFG_FDIV_MASK	0x1f00
+#define CLKCFG_FDIV_USB_VAL	0x0300
+#define CLKCFG_FFRAC_MASK	0x001f
+#define CLKCFG_FFRAC_USB_VAL	0x0003
+
 /* does the board have sdram or ddram */
 static int dram_type;
 
@@ -170,6 +176,19 @@ void __init ralink_clk_init(void)
 	ralink_clk_add("10000500.uart", 40000000);
 	ralink_clk_add("10000b00.spi", 40000000);
 	ralink_clk_add("10000c00.uartlite", 40000000);
+
+	if (IS_ENABLED(CONFIG_USB)) {
+		/*
+		 * When the CPU goes into sleep mode, the BUS clock will be too low for
+		 * USB to function properly
+		 */
+		u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
+
+		val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
+		val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
+
+		rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
+	}
 }
 
 void __init ralink_of_remap(void)
-- 
1.7.10.4

[PATCH 5/5] MIPS: ralink: mt7620: this SoC has ehci and ohci hosts

[John Crispin]

Select the the EHCI and OHCI symbols.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/ralink/Kconfig |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
index c528d0c..5f5dad2 100644
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -29,6 +29,8 @@ choice
 
 	config SOC_MT7620
 		bool "MT7620"
+		select USB_ARCH_HAS_OHCI
+		select USB_ARCH_HAS_EHCI
 
 endchoice
 
-- 
1.7.10.4

Re: [PATCH 2/5] MIPS: ralink: mt7620: add spi clock definition

[Gabor Juhos]

2013.08.08. 13:17 keltezéssel, John Crispin írta:
> The definition of the spi clock is missing.
> 
> Signed-off-by: John Crispin <blogic@openwrt.org>
> ---
>  arch/mips/ralink/mt7620.c |    1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
> index ccdec5a..769296f 100644
> --- a/arch/mips/ralink/mt7620.c
> +++ b/arch/mips/ralink/mt7620.c
> @@ -167,6 +167,7 @@ void __init ralink_clk_init(void)
>  	ralink_clk_add("cpu", cpu_rate);
>  	ralink_clk_add("10000100.timer", 40000000);
>  	ralink_clk_add("10000500.uart", 40000000);
> +	ralink_clk_add("10000b00.spi", 40000000);

Please verify this. The SPI core uses the system clock AFAIK.

-Gabor