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From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: xen-devel <xen-devel@lists.xenproject.org>,
	Keir Fraser <keir@xen.org>, Eddie Dong <eddie.dong@intel.com>,
	Jun Nakajima <jun.nakajima@intel.com>
Subject: Re: [PATCH v4 3/4] VMX: use proper instruction mnemonics if assembler supports them
Date: Mon, 26 Aug 2013 16:07:45 +0100	[thread overview]
Message-ID: <521B6F41.6090204@citrix.com> (raw)
In-Reply-To: <521B825D02000078000EE72D@nat28.tlf.novell.com>

On 26/08/2013 15:29, Jan Beulich wrote:
>>>> On 26.08.13 at 16:18, Andrew Cooper <andrew.cooper3@citrix.com> wrote:
>> On 26/08/2013 15:03, Jan Beulich wrote:
>>> +    asm volatile (
>>> +#ifdef HAVE_GAS_VMX
>>> +                   "vmread %2, %1\n\t"
>>> +#else
>>> +                   VMREAD_OPCODE MODRM_EAX_ECX
>>> +#endif
>>> +                   /* CF==1 or ZF==1 --> rc = 0 */
>>> +                   "setnbe %0"
>>> +#ifdef HAVE_GAS_VMX
>>> +                   : "=qm" (okay), "=rm" (*value)
>>> +                   : "r" (field)
>>> +#else
>>> +                   : "=qm" (okay), "=c" (*value)
>>> +                   : "a" (field)
>>> +#endif
>> From what I can work out while googling, the q constraint is equivalent
>> to the r constraint for 64bit code.
>>
>> For consistency sake, I would suggest "=rm" (okay) here
> And I'd like to keep it the way it is for generality's  sake (i.e. not
> making the code more 32-bit unclean than we need to).

Ok

>
>>> @@ -365,14 +398,22 @@ static inline void __invept(int type, u6
>>>           !cpu_has_vmx_ept_invept_single_context )
>>>          type = INVEPT_ALL_CONTEXT;
>>>  
>>> -    asm volatile ( INVEPT_OPCODE
>>> -                   MODRM_EAX_08
>>> +    asm volatile (
>>> +#ifdef HAVE_GAS_EPT
>>> +                   "invept %0, %q1\n"
>> Another stray q
> No - operand 1 is of type "int", and while the high 32 bits get
> ignored (i.e. we don't need to do any zero- or sign-extension), we
> still need to specify the 64-bit register name here. Or wait - I
> thought it would ignore the upper bits, but it's not documented to.
> In which case this involves more than just dropping the q modifier.

I was more referring to having a q in the instruction, yet an "r" in the
parameter list.  I would suggest

INV{EPT,VPID} is strictly defined to take r64 as the "type" parameter in
long mode.  Invalid/unsupported values found in this register can be
detected based on the state of EFLAGS afterwards.

Therefore, I would suggest possibly changing "int type" to "unsigned
long type" if we are going to the effort of getting this correct.  It
shouldn't make a difference currently, as all calls use appropriate
INVEPT_*_CONTEXT defines.

As for the flags, should we be including "cc" to the clobber list as
each of the VM*/INV* instructions explicitly sets the flags.  I would
hope that the toolchain is pessimistic enough to not trust the state of
the flags across some inline assembly, but I can't find any hard
information one way or another.

~Andrew

  reply	other threads:[~2013-08-26 15:07 UTC|newest]

Thread overview: 60+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-08-23 13:58 [PATCH 0/4] HVM: produce better binary code Jan Beulich
2013-08-23 14:01 ` [PATCH 1/4] VMX: streamline entry.S code Jan Beulich
2013-08-26 10:44   ` Andrew Cooper
2013-08-26 11:01     ` Jan Beulich
2013-08-26 11:48       ` Andrew Cooper
2013-08-26 13:12         ` Jan Beulich
2013-08-26 13:22           ` Andrew Cooper
2013-08-29 11:01   ` Tim Deegan
2013-08-29 12:35     ` Jan Beulich
2013-08-23 14:02 ` [PATCH 2/4] VMX: move various uses of UD2 out of fast paths Jan Beulich
2013-08-23 22:06   ` Andrew Cooper
2013-08-26  8:50     ` Jan Beulich
2013-08-26  9:07       ` Andrew Cooper
2013-08-26  8:58     ` [PATCH v2 " Jan Beulich
2013-08-26  9:09       ` Andrew Cooper
2013-08-29 11:08       ` Tim Deegan
2013-08-23 14:03 ` [PATCH 3/4] VMX: use proper instruction mnemonics if assembler supports them Jan Beulich
2013-08-24 22:18   ` Andrew Cooper
2013-08-26  9:06     ` Jan Beulich
2013-08-26  9:25       ` Andrew Cooper
2013-08-26  9:41         ` Jan Beulich
2013-08-26 10:18         ` [PATCH v3 " Jan Beulich
2013-08-26 13:05           ` Andrew Cooper
2013-08-26 13:20             ` Jan Beulich
2013-08-26 14:03             ` [PATCH v4 " Jan Beulich
2013-08-26 14:18               ` Andrew Cooper
2013-08-26 14:29                 ` Jan Beulich
2013-08-26 15:07                   ` Andrew Cooper [this message]
2013-08-26 15:10                     ` Andrew Cooper
2013-08-26 15:30                       ` Jan Beulich
2013-08-26 15:29                     ` Jan Beulich
2013-08-26 15:33                       ` Andrew Cooper
2013-08-26 15:31                 ` [PATCH v5 " Jan Beulich
2013-08-26 15:36                   ` Andrew Cooper
2013-08-29 11:47                   ` Tim Deegan
2013-08-29 12:30                     ` Jan Beulich
2013-08-29 13:11                       ` Tim Deegan
2013-08-29 13:27                         ` Jan Beulich
2013-08-29 14:02                           ` Tim Deegan
2013-08-29 12:45                     ` Jan Beulich
2013-08-29 13:19                       ` Tim Deegan
2013-08-26  9:03   ` [PATCH v2 " Jan Beulich
2013-08-23 14:04 ` [PATCH 4/4] SVM: streamline entry.S code Jan Beulich
2013-08-26 16:20   ` Andrew Cooper
2013-08-26 17:20     ` Keir Fraser
2013-08-26 17:46       ` Andrew Cooper
2013-08-26 21:47   ` Andrew Cooper
2013-08-27  7:38     ` Jan Beulich
2013-08-29 11:56   ` Tim Deegan
2013-09-04 14:39   ` Boris Ostrovsky
2013-09-04 14:50     ` Jan Beulich
2013-09-04 15:09       ` Boris Ostrovsky
2013-09-04 15:20         ` Jan Beulich
2013-09-04 16:42           ` Boris Ostrovsky
2013-09-05  7:10             ` Jan Beulich
2013-09-04 10:06 ` Ping: [PATCH 0/4] HVM: produce better binary code Jan Beulich
2013-09-04 16:16   ` Andrew Cooper
2013-09-04 16:30     ` Tim Deegan
2013-09-05  7:52       ` Jan Beulich
2013-09-05  7:58         ` Tim Deegan

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