From: Suravee Suthikulanit <suravee.suthikulpanit@amd.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: Sander Eikelenboom <linux@eikelenboom.it>,
Jacob Shin <jacob.shin@amd.com>,
xen-devel <xen-devel@lists.xenproject.org>
Subject: Re: [PATCH] AMD IOMMU: also allocate IRTEs for HPET MSI
Date: Tue, 27 Aug 2013 14:06:54 -0500 [thread overview]
Message-ID: <521CF8CE.8040307@amd.com> (raw)
In-Reply-To: <521C665302000078000EE9C1@nat28.tlf.novell.com>
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On 8/27/2013 1:41 AM, Jan Beulich wrote:
>>>> On 27.08.13 at 03:21, Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> wrote:
>> I have been trying to test out this patch. Somehow, I could not get Xen
>> boot option to exercise the code path. What boot configuration are you
>> using to test this?
> I don't have a system suitable for testing this; Sander did. The main
> requirement apart from having an IOMMU is to also have a HPET
> with at least on MSI-capable channel. Otherwise code won't get
> here. The normal flow is
>
> hpet_broadcast_init() -> hpet_fsb_cap_lookup() -> hpet_assign_irq()
> -> hpet_setup_msi_irq() -> iommu_setup_hpet_msi()
>
> Jan
Ah,ok.. I found out thatthisonly applies on the family10h system with
IOMMUdue to the check in arch/x86/time.c:_disable_pit_irq
"if (!boot_cpu_has(X86_FEATURE_ARAT))"
and the condition in arch/x86/cpu/amd.c:_init_amd()
/*
* Family 0x12 and above processors have APIC timer
* running in deep C states.
*/
if (c->x86 > 0x11)
set_bit(X86_FEATURE_ARAT, c->x86_capability);
Jan, doyou think you could also add the comment that this only
applicable on family10h?
Acked-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Thank you,
Suravee.
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next prev parent reply other threads:[~2013-08-27 19:07 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-08-26 14:20 [PATCH] AMD IOMMU: also allocate IRTEs for HPET MSI Jan Beulich
2013-08-27 1:21 ` Suravee Suthikulpanit
2013-08-27 6:41 ` Jan Beulich
2013-08-27 19:06 ` Suravee Suthikulanit [this message]
2013-08-28 7:43 ` Jan Beulich
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