* [PATCH] MIPS: Fix errata for some 1074K cores.
@ 2013-09-11 20:01 Steven J. Hill
2013-09-12 9:39 ` Paul Burton
0 siblings, 1 reply; 11+ messages in thread
From: Steven J. Hill @ 2013-09-11 20:01 UTC (permalink / raw)
To: linux-mips; +Cc: Leonid Yegoshin, ralf, Steven J. Hill
From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Fixes errata E16 for some problems on 1074K cores.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
---
arch/mips/mm/c-r4k.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index f749f68..8d3ed32 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -786,12 +786,12 @@ static inline void alias_74k_erratum(struct cpuinfo_mips *c)
* aliases. In this case it is better to treat the cache as always
* having aliases.
*/
- if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
- c->dcache.flags |= MIPS_CACHE_VTAG;
- if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
- write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
- if (((c->processor_id & 0xff00) == PRID_IMP_1074K) &&
- ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) {
+ if ((c->processor_id & 0xff00) != PRID_IMP_1074K) {
+ if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
+ c->dcache.flags |= MIPS_CACHE_VTAG;
+ if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
+ write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
+ } else if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0)) {
c->dcache.flags |= MIPS_CACHE_VTAG;
write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH] MIPS: Fix errata for some 1074K cores.
@ 2013-09-12 9:39 ` Paul Burton
0 siblings, 0 replies; 11+ messages in thread
From: Paul Burton @ 2013-09-12 9:39 UTC (permalink / raw)
To: Leonid Yegoshin; +Cc: Steven J. Hill, linux-mips, ralf
Could you expand on that please? What is errata E16, what are "some
problems" and how does this fix those problems? The commit message is
somewhat lacking...
Paul
On 11/09/13 21:01, Steven J. Hill wrote:
> From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
>
> Fixes errata E16 for some problems on 1074K cores.
>
> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
> ---
> arch/mips/mm/c-r4k.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
> index f749f68..8d3ed32 100644
> --- a/arch/mips/mm/c-r4k.c
> +++ b/arch/mips/mm/c-r4k.c
> @@ -786,12 +786,12 @@ static inline void alias_74k_erratum(struct cpuinfo_mips *c)
> * aliases. In this case it is better to treat the cache as always
> * having aliases.
> */
> - if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
> - c->dcache.flags |= MIPS_CACHE_VTAG;
> - if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
> - write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
> - if (((c->processor_id & 0xff00) == PRID_IMP_1074K) &&
> - ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) {
> + if ((c->processor_id & 0xff00) != PRID_IMP_1074K) {
> + if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
> + c->dcache.flags |= MIPS_CACHE_VTAG;
> + if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
> + write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
> + } else if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0)) {
> c->dcache.flags |= MIPS_CACHE_VTAG;
> write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
> }
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH] MIPS: Fix errata for some 1074K cores.
@ 2013-09-12 9:39 ` Paul Burton
0 siblings, 0 replies; 11+ messages in thread
From: Paul Burton @ 2013-09-12 9:39 UTC (permalink / raw)
To: Leonid Yegoshin; +Cc: Steven J. Hill, linux-mips, ralf
Could you expand on that please? What is errata E16, what are "some
problems" and how does this fix those problems? The commit message is
somewhat lacking...
Paul
On 11/09/13 21:01, Steven J. Hill wrote:
> From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
>
> Fixes errata E16 for some problems on 1074K cores.
>
> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
> ---
> arch/mips/mm/c-r4k.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
> index f749f68..8d3ed32 100644
> --- a/arch/mips/mm/c-r4k.c
> +++ b/arch/mips/mm/c-r4k.c
> @@ -786,12 +786,12 @@ static inline void alias_74k_erratum(struct cpuinfo_mips *c)
> * aliases. In this case it is better to treat the cache as always
> * having aliases.
> */
> - if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
> - c->dcache.flags |= MIPS_CACHE_VTAG;
> - if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
> - write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
> - if (((c->processor_id & 0xff00) == PRID_IMP_1074K) &&
> - ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) {
> + if ((c->processor_id & 0xff00) != PRID_IMP_1074K) {
> + if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
> + c->dcache.flags |= MIPS_CACHE_VTAG;
> + if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
> + write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
> + } else if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0)) {
> c->dcache.flags |= MIPS_CACHE_VTAG;
> write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
> }
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH] MIPS: Fix errata for some 1074K cores.
2013-09-12 9:39 ` Paul Burton
(?)
@ 2013-09-12 14:57 ` Leonid Yegoshin
2013-09-12 15:05 ` Florian Fainelli
-1 siblings, 1 reply; 11+ messages in thread
From: Leonid Yegoshin @ 2013-09-12 14:57 UTC (permalink / raw)
To: Paul Burton
Cc: Steven J. Hill, linux-mips@linux-mips.org, ralf@linux-mips.org
Treat it as is.
It is a dirty laundry of HW engineers and you may need to communicate with them or read Errata docs on CPU.
If it is about a way how it is written - ask Steven, initially it was in mainland probe code but he think it should be a separate function. I just corrected him, pointing that erratas on 74K and 1074K are different. But because he insist on having the same CPU_74K for both, so...
- Leonid.
PS. If you think the code is bad, please be specific beyond broad blame.
Paul Burton <Paul.Burton@imgtec.com> wrote:
Could you expand on that please? What is errata E16, what are "some
problems" and how does this fix those problems? The commit message is
somewhat lacking...
Paul
On 11/09/13 21:01, Steven J. Hill wrote:
> From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
>
> Fixes errata E16 for some problems on 1074K cores.
>
> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
> ---
> arch/mips/mm/c-r4k.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
> index f749f68..8d3ed32 100644
> --- a/arch/mips/mm/c-r4k.c
> +++ b/arch/mips/mm/c-r4k.c
> @@ -786,12 +786,12 @@ static inline void alias_74k_erratum(struct cpuinfo_mips *c)
> * aliases. In this case it is better to treat the cache as always
> * having aliases.
> */
> - if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
> - c->dcache.flags |= MIPS_CACHE_VTAG;
> - if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
> - write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
> - if (((c->processor_id & 0xff00) == PRID_IMP_1074K) &&
> - ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) {
> + if ((c->processor_id & 0xff00) != PRID_IMP_1074K) {
> + if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
> + c->dcache.flags |= MIPS_CACHE_VTAG;
> + if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
> + write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
> + } else if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0)) {
> c->dcache.flags |= MIPS_CACHE_VTAG;
> write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
> }
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH] MIPS: Fix errata for some 1074K cores.
2013-09-12 14:57 ` Leonid Yegoshin
@ 2013-09-12 15:05 ` Florian Fainelli
2013-09-12 15:12 ` Leonid Yegoshin
2013-09-12 15:12 ` Paul Burton
0 siblings, 2 replies; 11+ messages in thread
From: Florian Fainelli @ 2013-09-12 15:05 UTC (permalink / raw)
To: Leonid Yegoshin
Cc: Paul Burton, Steven J. Hill, linux-mips@linux-mips.org,
ralf@linux-mips.org
2013/9/12 Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>:
> Treat it as is.
>
> It is a dirty laundry of HW engineers and you may need to communicate with them or read Errata docs on CPU.
>
> If it is about a way how it is written - ask Steven, initially it was in mainland probe code but he think it should be a separate function. I just corrected him, pointing that erratas on 74K and 1074K are different. But because he insist on having the same CPU_74K for both, so...
If you take a look at another CPU company such as ARM, they provide
lengthy explanations for their various Erratas:
config PJ4B_ERRATA_4742
bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the
CPU Core to Cease Operation"
depends on CPU_PJ4B && MACH_ARMADA_370
default y
help
When coming out of either a Wait for Interrupt (WFI) or a Wait for
Event (WFE) IDLE states, a specific timing sensitivity exists between
the retiring WFI/WFE instructions and the newly issued subsequent
instructions. This sensitivity can result in a CPU hang scenario.
Workaround:
The software must insert either a Data Synchronization Barrier (DSB)
or Data Memory Barrier (DMB) command immediately after the WFI/WFE
instruction
I really think that you should aim for the same level of information
so that people know whether this is relevant for their platform,
whether they have the ECO applied etc...
--
Florian
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH] MIPS: Fix errata for some 1074K cores.
2013-09-12 15:05 ` Florian Fainelli
@ 2013-09-12 15:12 ` Leonid Yegoshin
2013-09-12 15:12 ` Paul Burton
1 sibling, 0 replies; 11+ messages in thread
From: Leonid Yegoshin @ 2013-09-12 15:12 UTC (permalink / raw)
To: Florian Fainelli
Cc: Paul Burton, Steven J. Hill, linux-mips@linux-mips.org,
ralf@linux-mips.org
Well, if you read an errata text, you probably have a big chance to stare at it trying to understand it. At least I don't and I just put that was said to me by HW team. There is no sense in discussion here because it is a part of specific core tuneup.
Florian Fainelli <f.fainelli@gmail.com> wrote:
2013/9/12 Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>:
> Treat it as is.
>
> It is a dirty laundry of HW engineers and you may need to communicate with them or read Errata docs on CPU.
>
> If it is about a way how it is written - ask Steven, initially it was in mainland probe code but he think it should be a separate function. I just corrected him, pointing that erratas on 74K and 1074K are different. But because he insist on having the same CPU_74K for both, so...
If you take a look at another CPU company such as ARM, they provide
lengthy explanations for their various Erratas:
config PJ4B_ERRATA_4742
bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the
CPU Core to Cease Operation"
depends on CPU_PJ4B && MACH_ARMADA_370
default y
help
When coming out of either a Wait for Interrupt (WFI) or a Wait for
Event (WFE) IDLE states, a specific timing sensitivity exists between
the retiring WFI/WFE instructions and the newly issued subsequent
instructions. This sensitivity can result in a CPU hang scenario.
Workaround:
The software must insert either a Data Synchronization Barrier (DSB)
or Data Memory Barrier (DMB) command immediately after the WFI/WFE
instruction
I really think that you should aim for the same level of information
so that people know whether this is relevant for their platform,
whether they have the ECO applied etc...
--
Florian
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH] MIPS: Fix errata for some 1074K cores.
2013-09-12 15:05 ` Florian Fainelli
2013-09-12 15:12 ` Leonid Yegoshin
@ 2013-09-12 15:12 ` Paul Burton
2013-09-12 15:30 ` Leonid Yegoshin
1 sibling, 1 reply; 11+ messages in thread
From: Paul Burton @ 2013-09-12 15:12 UTC (permalink / raw)
To: Florian Fainelli
Cc: Leonid Yegoshin, Steven J. Hill, linux-mips@linux-mips.org,
ralf@linux-mips.org
Agreed, my point is not about your code but your commit message. If I'm
reading a commit which works around CPU errata I should not have to go
and ask the hardware engineers or even read an errata document in order
to know what you're doing. Your commit message should explain the
errata, its effects and how your patch works around the problem.
Paul
On 12/09/13 16:05, Florian Fainelli wrote:
> 2013/9/12 Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>:
>> Treat it as is.
>>
>> It is a dirty laundry of HW engineers and you may need to communicate with them or read Errata docs on CPU.
>>
>> If it is about a way how it is written - ask Steven, initially it was in mainland probe code but he think it should be a separate function. I just corrected him, pointing that erratas on 74K and 1074K are different. But because he insist on having the same CPU_74K for both, so...
> If you take a look at another CPU company such as ARM, they provide
> lengthy explanations for their various Erratas:
>
> config PJ4B_ERRATA_4742
> bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the
> CPU Core to Cease Operation"
> depends on CPU_PJ4B && MACH_ARMADA_370
> default y
> help
> When coming out of either a Wait for Interrupt (WFI) or a Wait for
> Event (WFE) IDLE states, a specific timing sensitivity exists between
> the retiring WFI/WFE instructions and the newly issued subsequent
> instructions. This sensitivity can result in a CPU hang scenario.
> Workaround:
> The software must insert either a Data Synchronization Barrier (DSB)
> or Data Memory Barrier (DMB) command immediately after the WFI/WFE
> instruction
>
> I really think that you should aim for the same level of information
> so that people know whether this is relevant for their platform,
> whether they have the ECO applied etc...
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] MIPS: Fix errata for some 1074K cores.
2013-09-12 15:12 ` Paul Burton
@ 2013-09-12 15:30 ` Leonid Yegoshin
2013-09-12 15:50 ` Florian Fainelli
0 siblings, 1 reply; 11+ messages in thread
From: Leonid Yegoshin @ 2013-09-12 15:30 UTC (permalink / raw)
To: Paul Burton
Cc: Florian Fainelli, Steven J. Hill, linux-mips@linux-mips.org,
ralf@linux-mips.org
It is not mine, I just fixed an existent code which applies a wrong
errata to 1074K.
Errata fix did exist before me.
- Leonid.
On 09/12/2013 08:12 AM, Paul Burton wrote:
> Agreed, my point is not about your code but your commit message. If
> I'm reading a commit which works around CPU errata I should not have
> to go and ask the hardware engineers or even read an errata document
> in order to know what you're doing. Your commit message should explain
> the errata, its effects and how your patch works around the problem.
>
> Paul
>
> On 12/09/13 16:05, Florian Fainelli wrote:
>> 2013/9/12 Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>:
>>> Treat it as is.
>>>
>>> It is a dirty laundry of HW engineers and you may need to
>>> communicate with them or read Errata docs on CPU.
>>>
>>> If it is about a way how it is written - ask Steven, initially it
>>> was in mainland probe code but he think it should be a separate
>>> function. I just corrected him, pointing that erratas on 74K and
>>> 1074K are different. But because he insist on having the same
>>> CPU_74K for both, so...
>> If you take a look at another CPU company such as ARM, they provide
>> lengthy explanations for their various Erratas:
>>
>> config PJ4B_ERRATA_4742
>> bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the
>> CPU Core to Cease Operation"
>> depends on CPU_PJ4B && MACH_ARMADA_370
>> default y
>> help
>> When coming out of either a Wait for Interrupt (WFI) or a
>> Wait for
>> Event (WFE) IDLE states, a specific timing sensitivity
>> exists between
>> the retiring WFI/WFE instructions and the newly issued
>> subsequent
>> instructions. This sensitivity can result in a CPU hang
>> scenario.
>> Workaround:
>> The software must insert either a Data Synchronization
>> Barrier (DSB)
>> or Data Memory Barrier (DMB) command immediately after the
>> WFI/WFE
>> instruction
>>
>> I really think that you should aim for the same level of information
>> so that people know whether this is relevant for their platform,
>> whether they have the ECO applied etc...
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] MIPS: Fix errata for some 1074K cores.
2013-09-12 15:30 ` Leonid Yegoshin
@ 2013-09-12 15:50 ` Florian Fainelli
2013-09-12 16:02 ` Steven J. Hill
0 siblings, 1 reply; 11+ messages in thread
From: Florian Fainelli @ 2013-09-12 15:50 UTC (permalink / raw)
To: Leonid Yegoshin
Cc: Paul Burton, Steven J. Hill, linux-mips@linux-mips.org,
ralf@linux-mips.org
Hello,
2013/9/12 Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>:
> It is not mine, I just fixed an existent code which applies a wrong errata
> to 1074K.
> Errata fix did exist before me.
Are there any reasons why you cannot quote an internal note about this
errata which would give a better idea of what this code is about?
Sorry but the diff really does not help understand what is happening
without a proper explanation of why this is required. At first glance
it would like some revisions of the CPU are affected by some D$ bug?
>
> - Leonid.
>
>
>
> On 09/12/2013 08:12 AM, Paul Burton wrote:
>>
>> Agreed, my point is not about your code but your commit message. If I'm
>> reading a commit which works around CPU errata I should not have to go and
>> ask the hardware engineers or even read an errata document in order to know
>> what you're doing. Your commit message should explain the errata, its
>> effects and how your patch works around the problem.
>>
>> Paul
>>
>> On 12/09/13 16:05, Florian Fainelli wrote:
>>>
>>> 2013/9/12 Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>:
>>>>
>>>> Treat it as is.
>>>>
>>>> It is a dirty laundry of HW engineers and you may need to communicate
>>>> with them or read Errata docs on CPU.
>>>>
>>>> If it is about a way how it is written - ask Steven, initially it was in
>>>> mainland probe code but he think it should be a separate function. I just
>>>> corrected him, pointing that erratas on 74K and 1074K are different. But
>>>> because he insist on having the same CPU_74K for both, so...
>>>
>>> If you take a look at another CPU company such as ARM, they provide
>>> lengthy explanations for their various Erratas:
>>>
>>> config PJ4B_ERRATA_4742
>>> bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the
>>> CPU Core to Cease Operation"
>>> depends on CPU_PJ4B && MACH_ARMADA_370
>>> default y
>>> help
>>> When coming out of either a Wait for Interrupt (WFI) or a Wait
>>> for
>>> Event (WFE) IDLE states, a specific timing sensitivity exists
>>> between
>>> the retiring WFI/WFE instructions and the newly issued
>>> subsequent
>>> instructions. This sensitivity can result in a CPU hang
>>> scenario.
>>> Workaround:
>>> The software must insert either a Data Synchronization Barrier
>>> (DSB)
>>> or Data Memory Barrier (DMB) command immediately after the
>>> WFI/WFE
>>> instruction
>>>
>>> I really think that you should aim for the same level of information
>>> so that people know whether this is relevant for their platform,
>>> whether they have the ECO applied etc...
>>
>>
>
>
--
Florian
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] MIPS: Fix errata for some 1074K cores.
@ 2013-09-12 16:02 ` Steven J. Hill
0 siblings, 0 replies; 11+ messages in thread
From: Steven J. Hill @ 2013-09-12 16:02 UTC (permalink / raw)
To: Florian Fainelli; +Cc: Leonid Yegoshin, Paul Burton, linux-mips
On 09/12/2013 10:50 AM, Florian Fainelli wrote:
>
> Are there any reasons why you cannot quote an internal note about this
> errata which would give a better idea of what this code is about?
> Sorry but the diff really does not help understand what is happening
> without a proper explanation of why this is required. At first glance
> it would like some revisions of the CPU are affected by some D$ bug?
>
Okaaay. How about we just stop here. I posted a poor quality patch that
did not have enough information. I will post a second version that will
have the details of what E16 is and what is being fixed. This will
involve me talking to hardware engineers to get something I can put in
the patch. My sincere apologies to everyone. I will go crawl back under
my rock and finish my work for this week. You should see the corrected
version the first part of next week. Cheers.
Steve
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] MIPS: Fix errata for some 1074K cores.
@ 2013-09-12 16:02 ` Steven J. Hill
0 siblings, 0 replies; 11+ messages in thread
From: Steven J. Hill @ 2013-09-12 16:02 UTC (permalink / raw)
To: Florian Fainelli; +Cc: Leonid Yegoshin, Paul Burton, linux-mips
On 09/12/2013 10:50 AM, Florian Fainelli wrote:
>
> Are there any reasons why you cannot quote an internal note about this
> errata which would give a better idea of what this code is about?
> Sorry but the diff really does not help understand what is happening
> without a proper explanation of why this is required. At first glance
> it would like some revisions of the CPU are affected by some D$ bug?
>
Okaaay. How about we just stop here. I posted a poor quality patch that
did not have enough information. I will post a second version that will
have the details of what E16 is and what is being fixed. This will
involve me talking to hardware engineers to get something I can put in
the patch. My sincere apologies to everyone. I will go crawl back under
my rock and finish my work for this week. You should see the corrected
version the first part of next week. Cheers.
Steve
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2013-09-12 16:02 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
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2013-09-11 20:01 [PATCH] MIPS: Fix errata for some 1074K cores Steven J. Hill
2013-09-12 9:39 ` Paul Burton
2013-09-12 9:39 ` Paul Burton
2013-09-12 14:57 ` Leonid Yegoshin
2013-09-12 15:05 ` Florian Fainelli
2013-09-12 15:12 ` Leonid Yegoshin
2013-09-12 15:12 ` Paul Burton
2013-09-12 15:30 ` Leonid Yegoshin
2013-09-12 15:50 ` Florian Fainelli
2013-09-12 16:02 ` Steven J. Hill
2013-09-12 16:02 ` Steven J. Hill
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