From: leroy christophe <christophe.leroy@c-s.fr>
To: Scott Wood <scottwood@freescale.com>
Cc: linuxppc-dev@lists.ozlabs.org, Paul Mackerras <paulus@samba.org>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] powerpc 8xx: Fixing issue with CONFIG_PIN_TLB
Date: Tue, 24 Sep 2013 10:00:02 +0200 [thread overview]
Message-ID: <52414682.3010608@c-s.fr> (raw)
In-Reply-To: <1379712141.16231.36.camel@aoeu.buserror.net>
Le 20/09/2013 23:22, Scott Wood a écrit :
>>> The hardware wants to decrement; why fight it?
>> >I see your point.
>> >However it is not clear in the documentation if the decrement is done
>> >really after the update, or at xTLB interrupt. So I propose to still set
>> >the CTR ourself as described in the reference Manual and not assume that
>> >the HW decrements it.
> It says "every update" -- do you have any reason to believe that's
> wrong? It could be tested...
>
>
Ok. I just test it, and I observe the following: As we have set the
RSV4x bit, the CPU sets Mx_CTR to a value below 0x1c after each update:
* After writing entry 0x1c, Mx_CTR has value 0x1b
* After writing entry 0x1d, Mx_CTR has value 0x18
* After writing entry 0x1e, Mx_CTR has value 0x19
* After writing entry 0x1f, Mx_CTR has value 0x1a
Indeed the first version of my patch was complete, only the description
was not fully correct.
So, in order to minimise code churn, I will re-submit my initial patch
with a modified description.
Christophe
WARNING: multiple messages have this Message-ID (diff)
From: leroy christophe <christophe.leroy@c-s.fr>
To: Scott Wood <scottwood@freescale.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Paul Mackerras <paulus@samba.org>,
linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
Joakim Tjernlund <joakim.tjernlund@transmode.se>
Subject: Re: [PATCH v2] powerpc 8xx: Fixing issue with CONFIG_PIN_TLB
Date: Tue, 24 Sep 2013 10:00:02 +0200 [thread overview]
Message-ID: <52414682.3010608@c-s.fr> (raw)
In-Reply-To: <1379712141.16231.36.camel@aoeu.buserror.net>
Le 20/09/2013 23:22, Scott Wood a écrit :
>>> The hardware wants to decrement; why fight it?
>> >I see your point.
>> >However it is not clear in the documentation if the decrement is done
>> >really after the update, or at xTLB interrupt. So I propose to still set
>> >the CTR ourself as described in the reference Manual and not assume that
>> >the HW decrements it.
> It says "every update" -- do you have any reason to believe that's
> wrong? It could be tested...
>
>
Ok. I just test it, and I observe the following: As we have set the
RSV4x bit, the CPU sets Mx_CTR to a value below 0x1c after each update:
* After writing entry 0x1c, Mx_CTR has value 0x1b
* After writing entry 0x1d, Mx_CTR has value 0x18
* After writing entry 0x1e, Mx_CTR has value 0x19
* After writing entry 0x1f, Mx_CTR has value 0x1a
Indeed the first version of my patch was complete, only the description
was not fully correct.
So, in order to minimise code churn, I will re-submit my initial patch
with a modified description.
Christophe
next prev parent reply other threads:[~2013-09-24 8:00 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-12 18:25 [PATCH v2] powerpc 8xx: Fixing issue with CONFIG_PIN_TLB Christophe Leroy
2013-09-12 18:25 ` Christophe Leroy
2013-09-12 18:44 ` Scott Wood
2013-09-12 18:44 ` Scott Wood
2013-09-13 5:04 ` leroy christophe
2013-09-13 5:04 ` leroy christophe
2013-09-16 21:02 ` Scott Wood
2013-09-16 21:02 ` Scott Wood
2013-09-17 16:40 ` leroy christophe
2013-09-17 16:40 ` leroy christophe
2013-09-20 21:22 ` Scott Wood
2013-09-20 21:22 ` Scott Wood
2013-09-24 8:00 ` leroy christophe [this message]
2013-09-24 8:00 ` leroy christophe
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