From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: Guillaume Ranquet <granquet@baylibre.com>,
Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Chunfeng Yun <chunfeng.yun@mediatek.com>,
Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>
Cc: dri-devel@lists.freedesktop.org,
linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] phy: mediatek: hdmi: mt8195: fix wrong pll calculus
Date: Fri, 14 Apr 2023 12:34:35 +0200 [thread overview]
Message-ID: <52440231-bbcc-48f6-fe47-a554cade8d73@collabora.com> (raw)
In-Reply-To: <20230413-fixes-for-mt8195-hdmi-phy-v1-2-b8482458df0d@baylibre.com>
Il 13/04/23 14:46, Guillaume Ranquet ha scritto:
> The clock rate calculus in mtk_hdmi_pll_calc() was wrong when it has
> been replaced by 'div_u64'.
>
> Fix the issue by multiplying the values in the denominator instead of
> dividing them.
>
> Fixes: 45810d486bb44 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195")
> Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
> ---
> drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
> index e10da6c4147e..5e84b294a43e 100644
> --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
> +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
> @@ -271,7 +271,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw,
> * [32,24] 9bit integer, [23,0]:24bit fraction
> */
> pcw = div_u64(((u64)ns_hdmipll_ck) << PCW_DECIMAL_WIDTH,
> - da_hdmitx21_ref_ck / PLL_FBKDIV_HS3);
> + da_hdmitx21_ref_ck * PLL_FBKDIV_HS3);
How did that even work?!?!?!? Because ... it worked, I did test it. Bah!
Luck was on your side :-P
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
WARNING: multiple messages have this Message-ID (diff)
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: Guillaume Ranquet <granquet@baylibre.com>,
Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Chunfeng Yun <chunfeng.yun@mediatek.com>,
Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>
Cc: dri-devel@lists.freedesktop.org,
linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] phy: mediatek: hdmi: mt8195: fix wrong pll calculus
Date: Fri, 14 Apr 2023 12:34:35 +0200 [thread overview]
Message-ID: <52440231-bbcc-48f6-fe47-a554cade8d73@collabora.com> (raw)
In-Reply-To: <20230413-fixes-for-mt8195-hdmi-phy-v1-2-b8482458df0d@baylibre.com>
Il 13/04/23 14:46, Guillaume Ranquet ha scritto:
> The clock rate calculus in mtk_hdmi_pll_calc() was wrong when it has
> been replaced by 'div_u64'.
>
> Fix the issue by multiplying the values in the denominator instead of
> dividing them.
>
> Fixes: 45810d486bb44 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195")
> Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
> ---
> drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
> index e10da6c4147e..5e84b294a43e 100644
> --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
> +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
> @@ -271,7 +271,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw,
> * [32,24] 9bit integer, [23,0]:24bit fraction
> */
> pcw = div_u64(((u64)ns_hdmipll_ck) << PCW_DECIMAL_WIDTH,
> - da_hdmitx21_ref_ck / PLL_FBKDIV_HS3);
> + da_hdmitx21_ref_ck * PLL_FBKDIV_HS3);
How did that even work?!?!?!? Because ... it worked, I did test it. Bah!
Luck was on your side :-P
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
WARNING: multiple messages have this Message-ID (diff)
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: Guillaume Ranquet <granquet@baylibre.com>,
Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Chunfeng Yun <chunfeng.yun@mediatek.com>,
Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>
Cc: dri-devel@lists.freedesktop.org,
linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] phy: mediatek: hdmi: mt8195: fix wrong pll calculus
Date: Fri, 14 Apr 2023 12:34:35 +0200 [thread overview]
Message-ID: <52440231-bbcc-48f6-fe47-a554cade8d73@collabora.com> (raw)
In-Reply-To: <20230413-fixes-for-mt8195-hdmi-phy-v1-2-b8482458df0d@baylibre.com>
Il 13/04/23 14:46, Guillaume Ranquet ha scritto:
> The clock rate calculus in mtk_hdmi_pll_calc() was wrong when it has
> been replaced by 'div_u64'.
>
> Fix the issue by multiplying the values in the denominator instead of
> dividing them.
>
> Fixes: 45810d486bb44 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195")
> Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
> ---
> drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
> index e10da6c4147e..5e84b294a43e 100644
> --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
> +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
> @@ -271,7 +271,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw,
> * [32,24] 9bit integer, [23,0]:24bit fraction
> */
> pcw = div_u64(((u64)ns_hdmipll_ck) << PCW_DECIMAL_WIDTH,
> - da_hdmitx21_ref_ck / PLL_FBKDIV_HS3);
> + da_hdmitx21_ref_ck * PLL_FBKDIV_HS3);
How did that even work?!?!?!? Because ... it worked, I did test it. Bah!
Luck was on your side :-P
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: Guillaume Ranquet <granquet@baylibre.com>,
Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Chunfeng Yun <chunfeng.yun@mediatek.com>,
Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>
Cc: linux-phy@lists.infradead.org,
linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] phy: mediatek: hdmi: mt8195: fix wrong pll calculus
Date: Fri, 14 Apr 2023 12:34:35 +0200 [thread overview]
Message-ID: <52440231-bbcc-48f6-fe47-a554cade8d73@collabora.com> (raw)
In-Reply-To: <20230413-fixes-for-mt8195-hdmi-phy-v1-2-b8482458df0d@baylibre.com>
Il 13/04/23 14:46, Guillaume Ranquet ha scritto:
> The clock rate calculus in mtk_hdmi_pll_calc() was wrong when it has
> been replaced by 'div_u64'.
>
> Fix the issue by multiplying the values in the denominator instead of
> dividing them.
>
> Fixes: 45810d486bb44 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195")
> Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
> ---
> drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
> index e10da6c4147e..5e84b294a43e 100644
> --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
> +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
> @@ -271,7 +271,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw,
> * [32,24] 9bit integer, [23,0]:24bit fraction
> */
> pcw = div_u64(((u64)ns_hdmipll_ck) << PCW_DECIMAL_WIDTH,
> - da_hdmitx21_ref_ck / PLL_FBKDIV_HS3);
> + da_hdmitx21_ref_ck * PLL_FBKDIV_HS3);
How did that even work?!?!?!? Because ... it worked, I did test it. Bah!
Luck was on your side :-P
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
next prev parent reply other threads:[~2023-04-14 10:34 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-13 12:46 [PATCH 0/2] Fix mtk-hdmi-mt8195 unitialized variable usage and clock rate calculation Guillaume Ranquet
2023-04-13 12:46 ` Guillaume Ranquet
2023-04-13 12:46 ` Guillaume Ranquet
2023-04-13 12:46 ` Guillaume Ranquet
2023-04-13 12:46 ` [PATCH 1/2] phy: mediatek: hdmi: mt8195: fix uninitialized variable usage in pll_calc Guillaume Ranquet
2023-04-13 12:46 ` Guillaume Ranquet
2023-04-13 12:46 ` Guillaume Ranquet
2023-04-13 12:46 ` Guillaume Ranquet
2023-04-14 10:31 ` AngeloGioacchino Del Regno
2023-04-14 10:31 ` AngeloGioacchino Del Regno
2023-04-14 10:31 ` AngeloGioacchino Del Regno
2023-04-14 10:31 ` AngeloGioacchino Del Regno
2023-04-14 12:52 ` Guillaume Ranquet
2023-04-14 12:52 ` Guillaume Ranquet
2023-04-14 12:52 ` Guillaume Ranquet
2023-04-14 12:52 ` Guillaume Ranquet
2023-04-13 12:46 ` [PATCH 2/2] phy: mediatek: hdmi: mt8195: fix wrong pll calculus Guillaume Ranquet
2023-04-13 12:46 ` Guillaume Ranquet
2023-04-13 12:46 ` Guillaume Ranquet
2023-04-13 12:46 ` Guillaume Ranquet
2023-04-14 10:34 ` AngeloGioacchino Del Regno [this message]
2023-04-14 10:34 ` AngeloGioacchino Del Regno
2023-04-14 10:34 ` AngeloGioacchino Del Regno
2023-04-14 10:34 ` AngeloGioacchino Del Regno
2023-05-05 9:26 ` [PATCH 0/2] Fix mtk-hdmi-mt8195 unitialized variable usage and clock rate calculation Vinod Koul
2023-05-05 9:26 ` Vinod Koul
2023-05-05 9:26 ` Vinod Koul
2023-05-05 9:26 ` Vinod Koul
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