[Qemu-devel] [PATCH 1/5] tcg-aarch64: Update to helper_ret_*_mmu routines

[Qemu-devel] [PATCH 1/5] tcg-aarch64: Update to helper_ret_*_mmu routines

[Claudio Fontana]

Hello
Richard,

> A minimal update to use the new helpers with the return address argument.
>
> Cc: Claudio Fontana <address@hidden>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>  include/exec/exec-all.h  | 18 ------------------
>  tcg/aarch64/tcg-target.c | 28 ++++++++++++++++------------
>  2 files changed, 16 insertions(+), 30 deletions(-)
>
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index 8dd1594..3ce80d1 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -320,24 +320,6 @@ extern uintptr_t tci_tb_ptr;
>  
>  #define GETPC()  (GETRA() - GETPC_ADJ)
>  
> -/* The LDST optimizations splits code generation into fast and slow path.
> -   In some implementations, we pass the "logical" return address manually;
> -   in others, we must infer the logical return from the true return.  */
> -#if defined(CONFIG_QEMU_LDST_OPTIMIZATION) && defined(CONFIG_SOFTMMU)
> -# if defined(__aarch64__)
> -#  define GETRA_LDST(RA)  tcg_getra_ldst(RA)
> -static inline uintptr_t tcg_getra_ldst(uintptr_t ra)
> -{
> -    int32_t b;
> -    ra += 4;                    /* skip one instruction */
> -    b = *(int32_t *)ra;         /* load the branch insn */
> -    b = (b << 6) >> (6 - 2);    /* extract the displacement */
> -    ra += b;                    /* apply the displacement  */
> -    return ra;
> -}
> -# endif
> -#endif /* CONFIG_QEMU_LDST_OPTIMIZATION */
> -
>  /* ??? Delete these once they are no longer used.  */
>  bool is_tcg_gen_code(uintptr_t pc_ptr);
>  #ifdef GETRA_LDST
> diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
> index 6379df1..78e1443 100644
> --- a/tcg/aarch64/tcg-target.c
> +++ b/tcg/aarch64/tcg-target.c
> @@ -778,22 +778,24 @@ static inline void tcg_out_nop(TCGContext *s)
>  }
>  
>  #ifdef CONFIG_SOFTMMU
> -/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
> -   int mmu_idx) */
> +/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
> + *                                     int mmu_idx, uintptr_t ra)
> + */
>  static const void * const qemu_ld_helpers[4] = {
> -    helper_ldb_mmu,
> -    helper_ldw_mmu,
> -    helper_ldl_mmu,
> -    helper_ldq_mmu,
> +    helper_ret_ldub_mmu,
> +    helper_ret_lduw_mmu,
> +    helper_ret_ldul_mmu,
> +    helper_ret_ldq_mmu,
>  };
>  
> -/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
> -   uintxx_t val, int mmu_idx) */
> +/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
> + *                                     uintxx_t val, int mmu_idx, uintptr_t ra)
> + */
>  static const void * const qemu_st_helpers[4] = {
> -    helper_stb_mmu,
> -    helper_stw_mmu,
> -    helper_stl_mmu,
> -    helper_stq_mmu,
> +    helper_ret_stb_mmu,
> +    helper_ret_stw_mmu,
> +    helper_ret_stl_mmu,
> +    helper_ret_stq_mmu,
>  };
>  
>  static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
> @@ -802,6 +804,7 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, 
> TCGLabelQemuLdst *lb)
>      tcg_out_movr(s, 1, TCG_REG_X0, TCG_AREG0);
>      tcg_out_movr(s, (TARGET_LONG_BITS == 64), TCG_REG_X1, lb->addrlo_reg);
>      tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, lb->mem_index);
> +    tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_X3, (tcg_target_long)lb->raddr);
>      tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP,
>                   (tcg_target_long)qemu_ld_helpers[lb->opc & 3]);
>      tcg_out_callr(s, TCG_REG_TMP);
> @@ -822,6 +825,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, 
> TCGLabelQemuLdst *lb)
>      tcg_out_movr(s, (TARGET_LONG_BITS == 64), TCG_REG_X1, lb->addrlo_reg);
>      tcg_out_movr(s, 1, TCG_REG_X2, lb->datalo_reg);
>      tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, lb->mem_index);
> +    tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_X4, (tcg_target_long)lb->raddr);

At first
glance I
think we
should add
X4 to the
list of
restrictions
in
function
`target_parse_constraint':

tcg_regset_reset_reg(ct->u.regs,
TCG_REG_X4);

Otherwise
I am more
than happy
with the
intention
to remove
tcg_getra_ldst.

>      tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP,
>                   (tcg_target_long)qemu_st_helpers[lb->opc & 3]);
>      tcg_out_callr(s, TCG_REG_TMP);
> -- 
> 1.8.3.1
>

Claudio

Re: [Qemu-devel] [PATCH 1/5] tcg-aarch64: Update to helper_ret_*_mmu routines

[Richard Henderson]

On 10/04/2013 02:15 PM, Claudio Fontana wrote:
> At first glance I think we should add X4 to the list of restrictions in 
> function `target_parse_constraint':

No, we've consumed all of the inputs at this point.  We only
need list those registers we're going to clobber before the
inputs are consumed.


r~

Re: [Qemu-devel] [PATCH 1/5] tcg-aarch64: Update to helper_ret_*_mmu routines

[Claudio Fontana]

On 10/05/13 09:37, Richard Henderson wrote:
> On 10/04/2013 02:15 PM, Claudio Fontana wrote:
>> At first glance I think we should add X4 to the list of restrictions in 
>> function `target_parse_constraint':
> 
> No, we've consumed all of the inputs at this point.  We only
> need list those registers we're going to clobber before the
> inputs are consumed.
> 
> 
> r~
> 

Indeed. Tested with target arm, x86-64, sparc, all good.

Reviewed-by: Claudio Fontana <claudio.fontana@linaro.org>
Tested-by: Claudio Fontana <claudio.fontana@linaro.org>

[Qemu-devel] [PATCH 0/5] Remove CONFIG_QEMU_LDST_OPTIMIZATION

[Richard Henderson]

This patch set is based upon

  git://github.com/rth7680/qemu.git tcg-arm-pull

With the first patch, to convert aarch64 away from the old
ldst helpers, we wean exec-all.h from any knowledge of the
tcg backend implementation.  Which means we no longer need
to involve configure in the backend implementation either.

The structure I've chosen, a TCGBackendData structure that
is (technically) totally private to the backend, is based
on my long-term assumption that many targets would do better
with some sort of constant pool.  Or allowing ia64 to save
data with which it could produce better instruction bundling
across tcg opcodes.

That said, until there is some need for the TCGBackendData
structure to be unique, let's share as much code as we can.
Thus the two helper header files, which allow all of the
boilerplate code for ldst optimization to be shared.


r~


Richard Henderson (5):
  tcg-aarch64: Update to helper_ret_*_mmu routines
  exec: Delete is_tcg_gen_code and GETRA_EXT
  tcg: Add tcg-be-null.h
  tcg: Add tcg-be-ldst.h
  configure: Remove CONFIG_QEMU_LDST_OPTIMIZATION

 configure                       |  8 ----
 include/exec/exec-all.h         | 30 --------------
 include/exec/softmmu_template.h |  4 +-
 tcg/aarch64/tcg-target.c        | 51 +++++++++--------------
 tcg/arm/tcg-target.c            | 27 ++-----------
 tcg/i386/tcg-target.c           | 30 ++------------
 tcg/ia64/tcg-target.c           |  2 +
 tcg/mips/tcg-target.c           |  2 +
 tcg/ppc/tcg-target.c            | 28 ++-----------
 tcg/ppc64/tcg-target.c          | 26 ++----------
 tcg/s390/tcg-target.c           |  2 +
 tcg/sparc/tcg-target.c          |  2 +
 tcg/tcg-be-ldst.h               | 90 +++++++++++++++++++++++++++++++++++++++++
 tcg/tcg-be-null.h               | 43 ++++++++++++++++++++
 tcg/tcg.c                       | 15 +++----
 tcg/tcg.h                       | 31 +-------------
 tcg/tci/tcg-target.c            |  2 +
 translate-all.c                 | 12 ------
 18 files changed, 183 insertions(+), 222 deletions(-)
 create mode 100644 tcg/tcg-be-ldst.h
 create mode 100644 tcg/tcg-be-null.h

-- 
1.8.3.1

[Qemu-devel] [PATCH 1/5] tcg-aarch64: Update to helper_ret_*_mmu routines

[Richard Henderson]

A minimal update to use the new helpers with the return address argument.

Cc: Claudio Fontana <claudio.fontana@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 include/exec/exec-all.h  | 18 ------------------
 tcg/aarch64/tcg-target.c | 28 ++++++++++++++++------------
 2 files changed, 16 insertions(+), 30 deletions(-)

diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 8dd1594..3ce80d1 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -320,24 +320,6 @@ extern uintptr_t tci_tb_ptr;
 
 #define GETPC()  (GETRA() - GETPC_ADJ)
 
-/* The LDST optimizations splits code generation into fast and slow path.
-   In some implementations, we pass the "logical" return address manually;
-   in others, we must infer the logical return from the true return.  */
-#if defined(CONFIG_QEMU_LDST_OPTIMIZATION) && defined(CONFIG_SOFTMMU)
-# if defined(__aarch64__)
-#  define GETRA_LDST(RA)  tcg_getra_ldst(RA)
-static inline uintptr_t tcg_getra_ldst(uintptr_t ra)
-{
-    int32_t b;
-    ra += 4;                    /* skip one instruction */
-    b = *(int32_t *)ra;         /* load the branch insn */
-    b = (b << 6) >> (6 - 2);    /* extract the displacement */
-    ra += b;                    /* apply the displacement  */
-    return ra;
-}
-# endif
-#endif /* CONFIG_QEMU_LDST_OPTIMIZATION */
-
 /* ??? Delete these once they are no longer used.  */
 bool is_tcg_gen_code(uintptr_t pc_ptr);
 #ifdef GETRA_LDST
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 6379df1..78e1443 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -778,22 +778,24 @@ static inline void tcg_out_nop(TCGContext *s)
 }
 
 #ifdef CONFIG_SOFTMMU
-/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
-   int mmu_idx) */
+/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
+ *                                     int mmu_idx, uintptr_t ra)
+ */
 static const void * const qemu_ld_helpers[4] = {
-    helper_ldb_mmu,
-    helper_ldw_mmu,
-    helper_ldl_mmu,
-    helper_ldq_mmu,
+    helper_ret_ldub_mmu,
+    helper_ret_lduw_mmu,
+    helper_ret_ldul_mmu,
+    helper_ret_ldq_mmu,
 };
 
-/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
-   uintxx_t val, int mmu_idx) */
+/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
+ *                                     uintxx_t val, int mmu_idx, uintptr_t ra)
+ */
 static const void * const qemu_st_helpers[4] = {
-    helper_stb_mmu,
-    helper_stw_mmu,
-    helper_stl_mmu,
-    helper_stq_mmu,
+    helper_ret_stb_mmu,
+    helper_ret_stw_mmu,
+    helper_ret_stl_mmu,
+    helper_ret_stq_mmu,
 };
 
 static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
@@ -802,6 +804,7 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
     tcg_out_movr(s, 1, TCG_REG_X0, TCG_AREG0);
     tcg_out_movr(s, (TARGET_LONG_BITS == 64), TCG_REG_X1, lb->addrlo_reg);
     tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, lb->mem_index);
+    tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_X3, (tcg_target_long)lb->raddr);
     tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP,
                  (tcg_target_long)qemu_ld_helpers[lb->opc & 3]);
     tcg_out_callr(s, TCG_REG_TMP);
@@ -822,6 +825,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
     tcg_out_movr(s, (TARGET_LONG_BITS == 64), TCG_REG_X1, lb->addrlo_reg);
     tcg_out_movr(s, 1, TCG_REG_X2, lb->datalo_reg);
     tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, lb->mem_index);
+    tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_X4, (tcg_target_long)lb->raddr);
     tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP,
                  (tcg_target_long)qemu_st_helpers[lb->opc & 3]);
     tcg_out_callr(s, TCG_REG_TMP);
-- 
1.8.3.1