Re: [PATCH v2 3/3] KVM: PPC: Book3S: MMIO emulation support for little endian guests

[Cedric Le Goater <clg@fr.ibm.com>]

On 10/09/2013 10:29 AM, Alexander Graf wrote:
> 
> 
> Am 09.10.2013 um 07:59 schrieb Paul Mackerras <paulus@samba.org>:
> 
>> On Wed, Oct 09, 2013 at 01:46:29AM +0200, Alexander Graf wrote:
>>>
>>>
>>> Am 09.10.2013 um 01:31 schrieb Paul Mackerras <paulus@samba.org>:
>>>
>>>> True, until we get to POWER8 with its split little-endian support,
>>>> where instructions and data can have different endianness...
>>>
>>> How exactly does that work?
>>
>> They added an extra MSR bit called SLE which enables the split-endian
>> mode.  It's bit 5 (IBM numbering).  For backwards compatibility, the
>> LE bit controls instruction endianness, and data endianness depends on
>> LE ^ SLE, that is, with SLE = 0 things work as before.  With SLE=1 and
>> LE=0 you get little-endian data and big-endian instructions, and vice
>> versa with SLE=1 and LE=1.
> 
> So ld32 should only honor LE and get_last_inst only looks at SLE and 
> swaps even the vcpu cached version if it's set, no?
 
Here is the table (PowerISA) illustrating the endian modes for all 
combinations :

	SLE	LE	Data	Instruction

	0	0	Big	Big
	0	1	Little	Little
	1	0	Little	Big
	1	1	Big	Little


My understanding is that when reading instructions, we should test MSR[LE] 
and for data, test MSR[SLE] ^ MSR[LE].

This has to be done in conjunction with the host endian order to determine 
if we should byte-swap or not, but we can assume the host is big endian
for the moment and fix the byte-swapping later.

C.



>>
>> There is also a user accessible "mtsle" instruction that sets the
>> value of the SLE bit.  This enables programs to flip their data
>> endianness back and forth quickly, so it's usable for short
>> instruction sequences, without the need to generate instructions of
>> the opposite endianness.
>>
>> Paul.
>