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* [PATCH V2 0/4]
@ 2013-10-11  9:58 ` Joseph Lo
  0 siblings, 0 replies; 20+ messages in thread
From: Joseph Lo @ 2013-10-11  9:58 UTC (permalink / raw)
  To: Stephen Warren
  Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Joseph Lo

This series adds the LP1 support for Tegra124. (suspend to LP2 also
supported in this series)

Note:
This patch series depends on the patch series below.
* [PATCH 0/5] Tegra124 clock support
* [PATCH V2 0/6] ARM: tegra: basic support for Tegra124 SoC
* [PATCH] ARM: tegra: add clock properties for devices of Tegra124
* [PATCH] ARM: tegra: enable Tegra RTC as default for Tegra124
* [PATCH 0/4] ARM: tegra: add CPU hot-plug and idle support for Tegra124

Verified on Cardhu, Dalmore and Venice2 and with THUMB2_KERNEL as well.

V2:
* remove the patch of "enable Tegra RTC for Venice2"
* add new patch of "re-calculate the LP1 data for Tegra30/114"
* squash the 2 to 5 into patch 3/4 of this series

Joseph Lo (4):
  clk: tegra124: add suspend/resume function for tegra_cpu_car_ops
  ARM: tegra: re-calculate the LP1 data for Tegra30/114
  ARM: tegra: add LP1 support code for Tegra124
  ARM: tegra: enable LP1 suspend mode for Venice2

 arch/arm/boot/dts/tegra124-venice2.dts |  7 +++++
 arch/arm/mach-tegra/Makefile           |  1 +
 arch/arm/mach-tegra/flowctrl.c         |  2 ++
 arch/arm/mach-tegra/iomap.h            |  3 +++
 arch/arm/mach-tegra/pm.c               | 12 ++++++---
 arch/arm/mach-tegra/sleep-tegra30.S    | 49 +++++++++++++++++++++++++---------
 drivers/clk/tegra/clk-tegra124.c       | 27 +++++++++++++++++++
 7 files changed, 86 insertions(+), 15 deletions(-)

-- 
1.8.4

^ permalink raw reply	[flat|nested] 20+ messages in thread
* [PATCH V2 0/4]
@ 2013-10-11  9:58 ` Joseph Lo
  0 siblings, 0 replies; 20+ messages in thread
From: Joseph Lo @ 2013-10-11  9:58 UTC (permalink / raw)
  To: linux-arm-kernel

This series adds the LP1 support for Tegra124. (suspend to LP2 also
supported in this series)

Note:
This patch series depends on the patch series below.
* [PATCH 0/5] Tegra124 clock support
* [PATCH V2 0/6] ARM: tegra: basic support for Tegra124 SoC
* [PATCH] ARM: tegra: add clock properties for devices of Tegra124
* [PATCH] ARM: tegra: enable Tegra RTC as default for Tegra124
* [PATCH 0/4] ARM: tegra: add CPU hot-plug and idle support for Tegra124

Verified on Cardhu, Dalmore and Venice2 and with THUMB2_KERNEL as well.

V2:
* remove the patch of "enable Tegra RTC for Venice2"
* add new patch of "re-calculate the LP1 data for Tegra30/114"
* squash the 2 to 5 into patch 3/4 of this series

Joseph Lo (4):
  clk: tegra124: add suspend/resume function for tegra_cpu_car_ops
  ARM: tegra: re-calculate the LP1 data for Tegra30/114
  ARM: tegra: add LP1 support code for Tegra124
  ARM: tegra: enable LP1 suspend mode for Venice2

 arch/arm/boot/dts/tegra124-venice2.dts |  7 +++++
 arch/arm/mach-tegra/Makefile           |  1 +
 arch/arm/mach-tegra/flowctrl.c         |  2 ++
 arch/arm/mach-tegra/iomap.h            |  3 +++
 arch/arm/mach-tegra/pm.c               | 12 ++++++---
 arch/arm/mach-tegra/sleep-tegra30.S    | 49 +++++++++++++++++++++++++---------
 drivers/clk/tegra/clk-tegra124.c       | 27 +++++++++++++++++++
 7 files changed, 86 insertions(+), 15 deletions(-)

-- 
1.8.4

^ permalink raw reply	[flat|nested] 20+ messages in thread
* [PATCH V2 1/4] clk: tegra124: add suspend/resume function for tegra_cpu_car_ops
  2013-10-11  9:58 ` Joseph Lo
@ 2013-10-11  9:58     ` Joseph Lo
  -1 siblings, 0 replies; 20+ messages in thread
From: Joseph Lo @ 2013-10-11  9:58 UTC (permalink / raw)
  To: Stephen Warren
  Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Joseph Lo,
	Mike Turquette

Adding suspend/resume function for tegra_cpu_car_ops. We only save and
restore the setting of the clock of CoreSight. Other clocks still need
to be taken care by clock driver.

Cc: Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Acked-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
V2:
* no change
---
 drivers/clk/tegra/clk-tegra124.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index c1c9330..66eb1f8a 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -28,6 +28,7 @@
 #include "clk.h"
 #include "clk-id.h"
 
+#define CLK_SOURCE_CSITE 0x1d4
 #define CLK_SOURCE_EMC 0x19c
 #define CLK_SOURCE_XUSB_SS_SRC 0x610
 
@@ -109,6 +110,12 @@
 /* Tegra CPU clock and reset control regs */
 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS	0x470
 
+#ifdef CONFIG_PM_SLEEP
+static struct cpu_clk_suspend_context {
+	u32 clk_csite_src;
+} tegra124_cpu_clk_sctx;
+#endif
+
 static void __iomem *clk_base;
 static void __iomem *pmc_base;
 
@@ -1139,9 +1146,29 @@ static void tegra124_disable_cpu_clock(u32 cpu)
 	/* flow controller would take care in the power sequence. */
 }
 
+#ifdef CONFIG_PM_SLEEP
+static void tegra124_cpu_clock_suspend(void)
+{
+	/* switch coresite to clk_m, save off original source */
+	tegra124_cpu_clk_sctx.clk_csite_src =
+				readl(clk_base + CLK_SOURCE_CSITE);
+	writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
+}
+
+static void tegra124_cpu_clock_resume(void)
+{
+	writel(tegra124_cpu_clk_sctx.clk_csite_src,
+				clk_base + CLK_SOURCE_CSITE);
+}
+#endif
+
 static struct tegra_cpu_car_ops tegra124_cpu_car_ops = {
 	.wait_for_reset	= tegra124_wait_cpu_in_reset,
 	.disable_clock	= tegra124_disable_cpu_clock,
+#ifdef CONFIG_PM_SLEEP
+	.suspend	= tegra124_cpu_clock_suspend,
+	.resume		= tegra124_cpu_clock_resume,
+#endif
 };
 
 static const struct of_device_id pmc_match[] __initconst = {
-- 
1.8.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH V2 1/4] clk: tegra124: add suspend/resume function for tegra_cpu_car_ops
@ 2013-10-11  9:58     ` Joseph Lo
  0 siblings, 0 replies; 20+ messages in thread
From: Joseph Lo @ 2013-10-11  9:58 UTC (permalink / raw)
  To: linux-arm-kernel

Adding suspend/resume function for tegra_cpu_car_ops. We only save and
restore the setting of the clock of CoreSight. Other clocks still need
to be taken care by clock driver.

Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
---
V2:
* no change
---
 drivers/clk/tegra/clk-tegra124.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index c1c9330..66eb1f8a 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -28,6 +28,7 @@
 #include "clk.h"
 #include "clk-id.h"
 
+#define CLK_SOURCE_CSITE 0x1d4
 #define CLK_SOURCE_EMC 0x19c
 #define CLK_SOURCE_XUSB_SS_SRC 0x610
 
@@ -109,6 +110,12 @@
 /* Tegra CPU clock and reset control regs */
 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS	0x470
 
+#ifdef CONFIG_PM_SLEEP
+static struct cpu_clk_suspend_context {
+	u32 clk_csite_src;
+} tegra124_cpu_clk_sctx;
+#endif
+
 static void __iomem *clk_base;
 static void __iomem *pmc_base;
 
@@ -1139,9 +1146,29 @@ static void tegra124_disable_cpu_clock(u32 cpu)
 	/* flow controller would take care in the power sequence. */
 }
 
+#ifdef CONFIG_PM_SLEEP
+static void tegra124_cpu_clock_suspend(void)
+{
+	/* switch coresite to clk_m, save off original source */
+	tegra124_cpu_clk_sctx.clk_csite_src =
+				readl(clk_base + CLK_SOURCE_CSITE);
+	writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
+}
+
+static void tegra124_cpu_clock_resume(void)
+{
+	writel(tegra124_cpu_clk_sctx.clk_csite_src,
+				clk_base + CLK_SOURCE_CSITE);
+}
+#endif
+
 static struct tegra_cpu_car_ops tegra124_cpu_car_ops = {
 	.wait_for_reset	= tegra124_wait_cpu_in_reset,
 	.disable_clock	= tegra124_disable_cpu_clock,
+#ifdef CONFIG_PM_SLEEP
+	.suspend	= tegra124_cpu_clock_suspend,
+	.resume		= tegra124_cpu_clock_resume,
+#endif
 };
 
 static const struct of_device_id pmc_match[] __initconst = {
-- 
1.8.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH V2 2/4] ARM: tegra: re-calculate the LP1 data for Tegra30/114
  2013-10-11  9:58 ` Joseph Lo
@ 2013-10-11  9:58     ` Joseph Lo
  -1 siblings, 0 replies; 20+ messages in thread
From: Joseph Lo @ 2013-10-11  9:58 UTC (permalink / raw)
  To: Stephen Warren
  Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Joseph Lo

This patch re-calculates the LP1 data of tegra30/114_sdram_pad_address
to base on its label not rely on others. This can make easier to
maintain if some other Tegra chips keep re-using these codes in the
future. And change the name of tegra30_sdram_pad_save to
tegra_sdram_pad_save to make it more common to other chips.

Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
V2:
* new in this series
---
 arch/arm/mach-tegra/sleep-tegra30.S | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index c6fc15c..7c529a1 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -383,7 +383,7 @@ _pll_m_c_x_done:
 	add	r1, r1, #LOCK_DELAY
 	wait_until r1, r7, r3
 
-	adr	r5, tegra30_sdram_pad_save
+	adr	r5, tegra_sdram_pad_save
 
 	ldr	r4, [r5, #0x18]		@ restore CLK_SOURCE_MSELECT
 	str	r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
@@ -538,6 +538,7 @@ tegra30_sdram_pad_address:
 	.word	TEGRA_PMC_BASE + PMC_IO_DPD_STATUS			@0x14
 	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT	@0x18
 	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST		@0x1c
+tegra30_sdram_pad_address_end:
 
 tegra114_sdram_pad_address:
 	.word	TEGRA_EMC0_BASE + EMC_CFG				@0x0
@@ -553,16 +554,17 @@ tegra114_sdram_pad_address:
 	.word	TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL			@0x28
 	.word	TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL			@0x2c
 	.word	TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2			@0x30
+tegra114_sdram_pad_adress_end:
 
 tegra30_sdram_pad_size:
-	.word	tegra114_sdram_pad_address - tegra30_sdram_pad_address
+	.word	tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
 
 tegra114_sdram_pad_size:
-	.word	tegra30_sdram_pad_size - tegra114_sdram_pad_address
+	.word	tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address
 
-	.type	tegra30_sdram_pad_save, %object
-tegra30_sdram_pad_save:
-	.rept (tegra30_sdram_pad_size - tegra114_sdram_pad_address) / 4
+	.type	tegra_sdram_pad_save, %object
+tegra_sdram_pad_save:
+	.rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4
 	.long	0
 	.endr
 
@@ -693,7 +695,7 @@ halted:
  */
 tegra30_sdram_self_refresh:
 
-	adr	r8, tegra30_sdram_pad_save
+	adr	r8, tegra_sdram_pad_save
 	tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
 	cmp	r10, #TEGRA30
 	adreq	r2, tegra30_sdram_pad_address
-- 
1.8.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH V2 2/4] ARM: tegra: re-calculate the LP1 data for Tegra30/114
@ 2013-10-11  9:58     ` Joseph Lo
  0 siblings, 0 replies; 20+ messages in thread
From: Joseph Lo @ 2013-10-11  9:58 UTC (permalink / raw)
  To: linux-arm-kernel

This patch re-calculates the LP1 data of tegra30/114_sdram_pad_address
to base on its label not rely on others. This can make easier to
maintain if some other Tegra chips keep re-using these codes in the
future. And change the name of tegra30_sdram_pad_save to
tegra_sdram_pad_save to make it more common to other chips.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
V2:
* new in this series
---
 arch/arm/mach-tegra/sleep-tegra30.S | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index c6fc15c..7c529a1 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -383,7 +383,7 @@ _pll_m_c_x_done:
 	add	r1, r1, #LOCK_DELAY
 	wait_until r1, r7, r3
 
-	adr	r5, tegra30_sdram_pad_save
+	adr	r5, tegra_sdram_pad_save
 
 	ldr	r4, [r5, #0x18]		@ restore CLK_SOURCE_MSELECT
 	str	r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
@@ -538,6 +538,7 @@ tegra30_sdram_pad_address:
 	.word	TEGRA_PMC_BASE + PMC_IO_DPD_STATUS			@0x14
 	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT	@0x18
 	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST		@0x1c
+tegra30_sdram_pad_address_end:
 
 tegra114_sdram_pad_address:
 	.word	TEGRA_EMC0_BASE + EMC_CFG				@0x0
@@ -553,16 +554,17 @@ tegra114_sdram_pad_address:
 	.word	TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL			@0x28
 	.word	TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL			@0x2c
 	.word	TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2			@0x30
+tegra114_sdram_pad_adress_end:
 
 tegra30_sdram_pad_size:
-	.word	tegra114_sdram_pad_address - tegra30_sdram_pad_address
+	.word	tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
 
 tegra114_sdram_pad_size:
-	.word	tegra30_sdram_pad_size - tegra114_sdram_pad_address
+	.word	tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address
 
-	.type	tegra30_sdram_pad_save, %object
-tegra30_sdram_pad_save:
-	.rept (tegra30_sdram_pad_size - tegra114_sdram_pad_address) / 4
+	.type	tegra_sdram_pad_save, %object
+tegra_sdram_pad_save:
+	.rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4
 	.long	0
 	.endr
 
@@ -693,7 +695,7 @@ halted:
  */
 tegra30_sdram_self_refresh:
 
-	adr	r8, tegra30_sdram_pad_save
+	adr	r8, tegra_sdram_pad_save
 	tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
 	cmp	r10, #TEGRA30
 	adreq	r2, tegra30_sdram_pad_address
-- 
1.8.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH V2 3/4] ARM: tegra: add LP1 support code for Tegra124
  2013-10-11  9:58 ` Joseph Lo
@ 2013-10-11  9:58     ` Joseph Lo
  -1 siblings, 0 replies; 20+ messages in thread
From: Joseph Lo @ 2013-10-11  9:58 UTC (permalink / raw)
  To: Stephen Warren
  Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Joseph Lo

The LP1 suspend procedure is the same with Tegra30 and Tegra114. Just
need to update the difference of the register address, then we can
continue to share the code.

Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
V2:
* squash from 2/7 to 5/7 in V1
---
 arch/arm/mach-tegra/Makefile        |  1 +
 arch/arm/mach-tegra/flowctrl.c      |  2 ++
 arch/arm/mach-tegra/iomap.h         |  3 +++
 arch/arm/mach-tegra/pm.c            | 12 +++++++++---
 arch/arm/mach-tegra/sleep-tegra30.S | 33 ++++++++++++++++++++++++++++-----
 5 files changed, 43 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index de3748e..019bb17 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -36,6 +36,7 @@ ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= cpuidle-tegra114.o
 endif
 obj-$(CONFIG_ARCH_TEGRA_124_SOC)	+= sleep-tegra30.o
+obj-$(CONFIG_ARCH_TEGRA_124_SOC)	+= pm-tegra30.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_124_SOC)	+= cpuidle-tegra114.o
 endif
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
index 5348543..ce8ab8a 100644
--- a/arch/arm/mach-tegra/flowctrl.c
+++ b/arch/arm/mach-tegra/flowctrl.c
@@ -87,6 +87,7 @@ void flowctrl_cpu_suspend_enter(unsigned int cpuid)
 		break;
 	case TEGRA30:
 	case TEGRA114:
+	case TEGRA124:
 		/* clear wfe bitmap */
 		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
 		/* clear wfi bitmap */
@@ -125,6 +126,7 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid)
 		break;
 	case TEGRA30:
 	case TEGRA114:
+	case TEGRA124:
 		/* clear wfe bitmap */
 		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
 		/* clear wfi bitmap */
diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index cbee57f..26b1c2a 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -105,6 +105,9 @@
 #define TEGRA_EMC1_BASE			0x7001A800
 #define TEGRA_EMC1_SIZE			SZ_2K
 
+#define TEGRA124_EMC_BASE		0x7001B000
+#define TEGRA124_EMC_SIZE		SZ_2K
+
 #define TEGRA_CSITE_BASE		0x70040000
 #define TEGRA_CSITE_SIZE		SZ_256K
 
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 36ed88a..4ae0286 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -59,8 +59,10 @@ static void tegra_tear_down_cpu_init(void)
 		break;
 	case TEGRA30:
 	case TEGRA114:
+	case TEGRA124:
 		if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
-		    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
+		    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
+		    IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
 			tegra_tear_down_cpu = tegra30_tear_down_cpu;
 		break;
 	}
@@ -216,8 +218,10 @@ static bool tegra_lp1_iram_hook(void)
 		break;
 	case TEGRA30:
 	case TEGRA114:
+	case TEGRA124:
 		if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
-		    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
+		    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
+		    IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
 			tegra30_lp1_iram_hook();
 		break;
 	default:
@@ -244,8 +248,10 @@ static bool tegra_sleep_core_init(void)
 		break;
 	case TEGRA30:
 	case TEGRA114:
+	case TEGRA124:
 		if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
-		    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
+		    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
+		    IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
 			tegra30_sleep_core_init();
 		break;
 	default:
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index 7c529a1..b16d4a57 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -408,8 +408,12 @@ _pll_m_c_x_done:
 	cmp	r10, #TEGRA30
 	movweq	r0, #:lower16:TEGRA_EMC_BASE	@ r0 reserved for emc base
 	movteq	r0, #:upper16:TEGRA_EMC_BASE
-	movwne	r0, #:lower16:TEGRA_EMC0_BASE
-	movtne	r0, #:upper16:TEGRA_EMC0_BASE
+	cmp	r10, #TEGRA114
+	movweq	r0, #:lower16:TEGRA_EMC0_BASE
+	movteq	r0, #:upper16:TEGRA_EMC0_BASE
+	cmp	r10, #TEGRA124
+	movweq	r0, #:lower16:TEGRA124_EMC_BASE
+	movteq	r0, #:upper16:TEGRA124_EMC_BASE
 
 exit_self_refresh:
 	ldr	r1, [r5, #0xC]		@ restore EMC_XM2VTTGENPADCTRL
@@ -556,6 +560,17 @@ tegra114_sdram_pad_address:
 	.word	TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2			@0x30
 tegra114_sdram_pad_adress_end:
 
+tegra124_sdram_pad_address:
+	.word	TEGRA124_EMC_BASE + EMC_CFG				@0x0
+	.word	TEGRA124_EMC_BASE + EMC_ZCAL_INTERVAL			@0x4
+	.word	TEGRA124_EMC_BASE + EMC_AUTO_CAL_INTERVAL		@0x8
+	.word	TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL		@0xc
+	.word	TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL2		@0x10
+	.word	TEGRA_PMC_BASE + PMC_IO_DPD_STATUS			@0x14
+	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT	@0x18
+	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST		@0x1c
+tegra124_sdram_pad_address_end:
+
 tegra30_sdram_pad_size:
 	.word	tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
 
@@ -700,8 +715,13 @@ tegra30_sdram_self_refresh:
 	cmp	r10, #TEGRA30
 	adreq	r2, tegra30_sdram_pad_address
 	ldreq	r3, tegra30_sdram_pad_size
-	adrne	r2, tegra114_sdram_pad_address
-	ldrne	r3, tegra114_sdram_pad_size
+	cmp	r10, #TEGRA114
+	adreq	r2, tegra114_sdram_pad_address
+	ldreq	r3, tegra114_sdram_pad_size
+	cmp	r10, #TEGRA124
+	adreq	r2, tegra124_sdram_pad_address
+	ldreq	r3, tegra30_sdram_pad_size
+
 	mov	r9, #0
 
 padsave:
@@ -719,7 +739,10 @@ padsave_done:
 
 	cmp	r10, #TEGRA30
 	ldreq	r0, =TEGRA_EMC_BASE	@ r0 reserved for emc base addr
-	ldrne	r0, =TEGRA_EMC0_BASE
+	cmp	r10, #TEGRA114
+	ldreq	r0, =TEGRA_EMC0_BASE
+	cmp	r10, #TEGRA124
+	ldreq	r0, =TEGRA124_EMC_BASE
 
 enter_self_refresh:
 	cmp	r10, #TEGRA30
-- 
1.8.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH V2 3/4] ARM: tegra: add LP1 support code for Tegra124
@ 2013-10-11  9:58     ` Joseph Lo
  0 siblings, 0 replies; 20+ messages in thread
From: Joseph Lo @ 2013-10-11  9:58 UTC (permalink / raw)
  To: linux-arm-kernel

The LP1 suspend procedure is the same with Tegra30 and Tegra114. Just
need to update the difference of the register address, then we can
continue to share the code.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
V2:
* squash from 2/7 to 5/7 in V1
---
 arch/arm/mach-tegra/Makefile        |  1 +
 arch/arm/mach-tegra/flowctrl.c      |  2 ++
 arch/arm/mach-tegra/iomap.h         |  3 +++
 arch/arm/mach-tegra/pm.c            | 12 +++++++++---
 arch/arm/mach-tegra/sleep-tegra30.S | 33 ++++++++++++++++++++++++++++-----
 5 files changed, 43 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index de3748e..019bb17 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -36,6 +36,7 @@ ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= cpuidle-tegra114.o
 endif
 obj-$(CONFIG_ARCH_TEGRA_124_SOC)	+= sleep-tegra30.o
+obj-$(CONFIG_ARCH_TEGRA_124_SOC)	+= pm-tegra30.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_124_SOC)	+= cpuidle-tegra114.o
 endif
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
index 5348543..ce8ab8a 100644
--- a/arch/arm/mach-tegra/flowctrl.c
+++ b/arch/arm/mach-tegra/flowctrl.c
@@ -87,6 +87,7 @@ void flowctrl_cpu_suspend_enter(unsigned int cpuid)
 		break;
 	case TEGRA30:
 	case TEGRA114:
+	case TEGRA124:
 		/* clear wfe bitmap */
 		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
 		/* clear wfi bitmap */
@@ -125,6 +126,7 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid)
 		break;
 	case TEGRA30:
 	case TEGRA114:
+	case TEGRA124:
 		/* clear wfe bitmap */
 		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
 		/* clear wfi bitmap */
diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index cbee57f..26b1c2a 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -105,6 +105,9 @@
 #define TEGRA_EMC1_BASE			0x7001A800
 #define TEGRA_EMC1_SIZE			SZ_2K
 
+#define TEGRA124_EMC_BASE		0x7001B000
+#define TEGRA124_EMC_SIZE		SZ_2K
+
 #define TEGRA_CSITE_BASE		0x70040000
 #define TEGRA_CSITE_SIZE		SZ_256K
 
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 36ed88a..4ae0286 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -59,8 +59,10 @@ static void tegra_tear_down_cpu_init(void)
 		break;
 	case TEGRA30:
 	case TEGRA114:
+	case TEGRA124:
 		if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
-		    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
+		    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
+		    IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
 			tegra_tear_down_cpu = tegra30_tear_down_cpu;
 		break;
 	}
@@ -216,8 +218,10 @@ static bool tegra_lp1_iram_hook(void)
 		break;
 	case TEGRA30:
 	case TEGRA114:
+	case TEGRA124:
 		if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
-		    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
+		    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
+		    IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
 			tegra30_lp1_iram_hook();
 		break;
 	default:
@@ -244,8 +248,10 @@ static bool tegra_sleep_core_init(void)
 		break;
 	case TEGRA30:
 	case TEGRA114:
+	case TEGRA124:
 		if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
-		    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
+		    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
+		    IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
 			tegra30_sleep_core_init();
 		break;
 	default:
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index 7c529a1..b16d4a57 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -408,8 +408,12 @@ _pll_m_c_x_done:
 	cmp	r10, #TEGRA30
 	movweq	r0, #:lower16:TEGRA_EMC_BASE	@ r0 reserved for emc base
 	movteq	r0, #:upper16:TEGRA_EMC_BASE
-	movwne	r0, #:lower16:TEGRA_EMC0_BASE
-	movtne	r0, #:upper16:TEGRA_EMC0_BASE
+	cmp	r10, #TEGRA114
+	movweq	r0, #:lower16:TEGRA_EMC0_BASE
+	movteq	r0, #:upper16:TEGRA_EMC0_BASE
+	cmp	r10, #TEGRA124
+	movweq	r0, #:lower16:TEGRA124_EMC_BASE
+	movteq	r0, #:upper16:TEGRA124_EMC_BASE
 
 exit_self_refresh:
 	ldr	r1, [r5, #0xC]		@ restore EMC_XM2VTTGENPADCTRL
@@ -556,6 +560,17 @@ tegra114_sdram_pad_address:
 	.word	TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2			@0x30
 tegra114_sdram_pad_adress_end:
 
+tegra124_sdram_pad_address:
+	.word	TEGRA124_EMC_BASE + EMC_CFG				@0x0
+	.word	TEGRA124_EMC_BASE + EMC_ZCAL_INTERVAL			@0x4
+	.word	TEGRA124_EMC_BASE + EMC_AUTO_CAL_INTERVAL		@0x8
+	.word	TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL		@0xc
+	.word	TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL2		@0x10
+	.word	TEGRA_PMC_BASE + PMC_IO_DPD_STATUS			@0x14
+	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT	@0x18
+	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST		@0x1c
+tegra124_sdram_pad_address_end:
+
 tegra30_sdram_pad_size:
 	.word	tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
 
@@ -700,8 +715,13 @@ tegra30_sdram_self_refresh:
 	cmp	r10, #TEGRA30
 	adreq	r2, tegra30_sdram_pad_address
 	ldreq	r3, tegra30_sdram_pad_size
-	adrne	r2, tegra114_sdram_pad_address
-	ldrne	r3, tegra114_sdram_pad_size
+	cmp	r10, #TEGRA114
+	adreq	r2, tegra114_sdram_pad_address
+	ldreq	r3, tegra114_sdram_pad_size
+	cmp	r10, #TEGRA124
+	adreq	r2, tegra124_sdram_pad_address
+	ldreq	r3, tegra30_sdram_pad_size
+
 	mov	r9, #0
 
 padsave:
@@ -719,7 +739,10 @@ padsave_done:
 
 	cmp	r10, #TEGRA30
 	ldreq	r0, =TEGRA_EMC_BASE	@ r0 reserved for emc base addr
-	ldrne	r0, =TEGRA_EMC0_BASE
+	cmp	r10, #TEGRA114
+	ldreq	r0, =TEGRA_EMC0_BASE
+	cmp	r10, #TEGRA124
+	ldreq	r0, =TEGRA124_EMC_BASE
 
 enter_self_refresh:
 	cmp	r10, #TEGRA30
-- 
1.8.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH V2 4/4] ARM: tegra: enable LP1 suspend mode for Venice2
  2013-10-11  9:58 ` Joseph Lo
@ 2013-10-11  9:58     ` Joseph Lo
  -1 siblings, 0 replies; 20+ messages in thread
From: Joseph Lo @ 2013-10-11  9:58 UTC (permalink / raw)
  To: Stephen Warren
  Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Joseph Lo

Enable LP1 suspend mode for Tegra124 Venice2 board.

Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
V2:
* no change
---
 arch/arm/boot/dts/tegra124-venice2.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index 5859ec2..a0b0283 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -16,6 +16,13 @@
 
 	pmc@7000e400 {
 		nvidia,invert-interrupt;
+		nvidia,suspend-mode = <1>;
+		nvidia,cpu-pwr-good-time = <500>;
+		nvidia,cpu-pwr-off-time = <300>;
+		nvidia,core-pwr-good-time = <641 3845>;
+		nvidia,core-pwr-off-time = <61036>;
+		nvidia,core-power-req-active-high;
+		nvidia,sys-clock-req-active-high;
 	};
 
 	clocks {
-- 
1.8.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH V2 4/4] ARM: tegra: enable LP1 suspend mode for Venice2
@ 2013-10-11  9:58     ` Joseph Lo
  0 siblings, 0 replies; 20+ messages in thread
From: Joseph Lo @ 2013-10-11  9:58 UTC (permalink / raw)
  To: linux-arm-kernel

Enable LP1 suspend mode for Tegra124 Venice2 board.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
V2:
* no change
---
 arch/arm/boot/dts/tegra124-venice2.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index 5859ec2..a0b0283 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -16,6 +16,13 @@
 
 	pmc at 7000e400 {
 		nvidia,invert-interrupt;
+		nvidia,suspend-mode = <1>;
+		nvidia,cpu-pwr-good-time = <500>;
+		nvidia,cpu-pwr-off-time = <300>;
+		nvidia,core-pwr-good-time = <641 3845>;
+		nvidia,core-pwr-off-time = <61036>;
+		nvidia,core-power-req-active-high;
+		nvidia,sys-clock-req-active-high;
 	};
 
 	clocks {
-- 
1.8.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread
* Re: [PATCH V2 0/4]
  2013-10-11  9:58 ` Joseph Lo
@ 2013-10-11 18:40     ` Stephen Warren
  -1 siblings, 0 replies; 20+ messages in thread
From: Stephen Warren @ 2013-10-11 18:40 UTC (permalink / raw)
  To: Joseph Lo
  Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r

On 10/11/2013 03:58 AM, Joseph Lo wrote:
> This series adds the LP1 support for Tegra124. (suspend to LP2 also
> supported in this series)
> 
> Note:
> This patch series depends on the patch series below.
> * [PATCH 0/5] Tegra124 clock support
> * [PATCH V2 0/6] ARM: tegra: basic support for Tegra124 SoC
> * [PATCH] ARM: tegra: add clock properties for devices of Tegra124
> * [PATCH] ARM: tegra: enable Tegra RTC as default for Tegra124
> * [PATCH 0/4] ARM: tegra: add CPU hot-plug and idle support for Tegra124
> 
> Verified on Cardhu, Dalmore and Venice2 and with THUMB2_KERNEL as well.

I have applied patches 2-3 to Tegra's for-3.13/soc branch, and patch 4
to Tegra's for-3.13/dt branch.

I have not applied patch 1, since that's a clock driver change. Please
work with Mike and/or Peter to send that patch through the clock tree.
In general, if there aren't any compile-time or run-time dependencies
(for existing features, not new ones) between patches, patches for
different subsystems should be sent separately, rather than as a
combined series.

Note that "[PATCH] ARM: tegra: add clock properties for devices of
Tegra124" is not yet applied; I'm waiting for Peter's Tegra124 clock
series to be finalized before applying that. There's no compile-time
dependency here, and the patch only enables new features without
breaking existing ones, so there's no bisection issue here.

^ permalink raw reply	[flat|nested] 20+ messages in thread
* [PATCH V2 0/4]
@ 2013-10-11 18:40     ` Stephen Warren
  0 siblings, 0 replies; 20+ messages in thread
From: Stephen Warren @ 2013-10-11 18:40 UTC (permalink / raw)
  To: linux-arm-kernel

On 10/11/2013 03:58 AM, Joseph Lo wrote:
> This series adds the LP1 support for Tegra124. (suspend to LP2 also
> supported in this series)
> 
> Note:
> This patch series depends on the patch series below.
> * [PATCH 0/5] Tegra124 clock support
> * [PATCH V2 0/6] ARM: tegra: basic support for Tegra124 SoC
> * [PATCH] ARM: tegra: add clock properties for devices of Tegra124
> * [PATCH] ARM: tegra: enable Tegra RTC as default for Tegra124
> * [PATCH 0/4] ARM: tegra: add CPU hot-plug and idle support for Tegra124
> 
> Verified on Cardhu, Dalmore and Venice2 and with THUMB2_KERNEL as well.

I have applied patches 2-3 to Tegra's for-3.13/soc branch, and patch 4
to Tegra's for-3.13/dt branch.

I have not applied patch 1, since that's a clock driver change. Please
work with Mike and/or Peter to send that patch through the clock tree.
In general, if there aren't any compile-time or run-time dependencies
(for existing features, not new ones) between patches, patches for
different subsystems should be sent separately, rather than as a
combined series.

Note that "[PATCH] ARM: tegra: add clock properties for devices of
Tegra124" is not yet applied; I'm waiting for Peter's Tegra124 clock
series to be finalized before applying that. There's no compile-time
dependency here, and the patch only enables new features without
breaking existing ones, so there's no bisection issue here.

^ permalink raw reply	[flat|nested] 20+ messages in thread
* [PATCH v2 0/4]
@ 2013-11-20  0:43 Murali Karicheri
  2013-11-20  0:45 ` Karicheri, Muralidharan
  0 siblings, 1 reply; 20+ messages in thread
From: Murali Karicheri @ 2013-11-20  0:43 UTC (permalink / raw)
  To: linux-arm-kernel

This patch series add a K2HK (K2 Hawking/Kepler) EVM
dts file and make some updates to the existing dts
files and Keystone PLL clk driver.

Murali Karicheri (4):
  clk: keystone: use clkod register bits for postdiv
  keystone: dts: add a k2hk-evm specific dts file
  keystone: dts: fix typo in the ddr3 pllclk node name
  keystone: dts: add paclk divider clock node

 .../devicetree/bindings/clock/keystone-pll.txt     |    8 +--
 arch/arm/boot/dts/k2hk-evm.dts                     |   55 ++++++++++++++++++++
 arch/arm/boot/dts/keystone-clocks.dtsi             |   36 ++++++-------
 arch/arm/boot/dts/{keystone.dts => keystone.dtsi}  |    2 -
 drivers/clk/keystone/pll.c                         |   24 +++++++--
 5 files changed, 96 insertions(+), 29 deletions(-)
 create mode 100644 arch/arm/boot/dts/k2hk-evm.dts
 rename arch/arm/boot/dts/{keystone.dts => keystone.dtsi} (98%)

-- 
1.7.9.5

^ permalink raw reply	[flat|nested] 20+ messages in thread
* [PATCH v2 0/4]
  2013-11-20  0:43 [PATCH v2 0/4] Murali Karicheri
@ 2013-11-20  0:45 ` Karicheri, Muralidharan
  0 siblings, 0 replies; 20+ messages in thread
From: Karicheri, Muralidharan @ 2013-11-20  0:45 UTC (permalink / raw)
  To: linux-arm-kernel

>> -----Original Message-----
>> From: Karicheri, Muralidharan
>> Sent: Tuesday, November 19, 2013 7:43 PM
>> To: linux-arm-kernel at lists.infradead.org; mturquette at linaro.org; Shilimkar, Santosh; linux-
>> keystone at list.ti.com - Linux developers for Keystone family of devices (May contain non-
>> TIers)
>> Cc: Karicheri, Muralidharan
>> Subject: [PATCH v2 0/4]
>> 
>> This patch series add a K2HK (K2 Hawking/Kepler) EVM dts file and make some updates to
>> the existing dts files and Keystone PLL clk driver.
>> 
>> Murali Karicheri (4):
>>   clk: keystone: use clkod register bits for postdiv
>>   keystone: dts: add a k2hk-evm specific dts file
>>   keystone: dts: fix typo in the ddr3 pllclk node name
>>   keystone: dts: add paclk divider clock node
>> 
>>  .../devicetree/bindings/clock/keystone-pll.txt     |    8 +--
>>  arch/arm/boot/dts/k2hk-evm.dts                     |   55 ++++++++++++++++++++
>>  arch/arm/boot/dts/keystone-clocks.dtsi             |   36 ++++++-------
>>  arch/arm/boot/dts/{keystone.dts => keystone.dtsi}  |    2 -
>>  drivers/clk/keystone/pll.c                         |   24 +++++++--
>>  5 files changed, 96 insertions(+), 29 deletions(-)  create mode 100644
>> arch/arm/boot/dts/k2hk-evm.dts  rename arch/arm/boot/dts/{keystone.dts =>
>> keystone.dtsi} (98%)
>> 
>> --
>> 1.7.9.5

Will resend. Subject is missing.

^ permalink raw reply	[flat|nested] 20+ messages in thread
* [PATCH v2 0/4]
@ 2014-01-02 16:12 Sebastian Schuberth
  0 siblings, 0 replies; 20+ messages in thread
From: Sebastian Schuberth @ 2014-01-02 16:12 UTC (permalink / raw)
  To: Git Mailing List; +Cc: Junio C Hamano, Christian Couder

This is the second iteration of the patches in

http://www.spinics.net/lists/git/msg222428.html
http://www.spinics.net/lists/git/msg222429.html

which

* adds a commit to use the term "builtin" instead of "internal command",
* also modifies the docs accordingly,
* moves the is_builtin() declaration to the existing builtin.h,
* finally moves all builtin-related definitions to a new builtin.c file.

Sebastian Schuberth (4):
  Consistently use the term "builtin" instead of "internal command"
  Call load_command_list() only when it is needed
  Speed up is_git_command() by checking early for internal commands
  Move builtin-related implementations to a new builtin.c file

 Documentation/technical/api-builtin.txt |   4 +-
 Makefile                                |   1 +
 builtin.c                               | 225 ++++++++++++++++++++++++++++++
 builtin.h                               |  23 +++
 builtin/help.c                          |   6 +-
 git.c                                   | 238 +-------------------------------
 6 files changed, 262 insertions(+), 235 deletions(-)
 create mode 100644 builtin.c

-- 
1.8.3-mingw-1

^ permalink raw reply	[flat|nested] 20+ messages in thread
* [PATCH v2 0/4]
@ 2014-01-29  6:00 Max Filippov
  0 siblings, 0 replies; 20+ messages in thread
From: Max Filippov @ 2014-01-29  6:00 UTC (permalink / raw)
  To: linux-xtensa, netdev, linux-kernel
  Cc: Chris Zankel, Marc Gauthier, David S. Miller, Ben Hutchings,
	Florian Fainelli, Max Filippov

Hello David, Ben, Florian, Chris and everybody,

this series improves ethoc behavior in gigabit environment:
- first patch introduces two phylib setters for 'advertising' and 'supported'
  fields of struct phy_device;
- second patch disables gigabit advertisement in the attached PHY making
  possible to use gigabit link without any additional setup;
- third patch adds support to set up MII management bus frequency, adding
  new fields to platform data and to OF bindings;
- fourth patch adds basic ethtool support to ethoc driver.

These changes allow to use KC-705 board with 50MHz xtensa core and OpenCores
10/100 Mbps MAC connected to gigabit network without any additional setup.

Changes v1->v2:
- new patch "phy: provide accessors for 'advertising' and 'supported' fields";
- disable both gigabit advertisement and support;
- drop MDIO bus frequency configurability, always configure for standard
  2.5MHz;
- allow using common clock framework to provide ethoc clock;
- new patch: "net: ethoc: implement ethtool operations";
- drop device tree bindings documentation patch until common bindings format
  for network drivers is decided.

Max Filippov (4):
  phy: provide accessors for 'advertising' and 'supported' fields
  net: ethoc: don't advertise gigabit speed on attached PHY
  net: ethoc: set up MII management bus clock
  net: ethoc: implement ethtool operations

 drivers/net/ethernet/ethoc.c | 130 ++++++++++++++++++++++++++++++++++++++++++-
 include/linux/phy.h          |  12 ++++
 include/net/ethoc.h          |   1 +
 3 files changed, 141 insertions(+), 2 deletions(-)

-- 
1.8.1.4

^ permalink raw reply	[flat|nested] 20+ messages in thread
* [PATCH V2 0/4]
@ 2021-06-02  2:10 ` Jason Wang
  0 siblings, 0 replies; 20+ messages in thread
From: Jason Wang @ 2021-06-02  2:10 UTC (permalink / raw)
  To: mst, jasowang, virtualization, linux-kernel, kvm, netdev; +Cc: eli

*** BLURB HERE ***

Eli Cohen (1):
  virtio/vdpa: clear the virtqueue state during probe

Jason Wang (3):
  vdpa: support packed virtqueue for set/get_vq_state()
  virtio-pci library: introduce vp_modern_get_driver_features()
  vp_vdpa: allow set vq state to initial state after reset

 drivers/vdpa/ifcvf/ifcvf_main.c        |  4 +--
 drivers/vdpa/mlx5/net/mlx5_vnet.c      |  8 ++---
 drivers/vdpa/vdpa_sim/vdpa_sim.c       |  4 +--
 drivers/vdpa/virtio_pci/vp_vdpa.c      | 42 ++++++++++++++++++++++++--
 drivers/vhost/vdpa.c                   |  4 +--
 drivers/virtio/virtio_pci_modern_dev.c | 21 +++++++++++++
 drivers/virtio/virtio_vdpa.c           | 15 +++++++++
 include/linux/vdpa.h                   | 25 +++++++++++++--
 include/linux/virtio_pci_modern.h      |  1 +
 9 files changed, 109 insertions(+), 15 deletions(-)

-- 
2.25.1

_______________________________________________
Virtualization mailing list
Virtualization@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/virtualization

^ permalink raw reply	[flat|nested] 20+ messages in thread
* [PATCH V2 0/4]
@ 2021-06-02  2:10 ` Jason Wang
  0 siblings, 0 replies; 20+ messages in thread
From: Jason Wang @ 2021-06-02  2:10 UTC (permalink / raw)
  To: mst, jasowang, virtualization, linux-kernel, kvm, netdev; +Cc: eli

*** BLURB HERE ***

Eli Cohen (1):
  virtio/vdpa: clear the virtqueue state during probe

Jason Wang (3):
  vdpa: support packed virtqueue for set/get_vq_state()
  virtio-pci library: introduce vp_modern_get_driver_features()
  vp_vdpa: allow set vq state to initial state after reset

 drivers/vdpa/ifcvf/ifcvf_main.c        |  4 +--
 drivers/vdpa/mlx5/net/mlx5_vnet.c      |  8 ++---
 drivers/vdpa/vdpa_sim/vdpa_sim.c       |  4 +--
 drivers/vdpa/virtio_pci/vp_vdpa.c      | 42 ++++++++++++++++++++++++--
 drivers/vhost/vdpa.c                   |  4 +--
 drivers/virtio/virtio_pci_modern_dev.c | 21 +++++++++++++
 drivers/virtio/virtio_vdpa.c           | 15 +++++++++
 include/linux/vdpa.h                   | 25 +++++++++++++--
 include/linux/virtio_pci_modern.h      |  1 +
 9 files changed, 109 insertions(+), 15 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 20+ messages in thread
* Re: [PATCH V2 0/4]
  2021-06-02  2:10 ` Jason Wang
@ 2021-06-02  2:15   ` Jason Wang
  -1 siblings, 0 replies; 20+ messages in thread
From: Jason Wang @ 2021-06-02  2:15 UTC (permalink / raw)
  To: mst, virtualization, linux-kernel, kvm, netdev; +Cc: eli


在 2021/6/2 上午10:10, Jason Wang 写道:
> *** BLURB HERE ***


Missing blurb...

Will resend a new version.

Thanks


>
> Eli Cohen (1):
>    virtio/vdpa: clear the virtqueue state during probe
>
> Jason Wang (3):
>    vdpa: support packed virtqueue for set/get_vq_state()
>    virtio-pci library: introduce vp_modern_get_driver_features()
>    vp_vdpa: allow set vq state to initial state after reset
>
>   drivers/vdpa/ifcvf/ifcvf_main.c        |  4 +--
>   drivers/vdpa/mlx5/net/mlx5_vnet.c      |  8 ++---
>   drivers/vdpa/vdpa_sim/vdpa_sim.c       |  4 +--
>   drivers/vdpa/virtio_pci/vp_vdpa.c      | 42 ++++++++++++++++++++++++--
>   drivers/vhost/vdpa.c                   |  4 +--
>   drivers/virtio/virtio_pci_modern_dev.c | 21 +++++++++++++
>   drivers/virtio/virtio_vdpa.c           | 15 +++++++++
>   include/linux/vdpa.h                   | 25 +++++++++++++--
>   include/linux/virtio_pci_modern.h      |  1 +
>   9 files changed, 109 insertions(+), 15 deletions(-)
>

_______________________________________________
Virtualization mailing list
Virtualization@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/virtualization

^ permalink raw reply	[flat|nested] 20+ messages in thread
* Re: [PATCH V2 0/4]
@ 2021-06-02  2:15   ` Jason Wang
  0 siblings, 0 replies; 20+ messages in thread
From: Jason Wang @ 2021-06-02  2:15 UTC (permalink / raw)
  To: mst, virtualization, linux-kernel, kvm, netdev; +Cc: eli


在 2021/6/2 上午10:10, Jason Wang 写道:
> *** BLURB HERE ***


Missing blurb...

Will resend a new version.

Thanks


>
> Eli Cohen (1):
>    virtio/vdpa: clear the virtqueue state during probe
>
> Jason Wang (3):
>    vdpa: support packed virtqueue for set/get_vq_state()
>    virtio-pci library: introduce vp_modern_get_driver_features()
>    vp_vdpa: allow set vq state to initial state after reset
>
>   drivers/vdpa/ifcvf/ifcvf_main.c        |  4 +--
>   drivers/vdpa/mlx5/net/mlx5_vnet.c      |  8 ++---
>   drivers/vdpa/vdpa_sim/vdpa_sim.c       |  4 +--
>   drivers/vdpa/virtio_pci/vp_vdpa.c      | 42 ++++++++++++++++++++++++--
>   drivers/vhost/vdpa.c                   |  4 +--
>   drivers/virtio/virtio_pci_modern_dev.c | 21 +++++++++++++
>   drivers/virtio/virtio_vdpa.c           | 15 +++++++++
>   include/linux/vdpa.h                   | 25 +++++++++++++--
>   include/linux/virtio_pci_modern.h      |  1 +
>   9 files changed, 109 insertions(+), 15 deletions(-)
>


^ permalink raw reply	[flat|nested] 20+ messages in thread
end of thread, other threads:[~2021-06-02  2:15 UTC | newest]

Thread overview: 20+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-10-11  9:58 [PATCH V2 0/4] Joseph Lo
2013-10-11  9:58 ` Joseph Lo
     [not found] ` <1381485519-4027-1-git-send-email-josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-10-11  9:58   ` [PATCH V2 1/4] clk: tegra124: add suspend/resume function for tegra_cpu_car_ops Joseph Lo
2013-10-11  9:58     ` Joseph Lo
2013-10-11  9:58   ` [PATCH V2 2/4] ARM: tegra: re-calculate the LP1 data for Tegra30/114 Joseph Lo
2013-10-11  9:58     ` Joseph Lo
2013-10-11  9:58   ` [PATCH V2 3/4] ARM: tegra: add LP1 support code for Tegra124 Joseph Lo
2013-10-11  9:58     ` Joseph Lo
2013-10-11  9:58   ` [PATCH V2 4/4] ARM: tegra: enable LP1 suspend mode for Venice2 Joseph Lo
2013-10-11  9:58     ` Joseph Lo
2013-10-11 18:40   ` [PATCH V2 0/4] Stephen Warren
2013-10-11 18:40     ` Stephen Warren
  -- strict thread matches above, loose matches on Subject: below --
2013-11-20  0:43 [PATCH v2 0/4] Murali Karicheri
2013-11-20  0:45 ` Karicheri, Muralidharan
2014-01-02 16:12 Sebastian Schuberth
2014-01-29  6:00 Max Filippov
2021-06-02  2:10 [PATCH V2 0/4] Jason Wang
2021-06-02  2:10 ` Jason Wang
2021-06-02  2:15 ` Jason Wang
2021-06-02  2:15   ` Jason Wang

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