From: Richard Henderson <rth@twiddle.net>
To: Tom Musta <tommusta@gmail.com>, qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org
Subject: Re: [Qemu-devel] [V2 PATCH 12/14] target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-Adds
Date: Wed, 20 Nov 2013 10:29:40 +1000 [thread overview]
Message-ID: <528C0274.5020208@twiddle.net> (raw)
In-Reply-To: <1384868432-2427-13-git-send-email-tommusta@gmail.com>
On 11/19/2013 11:40 PM, Tom Musta wrote:
> + /* NOTE: in order to get accurate results, we must first round back */ \
> + /* to single precision and use the fused multiply add routine */ \
> + /* for 32-bit floats. */ \
> + float_status tstat = env->fp_status; \
> + float32 a32 = float64_to_float32(xa.f64[0], &tstat); \
> + float32 b32 = float64_to_float32(b->f64[0], &tstat); \
> + float32 c32 = float64_to_float32(c->f64[0], &tstat); \
> + \
> + set_float_exception_flags(0, &tstat); \
> + float32 t32 = float32_muladd(a32, b32, c32, maddflgs, &tstat); \
While this will produce correct results for the "normal" use case of correctly
rounded single-precision inputs, the spec says
# Except for xsresp or xsrsqrtesp, any double-precision value can
# be used in single-precision scalar arithmetic operations when
# OE=0 and UE=0.
Thus a more correct implementation would use the full double-precision inputs
while also correctly rounding. I pointed you at the glibc implementation to
show how that can be done using round-to-zero plus examining the inexact bit.
float_status tstat = env->fp_status;
set_float_exception_flags(0, &tstat);
if (tstat.float_rounding_mode == float_round_nearest_even) {
/* Avoid double rounding errors by rounding the intermediate
result to odd. See
http://hal.inria.fr/docs/00/08/04/27/PDF/odd-rounding.pdf */
set_float_rounding_mode(float_round_to_zero, &tstat);
res = float64_muladd(...);
res |= (get_float_exception_flags(&tstat) & float_flag_inexact) != 0;
} else {
res = float64_muladd(...);
}
res = helper_frsp(env, res);
apply tstat exceptions;
r~
next prev parent reply other threads:[~2013-11-20 0:29 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-11-19 13:40 [Qemu-devel] [V2 PATCH 00/14] target-ppc: VSX Stage 4 Tom Musta
2013-11-19 13:40 ` [Qemu-devel] [V2 PATCH 01/14] target-ppc: VSX Stage 4: Add VSX 2.07 Flag Tom Musta
2013-11-19 13:40 ` [Qemu-devel] [V2 PATCH 02/14] target-ppc: VSX Stage 4: Refactor lxsdx Tom Musta
2013-11-19 13:40 ` [Qemu-devel] [V2 PATCH 03/14] target-ppc: VSX Stage 4: Add lxsiwax, lxsiwzx and lxsspx Tom Musta
2013-11-19 13:40 ` [Qemu-devel] [V2 PATCH 04/14] target-ppc: VSX Stage 4: Refactor stxsdx Tom Musta
2013-11-19 13:40 ` [Qemu-devel] [V2 PATCH 05/14] target-ppc: VSX Stage 4: Add stxsiwx and stxsspx Tom Musta
2013-11-19 13:40 ` [Qemu-devel] [V2 PATCH 06/14] target-ppc: VSX Stage 4: Add xsaddsp and xssubsp Tom Musta
2013-11-19 13:40 ` [Qemu-devel] [V2 PATCH 07/14] target-ppc: VSX Stage 4: Add xsmulsp Tom Musta
2013-11-19 13:40 ` [Qemu-devel] [V2 PATCH 08/14] target-ppc: VSX Stage 4: Add xsdivsp Tom Musta
2013-11-19 13:40 ` [Qemu-devel] [V2 PATCH 09/14] target-ppc: VSX Stage 4: Add xsresp Tom Musta
2013-11-19 13:40 ` [Qemu-devel] [V2 PATCH 10/14] target-ppc: VSX Stage 4: Add xssqrtsp Tom Musta
2013-11-19 13:40 ` [Qemu-devel] [V2 PATCH 11/14] target-ppc: VSX Stage 4: add xsrsqrtesp Tom Musta
2013-11-19 13:40 ` [Qemu-devel] [V2 PATCH 12/14] target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-Adds Tom Musta
2013-11-20 0:29 ` Richard Henderson [this message]
2013-11-19 13:40 ` [Qemu-devel] [V2 PATCH 13/14] target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdsp Tom Musta
2013-11-19 13:40 ` [Qemu-devel] [V2 PATCH 14/14] target-ppc: VSX Stage 4: Add xxleqv, xxlnand and xxlorc Tom Musta
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