From: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
To: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Peter De Schrijver
<pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Prashant Gaikwad
<pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Mike Turquette
<mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: Re: [PATCH 1/5] clk: tegra: fix blink clock rate
Date: Sun, 01 Dec 2013 12:21:17 -0700 [thread overview]
Message-ID: <529B8C2D.3000300@wwwdotorg.org> (raw)
In-Reply-To: <20131129152241.GM9712-AwZRO8vwLAwmlAP/+Wk3EA@public.gmane.org>
On 11/29/2013 08:22 AM, Thierry Reding wrote:
> On Wed, Nov 20, 2013 at 04:47:18PM -0700, Stephen Warren wrote:
>> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>
>> The blink clock rate needs to be configured, or it will run at
>> ~1Hz rather than the desired 32KHz. If it runs at the wrong rate,
>> e.g. the SDIO WiFi on Seaboard and Cardhu will fail to be
>> detected.
>
> How is this related to WiFi?
The "blink" clock output from Tegra is connected to the WiFi module,
which then uses it for something; it probably has a PLL connected to
it that drives all the internal circuitry.
WARNING: multiple messages have this Message-ID (diff)
From: swarren@wwwdotorg.org (Stephen Warren)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/5] clk: tegra: fix blink clock rate
Date: Sun, 01 Dec 2013 12:21:17 -0700 [thread overview]
Message-ID: <529B8C2D.3000300@wwwdotorg.org> (raw)
In-Reply-To: <20131129152241.GM9712@ulmo.nvidia.com>
On 11/29/2013 08:22 AM, Thierry Reding wrote:
> On Wed, Nov 20, 2013 at 04:47:18PM -0700, Stephen Warren wrote:
>> From: Stephen Warren <swarren@nvidia.com>
>>
>> The blink clock rate needs to be configured, or it will run at
>> ~1Hz rather than the desired 32KHz. If it runs at the wrong rate,
>> e.g. the SDIO WiFi on Seaboard and Cardhu will fail to be
>> detected.
>
> How is this related to WiFi?
The "blink" clock output from Tegra is connected to the WiFi module,
which then uses it for something; it probably has a PLL connected to
it that drives all the internal circuitry.
next prev parent reply other threads:[~2013-12-01 19:21 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-11-20 23:47 [PATCH 1/5] clk: tegra: fix blink clock rate Stephen Warren
2013-11-20 23:47 ` Stephen Warren
[not found] ` <1384991242-13596-1-git-send-email-swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-11-20 23:47 ` [PATCH 2/5] clk: tegra: remove some redundant defines from Tegra114 Stephen Warren
2013-11-20 23:47 ` Stephen Warren
2013-11-20 23:47 ` [PATCH 3/5] clk: tegra: remove some redundant defines from Tegra30 Stephen Warren
2013-11-20 23:47 ` Stephen Warren
2013-11-20 23:47 ` [PATCH 4/5] clk: tegra: remove some redunant defines from Tegra20 Stephen Warren
2013-11-20 23:47 ` Stephen Warren
2013-11-20 23:47 ` [PATCH 5/5] clk: tegra: remove some redundant defines from Tegra124 Stephen Warren
2013-11-20 23:47 ` Stephen Warren
2013-11-22 13:45 ` [PATCH 1/5] clk: tegra: fix blink clock rate Peter De Schrijver
2013-11-22 13:45 ` Peter De Schrijver
2013-11-29 15:22 ` Thierry Reding
2013-11-29 15:22 ` Thierry Reding
[not found] ` <20131129152241.GM9712-AwZRO8vwLAwmlAP/+Wk3EA@public.gmane.org>
2013-11-29 15:37 ` Thierry Reding
2013-11-29 15:37 ` Thierry Reding
2013-12-01 19:21 ` Stephen Warren [this message]
2013-12-01 19:21 ` Stephen Warren
[not found] ` <529B8C2D.3000300-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-12-02 9:37 ` Thierry Reding
2013-12-02 9:37 ` Thierry Reding
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