From: Richard Henderson <rth@twiddle.net>
To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: patches@linaro.org, "Michael Matz" <matz@suse.de>,
"Claudio Fontana" <claudio.fontana@linaro.org>,
"Dirk Mueller" <dmueller@suse.de>,
"Will Newton" <will.newton@linaro.org>,
"Laurent Desnogues" <laurent.desnogues@gmail.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
kvmarm@lists.cs.columbia.edu,
"Christoffer Dall" <christoffer.dall@linaro.org>
Subject: Re: [Qemu-devel] [PATCH 9/9] target-arm: A64: implement SVC, BRK
Date: Mon, 09 Dec 2013 13:58:13 -0800 [thread overview]
Message-ID: <52A63CF5.4090100@twiddle.net> (raw)
In-Reply-To: <1386612744-1013-10-git-send-email-peter.maydell@linaro.org>
On 12/09/2013 10:12 AM, Peter Maydell wrote:
> + case 0:
> + /* SVC, HVC, SMC; since we don't support the Virtualization
> + * or TrustZone extensions these all UNDEF except SVC.
> + */
> + if (op2_ll != 1) {
> + unallocated_encoding(s);
> + break;
> + }
> + gen_exception_insn(s, 0, EXCP_SWI);
> + break;
Should the imm16 should be stored somewhere, for exception.syndrome?
I can only presume from this that the AA64 userland doesn't encode its syscall
number in the insn...
Otherwise,
Reviewed-by: Richard Henderson <rth@twiddle.net>
r~
next prev parent reply other threads:[~2013-12-09 21:58 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-09 18:12 [Qemu-devel] [PATCH 0/9] target-arm: A64 decoder set 3: loads, stores, misc integer Peter Maydell
2013-12-09 18:12 ` [Qemu-devel] [PATCH 1/9] target-arm: A64: add support for stp (store pair) Peter Maydell
2013-12-09 20:17 ` Richard Henderson
2013-12-10 14:05 ` Alex Bennée
2013-12-09 18:12 ` [Qemu-devel] [PATCH 2/9] target-arm: A64: add support for ldp (load pair) Peter Maydell
2013-12-09 20:25 ` Richard Henderson
2013-12-10 13:59 ` Alex Bennée
2013-12-10 16:58 ` Richard Henderson
2013-12-10 17:41 ` Alex Bennée
2013-12-09 18:12 ` [Qemu-devel] [PATCH 3/9] target-arm: A64: add support for ld/st unsigned imm Peter Maydell
2013-12-09 21:02 ` Richard Henderson
2013-12-10 14:09 ` Alex Bennée
2013-12-09 18:12 ` [Qemu-devel] [PATCH 4/9] target-arm: A64: add support for ld/st with reg offset Peter Maydell
2013-12-09 21:09 ` Richard Henderson
2013-12-10 14:16 ` Alex Bennée
2013-12-10 15:59 ` Richard Henderson
2013-12-11 22:01 ` Alex Bennée
2013-12-09 18:12 ` [Qemu-devel] [PATCH 5/9] target-arm: A64: add support for ld/st with index Peter Maydell
2013-12-09 18:12 ` [Qemu-devel] [PATCH 6/9] target-arm: A64: add support for add, addi, sub, subi Peter Maydell
2013-12-09 21:36 ` Richard Henderson
2013-12-09 18:12 ` [Qemu-devel] [PATCH 7/9] target-arm: A64: add support for move wide instructions Peter Maydell
2013-12-09 21:42 ` Richard Henderson
2013-12-09 18:12 ` [Qemu-devel] [PATCH 8/9] target-arm: A64: add support for 3 src data proc insns Peter Maydell
2013-12-09 21:52 ` Richard Henderson
2013-12-09 18:12 ` [Qemu-devel] [PATCH 9/9] target-arm: A64: implement SVC, BRK Peter Maydell
2013-12-09 21:58 ` Richard Henderson [this message]
2013-12-09 22:14 ` Peter Maydell
2013-12-09 18:16 ` [Qemu-devel] [PATCH 0/9] target-arm: A64 decoder set 3: loads, stores, misc integer Peter Maydell
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