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From: "Alex Bennée" <alex.bennee@linaro.org>
To: Richard Henderson <rth@twiddle.net>
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
	patches@linaro.org, "Michael Matz" <matz@suse.de>,
	qemu-devel@nongnu.org,
	"Claudio Fontana" <claudio.fontana@linaro.org>,
	"Dirk Mueller" <dmueller@suse.de>,
	"Will Newton" <will.newton@linaro.org>,
	"Laurent Desnogues" <laurent.desnogues@gmail.com>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	kvmarm@lists.cs.columbia.edu,
	"Christoffer Dall" <christoffer.dall@linaro.org>
Subject: Re: [Qemu-devel] [PATCH 4/9] target-arm: A64: add support for ld/st with reg offset
Date: Wed, 11 Dec 2013 22:01:49 +0000	[thread overview]
Message-ID: <87r49jnj1u.fsf@linaro.org> (raw)
In-Reply-To: <52A73A5F.4050101@twiddle.net>


rth@twiddle.net writes:

> On 12/10/2013 06:16 AM, Alex Bennée wrote:
>> However my preference unless there is a strong objection would be to
>> clean that up in later patches. For one thing the more instructions each
>> patch handles the longer it takes to run the instruction validation on
>> the rather slow models to have good coverage of the decoder!
>
> That'd be ok by me.

I had a play trying to see what pulling out the common parts of decode
and unallocated handling based on the ARM ARM pseudo-code into a
separate function would look like. Unfortunately what I ended up
with was a horrible function full of pass-by-reference parameters and a
not particularly cleaner or shorter call-sites in each handler.

I did briefly consider if I could construct a macro which would make for
less duplicated code but suspect that won't help in the long run.

This is certainly something I think that requires more thought. In the
meantime I've addresses your other review comments and Peter should be
pushing a new set of patches soon.


Cheers,

--
Alex Bennée
QEMU/KVM Hacker for Linaro

  reply	other threads:[~2013-12-11 22:02 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-12-09 18:12 [Qemu-devel] [PATCH 0/9] target-arm: A64 decoder set 3: loads, stores, misc integer Peter Maydell
2013-12-09 18:12 ` [Qemu-devel] [PATCH 1/9] target-arm: A64: add support for stp (store pair) Peter Maydell
2013-12-09 20:17   ` Richard Henderson
2013-12-10 14:05     ` Alex Bennée
2013-12-09 18:12 ` [Qemu-devel] [PATCH 2/9] target-arm: A64: add support for ldp (load pair) Peter Maydell
2013-12-09 20:25   ` Richard Henderson
2013-12-10 13:59     ` Alex Bennée
2013-12-10 16:58       ` Richard Henderson
2013-12-10 17:41         ` Alex Bennée
2013-12-09 18:12 ` [Qemu-devel] [PATCH 3/9] target-arm: A64: add support for ld/st unsigned imm Peter Maydell
2013-12-09 21:02   ` Richard Henderson
2013-12-10 14:09     ` Alex Bennée
2013-12-09 18:12 ` [Qemu-devel] [PATCH 4/9] target-arm: A64: add support for ld/st with reg offset Peter Maydell
2013-12-09 21:09   ` Richard Henderson
2013-12-10 14:16     ` Alex Bennée
2013-12-10 15:59       ` Richard Henderson
2013-12-11 22:01         ` Alex Bennée [this message]
2013-12-09 18:12 ` [Qemu-devel] [PATCH 5/9] target-arm: A64: add support for ld/st with index Peter Maydell
2013-12-09 18:12 ` [Qemu-devel] [PATCH 6/9] target-arm: A64: add support for add, addi, sub, subi Peter Maydell
2013-12-09 21:36   ` Richard Henderson
2013-12-09 18:12 ` [Qemu-devel] [PATCH 7/9] target-arm: A64: add support for move wide instructions Peter Maydell
2013-12-09 21:42   ` Richard Henderson
2013-12-09 18:12 ` [Qemu-devel] [PATCH 8/9] target-arm: A64: add support for 3 src data proc insns Peter Maydell
2013-12-09 21:52   ` Richard Henderson
2013-12-09 18:12 ` [Qemu-devel] [PATCH 9/9] target-arm: A64: implement SVC, BRK Peter Maydell
2013-12-09 21:58   ` Richard Henderson
2013-12-09 22:14     ` Peter Maydell
2013-12-09 18:16 ` [Qemu-devel] [PATCH 0/9] target-arm: A64 decoder set 3: loads, stores, misc integer Peter Maydell

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