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From: "Emilio López" <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>
To: Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Cc: zhangfei <zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
	"Arnd Bergmann" <arnd-r2nGTMty4D4@public.gmane.org>,
	dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org,
	mark.rutland-5wv7dgnIgG8@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	dinh.linux-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
	heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org,
	pawel.moll-5wv7dgnIgG8@public.gmane.org,
	bzhao-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org,
	tgih.jun-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org,
	"Peter De Schrijver"
	<pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
	linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org,
	rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org,
	jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org,
	alim.akhtar-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org,
	cjb-2X9k7bc8m7Mdnm+yROfE0A@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	ian.campbell-Sxgqhf6Nn4DQT0dZR+AlfA@public.gmane.org,
	"Hans de Goede"
	<hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>,
	"David Lanzendörfer"
	<david.lanzendoerfer-Z7Kmv9EsliU@public.gmane.org>,
	"Chen-Yu Tsai" <wens-jdAy2FN1RRM@public.gmane.org>
Subject: Re: [PATCHv6 2/5] clk: socfpga: Add a clock type for the SD/MMC driver
Date: Mon, 16 Dec 2013 17:55:55 -0300	[thread overview]
Message-ID: <52AF68DB.7090105@elopez.com.ar> (raw)
In-Reply-To: <20131215045116.23538.4@quantum>

Hi Mike et al,

El 15/12/13 01:51, Mike Turquette escribió:
> clk_set_phase has been proposed before and now may be the time to add
> it. There are two things that need to be addressed:
>
> 1) what are the values for the phase? This needs to work for others that
> must set clk phase, so we need to consider all those requirements before
> making a new function declaration in clk.h
>
> 2) is setting a clock's phase something done dynamically? Put another
> way, does the same clock has it's phase set multiple times while the
> system is running? For static configuration that only happens during
> initialization we do not need a new API. The clock driver can handle it
> privately. For dynamic operations though we likely need a new API.

We on sunxi also need this for our (not yet merged) MMC driver; we 
currently have it implemented as an exported

void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output)

that takes the MMC clock (and only the MMC clock) and does the setup 
(it's basically configuring two values, "sample" and "output", into the 
clock register). I really don't know what does this do/why is it 
required/when is it used; I'm cc'ing Hans and David who can hopefully 
explain that part.

I also saw a similar requirement from the gmac people (on cc too), who 
needed to set the phy type (or something like that) on one of the clock 
registers; so I'm thinking maybe a generic "tune something" approach 
that lets users configure some clock-dependent, arbitrary aspect of the 
clock is the way forward. Otherwise, we're going to end up bloating the 
clock framework with a lot of callback pointers that are going to be 
used in one or two clocks out of potentially hundreds on the whole system.

Cheers,

Emilio
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WARNING: multiple messages have this Message-ID (diff)
From: emilio@elopez.com.ar (Emilio López)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCHv6 2/5] clk: socfpga: Add a clock type for the SD/MMC driver
Date: Mon, 16 Dec 2013 17:55:55 -0300	[thread overview]
Message-ID: <52AF68DB.7090105@elopez.com.ar> (raw)
In-Reply-To: <20131215045116.23538.4@quantum>

Hi Mike et al,

El 15/12/13 01:51, Mike Turquette escribi?:
> clk_set_phase has been proposed before and now may be the time to add
> it. There are two things that need to be addressed:
>
> 1) what are the values for the phase? This needs to work for others that
> must set clk phase, so we need to consider all those requirements before
> making a new function declaration in clk.h
>
> 2) is setting a clock's phase something done dynamically? Put another
> way, does the same clock has it's phase set multiple times while the
> system is running? For static configuration that only happens during
> initialization we do not need a new API. The clock driver can handle it
> privately. For dynamic operations though we likely need a new API.

We on sunxi also need this for our (not yet merged) MMC driver; we 
currently have it implemented as an exported

void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output)

that takes the MMC clock (and only the MMC clock) and does the setup 
(it's basically configuring two values, "sample" and "output", into the 
clock register). I really don't know what does this do/why is it 
required/when is it used; I'm cc'ing Hans and David who can hopefully 
explain that part.

I also saw a similar requirement from the gmac people (on cc too), who 
needed to set the phy type (or something like that) on one of the clock 
registers; so I'm thinking maybe a generic "tune something" approach 
that lets users configure some clock-dependent, arbitrary aspect of the 
clock is the way forward. Otherwise, we're going to end up bloating the 
clock framework with a lot of callback pointers that are going to be 
used in one or two clocks out of potentially hundreds on the whole system.

Cheers,

Emilio

  reply	other threads:[~2013-12-16 20:55 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-12-12 20:30 [PATCHv6 0/5] socfpga: Enable SD/MMC support dinguyen
2013-12-12 20:30 ` dinguyen at altera.com
2013-12-12 20:30 ` [PATCHv6 1/5] mmc: dw_mmc: Add support to set the SDR and DDR timing through clock framework dinguyen
2013-12-12 20:30   ` dinguyen at altera.com
2013-12-15  2:05   ` zhangfei
2013-12-15  2:05     ` zhangfei
2013-12-15  3:16     ` Dinh Nguyen
2013-12-15  3:16       ` Dinh Nguyen
2013-12-15  4:37       ` zhangfei
2013-12-15  4:37         ` zhangfei
     [not found]         ` <52AD320A.4030502-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2013-12-16  3:24           ` Dinh Nguyen
2013-12-16  3:24             ` Dinh Nguyen
2013-12-16  3:38             ` Zhangfei Gao
2013-12-16  3:38               ` Zhangfei Gao
2013-12-16  4:20   ` Seungwon Jeon
2013-12-16  4:20     ` Seungwon Jeon
     [not found] ` <1386880245-10192-1-git-send-email-dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org>
2013-12-12 20:30   ` [PATCHv6 2/5] clk: socfpga: Add a clock type for the SD/MMC driver dinguyen-EIB2kfCEclfQT0dZR+AlfA
2013-12-12 20:30     ` dinguyen at altera.com
2013-12-14 21:33     ` Arnd Bergmann
2013-12-14 21:33       ` Arnd Bergmann
2013-12-15  2:18       ` zhangfei
2013-12-15  2:18         ` zhangfei
2013-12-15  4:51         ` Mike Turquette
2013-12-15  4:51           ` Mike Turquette
2013-12-16 20:55           ` Emilio López [this message]
2013-12-16 20:55             ` Emilio López
2013-12-16 21:06             ` Hans de Goede
2013-12-16 21:06               ` Hans de Goede
2013-12-16 21:54             ` David Lanzendörfer
2013-12-16 21:54               ` David Lanzendörfer
2013-12-18 20:10               ` Mike Turquette
2013-12-18 20:10                 ` Mike Turquette
2013-12-17  2:17             ` Chen-Yu Tsai
2013-12-17  2:17               ` Chen-Yu Tsai
2013-12-12 20:30 ` [PATCHv6 3/5] dts: socfpga: Add support for SD/MMC on the SOCFPGA platform dinguyen
2013-12-12 20:30   ` dinguyen at altera.com
2013-12-12 20:30 ` [PATCHv6 4/5] mmc: dw_mmc-socfpga: Remove the SOCFPGA specific platform for dw_mmc dinguyen
2013-12-12 20:30   ` dinguyen at altera.com
2013-12-12 20:30 ` [PATCHv6 5/5] ARM: socfpga_defconfig: enable SD/MMC support dinguyen
2013-12-12 20:30   ` dinguyen at altera.com

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