Re: [RESEND LIST PATCHv7 1/4] clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk"

[zhangfei <zhangfei.gao@linaro.org>]

On 12/17/2013 09:44 PM, Dinh Nguyen wrote:
> Hi Zhangfei,
>
> On 12/17/13 1:46 AM, zhangfei wrote:
>>
>>
>> On 12/17/2013 01:04 AM, dinguyen@altera.com wrote:
>>> From: Dinh Nguyen <dinguyen@altera.com>
>>
>>> +static int socfpga_clk_prepare(struct clk_hw *hwclk)
>>> +{
>>> +    struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk);
>>> +    struct regmap *sys_mgr_base_addr;
>>> +    u32 hs_timing;
>>> +
>>> +    if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
>>> +        sys_mgr_base_addr =
>>> syscon_regmap_lookup_by_compatible("altr,sys-mgr");
>>> +        if (IS_ERR(sys_mgr_base_addr)) {
>>> +            pr_err("%s: failed to find altr,sys-mgr regmap!\n",
>>> __func__);
>>> +            return -EINVAL;
>>> +        }
>>> +        hs_timing = SYSMGR_SDMMC_CTRL_SET(socfpgaclk->clk_phase[0],
>>> +                        socfpgaclk->clk_phase[1]);
>>> +        regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET,
>>> +                        hs_timing);
>>> +    }
>>> +    return 0;
>>> +}
>>
>> So reusing gate-clk here and check the node of "altr,sys-mgr".
>> I think it is good and simple.
>> Also can define new clock combined with node "altr,sys-mgr" with
>> parent of sdmmc_clk.
>>
>> Thanks for the update, it is fine to me.
> Thanks, can I get an Ack from you for this version?
>

Sure, if it is helpful.

Thanks