From: Wojciech Dubowik <Wojciech.Dubowik@neratec.com>
To: Sujith Manoharan <sujith@msujith.org>
Cc: John Linville <linville@tuxdriver.com>, linux-wireless@vger.kernel.org
Subject: Re: [PATCH 5/5] ath9k: Fix TX IQ calibration for SoC chips
Date: Thu, 09 Jan 2014 14:35:31 +0100 [thread overview]
Message-ID: <52CEA5A3.2040308@neratec.com> (raw)
In-Reply-To: <21198.40916.260973.48444@gargle.gargle.HOWL>
On 01/09/2014 02:10 PM, Sujith Manoharan wrote:
> Wojciech Dubowik wrote:
>> This code will always set run_agc to true. Does it mean you always have
>> to run agc cal no matter what since default is anyway true or it's just a typo?
> That was the aim of the patch.
>
> When it has been decided to do TX IQ calibration, AGC cal has to be
> run. IQ cal can be done separately in the driver (pre-AR9485) or it
> can be taken care of by the HW when AGC cal is triggered.
Ok
>> The reason I am asking is that I have ran into problem with rssi reporting
>> when calibration is ongoing. It looks like beacon received just after IQ
>> mismatch calibration is reported ~10-15 dB higher than it should. I have
>> verified power with wireshark and they are ok at antenna port. Next beacons
>> are reported fine. I have tried to enable disable different antennas but it
>> doesn't seem to affect the results.
>>
>> It doesn't happen all the time but since iq calibration is on every time we
>> are scanning it puts wrong rssi value in scan result entry. I don't have a
>> proof yet but it might affect probe responses as well.
> Which chip ? Is this issue seen with an older snapshot of the driver ?
> (There is an IQ cal fix for AR955x which I haven't ported to ath9k yet).
AR9590 running on powerpc with latest openwrt i.e.
compat-wireless-2013-11-05 backported with
your changes for split pci/soc IQ calibration.
I could try to reproduce it on my host with latest wireless testing if
you think
it helps.
Wojtek
>
> Sujith
next prev parent reply other threads:[~2014-01-09 13:39 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-11-17 5:10 [PATCH 1/5] ath9k: Separate routines for PCOEM and SoC calibration Sujith Manoharan
2013-11-17 5:10 ` [PATCH 2/5] ath9k: Remove RTT/MCI code from " Sujith Manoharan
2013-11-17 5:10 ` [PATCH 3/5] ath9k: Remove unnecessary check Sujith Manoharan
2013-11-17 5:10 ` [PATCH 4/5] ath9k: Fix Carrier Leak calibration for SoC chips Sujith Manoharan
2013-11-17 5:10 ` [PATCH 5/5] ath9k: Fix TX IQ " Sujith Manoharan
2014-01-09 12:17 ` Wojciech Dubowik
2014-01-09 13:10 ` Sujith Manoharan
2014-01-09 13:35 ` Wojciech Dubowik [this message]
2014-01-09 13:52 ` Sujith Manoharan
2014-01-09 13:59 ` Wojciech Dubowik
2014-01-13 14:34 ` Wojciech Dubowik
2014-01-13 15:07 ` Sujith Manoharan
[not found] ` <52D402C3.3070606@neratec.com>
[not found] ` <21204.1991.201080.986559@gargle.gargle.HOWL>
2014-01-13 15:42 ` Sujith Manoharan
2014-01-13 16:06 ` Sujith Manoharan
2014-01-15 7:54 ` Wojciech Dubowik
2014-01-15 8:15 ` Sujith Manoharan
2014-01-15 8:30 ` Wojciech Dubowik
2014-01-16 11:06 ` [ath9k-devel] " Sujith Manoharan
2014-01-16 11:06 ` Sujith Manoharan
2014-01-16 11:19 ` [ath9k-devel] " Sujith Manoharan
2014-01-16 11:19 ` Sujith Manoharan
2014-01-16 11:44 ` [ath9k-devel] " Wojciech Dubowik
2014-01-16 11:44 ` Wojciech Dubowik
2014-01-16 21:36 ` [ath9k-devel] " Sujith Manoharan
2014-01-16 21:36 ` Sujith Manoharan
2014-01-17 7:30 ` [ath9k-devel] " Wojciech Dubowik
2014-01-17 7:30 ` Wojciech Dubowik
2014-01-20 3:33 ` [ath9k-devel] " Sujith Manoharan
2014-01-20 3:33 ` Sujith Manoharan
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