diff for duplicates of <52CEF9E7.4070706@arm.com> diff --git a/a/1.txt b/N1/1.txt index 65e2746..643f55b 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -2,28 +2,28 @@ On 08/01/14 20:57, Russell King - ARM Linux wrote: > On Wed, Jan 08, 2014 at 07:26:07PM +0000, Sudeep Holla wrote: >> +#if __LINUX_ARM_ARCH__ < 7 /* pre ARMv7 */ >> + ->> +#define MAX_CACHE_LEVEL=09=091=09/* Only 1 level supported */ ->> +#define CTR_CTYPE_SHIFT=09=0924 ->> +#define CTR_CTYPE_MASK=09=09(1 << CTR_CTYPE_SHIFT) +>> +#define MAX_CACHE_LEVEL 1 /* Only 1 level supported */ +>> +#define CTR_CTYPE_SHIFT 24 +>> +#define CTR_CTYPE_MASK (1 << CTR_CTYPE_SHIFT) >> + >> +static inline unsigned int get_ctr(void) >> +{ ->> +=09unsigned int ctr; ->> +=09asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=3Dr" (ctr)); ->> +=09return ctr; +>> + unsigned int ctr; +>> + asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr)); +>> + return ctr; >> +} >> + >> +static enum cache_type get_cache_type(int level) >> +{ ->> +=09if (level > MAX_CACHE_LEVEL) ->> +=09=09return CACHE_TYPE_NOCACHE; ->> +=09return get_ctr() & CTR_CTYPE_MASK ? ->> +=09=09CACHE_TYPE_SEPARATE : CACHE_TYPE_UNIFIED; ->=20 +>> + if (level > MAX_CACHE_LEVEL) +>> + return CACHE_TYPE_NOCACHE; +>> + return get_ctr() & CTR_CTYPE_MASK ? +>> + CACHE_TYPE_SEPARATE : CACHE_TYPE_UNIFIED; +> > So, what do we do for CPUs that don't implement the CTR? Just return > random rubbish based on decoding the CPU Identity register as if it > were the cache type register? ->=20 +> I assume you referring to some particular CPUs which don't implement this. I could not find it as optional or IMPLEMENTATION defined in ARM ARM. diff --git a/a/content_digest b/N1/content_digest index 3b17569..b63977f 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,47 +1,38 @@ "ref\01389209168-17189-1-git-send-email-sudeep.holla@arm.com\0" "ref\01389209168-17189-3-git-send-email-sudeep.holla@arm.com\0" "ref\020140108205754.GN27432@n2100.arm.linux.org.uk\0" - "From\0Sudeep Holla <Sudeep.Holla@arm.com>\0" - "Subject\0Re: [PATCH RFC 2/3] ARM: kernel: add support for cpu cache information\0" + "From\0Sudeep.Holla@arm.com (Sudeep Holla)\0" + "Subject\0[PATCH RFC 2/3] ARM: kernel: add support for cpu cache information\0" "Date\0Thu, 09 Jan 2014 19:35:03 +0000\0" - "To\0Russell King - ARM Linux <linux@arm.linux.org.uk>\0" - "Cc\0devicetree@vger.kernel.org <devicetree@vger.kernel.org>" - Ashok Raj <ashok.raj@intel.com> - Rob Herring <robh@kernel.org> - x86@kernel.org <x86@kernel.org> - linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> - Greg Kroah-Hartman <gregkh@linuxfoundation.org> - Sudeep.Holla@arm.com - linuxppc-dev@lists.ozlabs.org <linuxppc-dev@lists.ozlabs.org> - " linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On 08/01/14 20:57, Russell King - ARM Linux wrote:\n" "> On Wed, Jan 08, 2014 at 07:26:07PM +0000, Sudeep Holla wrote:\n" ">> +#if __LINUX_ARM_ARCH__ < 7 /* pre ARMv7 */\n" ">> +\n" - ">> +#define MAX_CACHE_LEVEL=09=091=09/* Only 1 level supported */\n" - ">> +#define CTR_CTYPE_SHIFT=09=0924\n" - ">> +#define CTR_CTYPE_MASK=09=09(1 << CTR_CTYPE_SHIFT)\n" + ">> +#define MAX_CACHE_LEVEL\t\t1\t/* Only 1 level supported */\n" + ">> +#define CTR_CTYPE_SHIFT\t\t24\n" + ">> +#define CTR_CTYPE_MASK\t\t(1 << CTR_CTYPE_SHIFT)\n" ">> +\n" ">> +static inline unsigned int get_ctr(void)\n" ">> +{\n" - ">> +=09unsigned int ctr;\n" - ">> +=09asm volatile (\"mrc p15, 0, %0, c0, c0, 1\" : \"=3Dr\" (ctr));\n" - ">> +=09return ctr;\n" + ">> +\tunsigned int ctr;\n" + ">> +\tasm volatile (\"mrc p15, 0, %0, c0, c0, 1\" : \"=r\" (ctr));\n" + ">> +\treturn ctr;\n" ">> +}\n" ">> +\n" ">> +static enum cache_type get_cache_type(int level)\n" ">> +{\n" - ">> +=09if (level > MAX_CACHE_LEVEL)\n" - ">> +=09=09return CACHE_TYPE_NOCACHE;\n" - ">> +=09return get_ctr() & CTR_CTYPE_MASK ?\n" - ">> +=09=09CACHE_TYPE_SEPARATE : CACHE_TYPE_UNIFIED;\n" - ">=20\n" + ">> +\tif (level > MAX_CACHE_LEVEL)\n" + ">> +\t\treturn CACHE_TYPE_NOCACHE;\n" + ">> +\treturn get_ctr() & CTR_CTYPE_MASK ?\n" + ">> +\t\tCACHE_TYPE_SEPARATE : CACHE_TYPE_UNIFIED;\n" + "> \n" "> So, what do we do for CPUs that don't implement the CTR? Just return\n" "> random rubbish based on decoding the CPU Identity register as if it\n" "> were the cache type register?\n" - ">=20\n" + "> \n" "\n" "I assume you referring to some particular CPUs which don't implement this.\n" "I could not find it as optional or IMPLEMENTATION defined in ARM ARM.\n" @@ -51,4 +42,4 @@ "Regards,\n" Sudeep -43584d5f3a1afa631176fb6c0e0e86305c11bbbcfe907153cf19de44f2b20901 +273929280f6fff15896b671e23ce20f37b1225e1dfe214ac947c8bc974d8f90d
diff --git a/a/1.txt b/N2/1.txt index 65e2746..4819b42 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -2,28 +2,28 @@ On 08/01/14 20:57, Russell King - ARM Linux wrote: > On Wed, Jan 08, 2014 at 07:26:07PM +0000, Sudeep Holla wrote: >> +#if __LINUX_ARM_ARCH__ < 7 /* pre ARMv7 */ >> + ->> +#define MAX_CACHE_LEVEL=09=091=09/* Only 1 level supported */ ->> +#define CTR_CTYPE_SHIFT=09=0924 ->> +#define CTR_CTYPE_MASK=09=09(1 << CTR_CTYPE_SHIFT) +>> +#define MAX_CACHE_LEVEL 1 /* Only 1 level supported */ +>> +#define CTR_CTYPE_SHIFT 24 +>> +#define CTR_CTYPE_MASK (1 << CTR_CTYPE_SHIFT) >> + >> +static inline unsigned int get_ctr(void) >> +{ ->> +=09unsigned int ctr; ->> +=09asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=3Dr" (ctr)); ->> +=09return ctr; +>> + unsigned int ctr; +>> + asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr)); +>> + return ctr; >> +} >> + >> +static enum cache_type get_cache_type(int level) >> +{ ->> +=09if (level > MAX_CACHE_LEVEL) ->> +=09=09return CACHE_TYPE_NOCACHE; ->> +=09return get_ctr() & CTR_CTYPE_MASK ? ->> +=09=09CACHE_TYPE_SEPARATE : CACHE_TYPE_UNIFIED; ->=20 +>> + if (level > MAX_CACHE_LEVEL) +>> + return CACHE_TYPE_NOCACHE; +>> + return get_ctr() & CTR_CTYPE_MASK ? +>> + CACHE_TYPE_SEPARATE : CACHE_TYPE_UNIFIED; +> > So, what do we do for CPUs that don't implement the CTR? Just return > random rubbish based on decoding the CPU Identity register as if it > were the cache type register? ->=20 +> I assume you referring to some particular CPUs which don't implement this. I could not find it as optional or IMPLEMENTATION defined in ARM ARM. @@ -32,3 +32,8 @@ Can you please provide more information on that ? Regards, Sudeep + +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N2/content_digest index 3b17569..db77c0f 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,47 +1,49 @@ "ref\01389209168-17189-1-git-send-email-sudeep.holla@arm.com\0" "ref\01389209168-17189-3-git-send-email-sudeep.holla@arm.com\0" "ref\020140108205754.GN27432@n2100.arm.linux.org.uk\0" - "From\0Sudeep Holla <Sudeep.Holla@arm.com>\0" + "ref\020140108205754.GN27432-l+eeeJia6m9vn6HldHNs0ANdhmdF6hFW@public.gmane.org\0" + "From\0Sudeep Holla <Sudeep.Holla-5wv7dgnIgG8@public.gmane.org>\0" "Subject\0Re: [PATCH RFC 2/3] ARM: kernel: add support for cpu cache information\0" "Date\0Thu, 09 Jan 2014 19:35:03 +0000\0" - "To\0Russell King - ARM Linux <linux@arm.linux.org.uk>\0" - "Cc\0devicetree@vger.kernel.org <devicetree@vger.kernel.org>" - Ashok Raj <ashok.raj@intel.com> - Rob Herring <robh@kernel.org> - x86@kernel.org <x86@kernel.org> - linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> - Greg Kroah-Hartman <gregkh@linuxfoundation.org> - Sudeep.Holla@arm.com - linuxppc-dev@lists.ozlabs.org <linuxppc-dev@lists.ozlabs.org> - " linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>\0" + "To\0Russell King - ARM Linux <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>\0" + "Cc\0Sudeep.Holla-5wv7dgnIgG8@public.gmane.org" + x86-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org <x86-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> + linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org <linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org> + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org> + Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> + Benjamin Herrenschmidt <benh-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org> + Greg Kroah-Hartman <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org> + " Ashok Raj <ashok.raj-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>\0" "\00:1\0" "b\0" "On 08/01/14 20:57, Russell King - ARM Linux wrote:\n" "> On Wed, Jan 08, 2014 at 07:26:07PM +0000, Sudeep Holla wrote:\n" ">> +#if __LINUX_ARM_ARCH__ < 7 /* pre ARMv7 */\n" ">> +\n" - ">> +#define MAX_CACHE_LEVEL=09=091=09/* Only 1 level supported */\n" - ">> +#define CTR_CTYPE_SHIFT=09=0924\n" - ">> +#define CTR_CTYPE_MASK=09=09(1 << CTR_CTYPE_SHIFT)\n" + ">> +#define MAX_CACHE_LEVEL\t\t1\t/* Only 1 level supported */\n" + ">> +#define CTR_CTYPE_SHIFT\t\t24\n" + ">> +#define CTR_CTYPE_MASK\t\t(1 << CTR_CTYPE_SHIFT)\n" ">> +\n" ">> +static inline unsigned int get_ctr(void)\n" ">> +{\n" - ">> +=09unsigned int ctr;\n" - ">> +=09asm volatile (\"mrc p15, 0, %0, c0, c0, 1\" : \"=3Dr\" (ctr));\n" - ">> +=09return ctr;\n" + ">> +\tunsigned int ctr;\n" + ">> +\tasm volatile (\"mrc p15, 0, %0, c0, c0, 1\" : \"=r\" (ctr));\n" + ">> +\treturn ctr;\n" ">> +}\n" ">> +\n" ">> +static enum cache_type get_cache_type(int level)\n" ">> +{\n" - ">> +=09if (level > MAX_CACHE_LEVEL)\n" - ">> +=09=09return CACHE_TYPE_NOCACHE;\n" - ">> +=09return get_ctr() & CTR_CTYPE_MASK ?\n" - ">> +=09=09CACHE_TYPE_SEPARATE : CACHE_TYPE_UNIFIED;\n" - ">=20\n" + ">> +\tif (level > MAX_CACHE_LEVEL)\n" + ">> +\t\treturn CACHE_TYPE_NOCACHE;\n" + ">> +\treturn get_ctr() & CTR_CTYPE_MASK ?\n" + ">> +\t\tCACHE_TYPE_SEPARATE : CACHE_TYPE_UNIFIED;\n" + "> \n" "> So, what do we do for CPUs that don't implement the CTR? Just return\n" "> random rubbish based on decoding the CPU Identity register as if it\n" "> were the cache type register?\n" - ">=20\n" + "> \n" "\n" "I assume you referring to some particular CPUs which don't implement this.\n" "I could not find it as optional or IMPLEMENTATION defined in ARM ARM.\n" @@ -49,6 +51,11 @@ "Can you please provide more information on that ?\n" "\n" "Regards,\n" - Sudeep + "Sudeep\n" + "\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -43584d5f3a1afa631176fb6c0e0e86305c11bbbcfe907153cf19de44f2b20901 +6b7125e31e624ca7bbc6c79daa0f008c129187e8196db2c75c1425e44eeae6a4
diff --git a/a/1.txt b/N3/1.txt index 65e2746..643f55b 100644 --- a/a/1.txt +++ b/N3/1.txt @@ -2,28 +2,28 @@ On 08/01/14 20:57, Russell King - ARM Linux wrote: > On Wed, Jan 08, 2014 at 07:26:07PM +0000, Sudeep Holla wrote: >> +#if __LINUX_ARM_ARCH__ < 7 /* pre ARMv7 */ >> + ->> +#define MAX_CACHE_LEVEL=09=091=09/* Only 1 level supported */ ->> +#define CTR_CTYPE_SHIFT=09=0924 ->> +#define CTR_CTYPE_MASK=09=09(1 << CTR_CTYPE_SHIFT) +>> +#define MAX_CACHE_LEVEL 1 /* Only 1 level supported */ +>> +#define CTR_CTYPE_SHIFT 24 +>> +#define CTR_CTYPE_MASK (1 << CTR_CTYPE_SHIFT) >> + >> +static inline unsigned int get_ctr(void) >> +{ ->> +=09unsigned int ctr; ->> +=09asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=3Dr" (ctr)); ->> +=09return ctr; +>> + unsigned int ctr; +>> + asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr)); +>> + return ctr; >> +} >> + >> +static enum cache_type get_cache_type(int level) >> +{ ->> +=09if (level > MAX_CACHE_LEVEL) ->> +=09=09return CACHE_TYPE_NOCACHE; ->> +=09return get_ctr() & CTR_CTYPE_MASK ? ->> +=09=09CACHE_TYPE_SEPARATE : CACHE_TYPE_UNIFIED; ->=20 +>> + if (level > MAX_CACHE_LEVEL) +>> + return CACHE_TYPE_NOCACHE; +>> + return get_ctr() & CTR_CTYPE_MASK ? +>> + CACHE_TYPE_SEPARATE : CACHE_TYPE_UNIFIED; +> > So, what do we do for CPUs that don't implement the CTR? Just return > random rubbish based on decoding the CPU Identity register as if it > were the cache type register? ->=20 +> I assume you referring to some particular CPUs which don't implement this. I could not find it as optional or IMPLEMENTATION defined in ARM ARM. diff --git a/a/content_digest b/N3/content_digest index 3b17569..0ccedc2 100644 --- a/a/content_digest +++ b/N3/content_digest @@ -5,43 +5,44 @@ "Subject\0Re: [PATCH RFC 2/3] ARM: kernel: add support for cpu cache information\0" "Date\0Thu, 09 Jan 2014 19:35:03 +0000\0" "To\0Russell King - ARM Linux <linux@arm.linux.org.uk>\0" - "Cc\0devicetree@vger.kernel.org <devicetree@vger.kernel.org>" - Ashok Raj <ashok.raj@intel.com> - Rob Herring <robh@kernel.org> + "Cc\0Sudeep.Holla@arm.com" x86@kernel.org <x86@kernel.org> + linuxppc-dev@lists.ozlabs.org <linuxppc-dev@lists.ozlabs.org> + devicetree@vger.kernel.org <devicetree@vger.kernel.org> linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> + linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> + Rob Herring <robh@kernel.org> + Benjamin Herrenschmidt <benh@kernel.crashing.org> Greg Kroah-Hartman <gregkh@linuxfoundation.org> - Sudeep.Holla@arm.com - linuxppc-dev@lists.ozlabs.org <linuxppc-dev@lists.ozlabs.org> - " linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>\0" + " Ashok Raj <ashok.raj@intel.com>\0" "\00:1\0" "b\0" "On 08/01/14 20:57, Russell King - ARM Linux wrote:\n" "> On Wed, Jan 08, 2014 at 07:26:07PM +0000, Sudeep Holla wrote:\n" ">> +#if __LINUX_ARM_ARCH__ < 7 /* pre ARMv7 */\n" ">> +\n" - ">> +#define MAX_CACHE_LEVEL=09=091=09/* Only 1 level supported */\n" - ">> +#define CTR_CTYPE_SHIFT=09=0924\n" - ">> +#define CTR_CTYPE_MASK=09=09(1 << CTR_CTYPE_SHIFT)\n" + ">> +#define MAX_CACHE_LEVEL\t\t1\t/* Only 1 level supported */\n" + ">> +#define CTR_CTYPE_SHIFT\t\t24\n" + ">> +#define CTR_CTYPE_MASK\t\t(1 << CTR_CTYPE_SHIFT)\n" ">> +\n" ">> +static inline unsigned int get_ctr(void)\n" ">> +{\n" - ">> +=09unsigned int ctr;\n" - ">> +=09asm volatile (\"mrc p15, 0, %0, c0, c0, 1\" : \"=3Dr\" (ctr));\n" - ">> +=09return ctr;\n" + ">> +\tunsigned int ctr;\n" + ">> +\tasm volatile (\"mrc p15, 0, %0, c0, c0, 1\" : \"=r\" (ctr));\n" + ">> +\treturn ctr;\n" ">> +}\n" ">> +\n" ">> +static enum cache_type get_cache_type(int level)\n" ">> +{\n" - ">> +=09if (level > MAX_CACHE_LEVEL)\n" - ">> +=09=09return CACHE_TYPE_NOCACHE;\n" - ">> +=09return get_ctr() & CTR_CTYPE_MASK ?\n" - ">> +=09=09CACHE_TYPE_SEPARATE : CACHE_TYPE_UNIFIED;\n" - ">=20\n" + ">> +\tif (level > MAX_CACHE_LEVEL)\n" + ">> +\t\treturn CACHE_TYPE_NOCACHE;\n" + ">> +\treturn get_ctr() & CTR_CTYPE_MASK ?\n" + ">> +\t\tCACHE_TYPE_SEPARATE : CACHE_TYPE_UNIFIED;\n" + "> \n" "> So, what do we do for CPUs that don't implement the CTR? Just return\n" "> random rubbish based on decoding the CPU Identity register as if it\n" "> were the cache type register?\n" - ">=20\n" + "> \n" "\n" "I assume you referring to some particular CPUs which don't implement this.\n" "I could not find it as optional or IMPLEMENTATION defined in ARM ARM.\n" @@ -51,4 +52,4 @@ "Regards,\n" Sudeep -43584d5f3a1afa631176fb6c0e0e86305c11bbbcfe907153cf19de44f2b20901 +07f02b58fd9d57a1a97eb8896bd023428a308ffe1c9cd12c28048d1fa07a738d
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