From: Jaehoon Chung <jh80.chung@samsung.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2] arm: exynos: change to use clrbits macro instead of readl/writel function
Date: Wed, 15 Jan 2014 14:40:03 +0900 [thread overview]
Message-ID: <52D61F33.1060406@samsung.com> (raw)
In-Reply-To: <20140115142759.66afd1ce@songinha-Samsung-DeskTop-System>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Best Regards,
Jaehoon Chung
On 01/15/2014 02:27 PM, Inha Song wrote:
> Use setbits/clrbits macro instead of readl/writel function
>
> Signed-off-by: Inha Song <ideal.song@samsung.com>
> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
> Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
> ---
> Changes for v2:
> - Coding Style cleanup
> - add signed-off-by
>
> arch/arm/cpu/armv7/exynos/clock.c | 82 +++++++++----------------------------
> 1 file changed, 20 insertions(+), 62 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
> index 5bde9d1..6c589c9 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -870,7 +870,6 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
> struct exynos4_clock *clk =
> (struct exynos4_clock *)samsung_get_base_clock();
> unsigned int addr;
> - unsigned int val;
>
> /*
> * CLK_DIV_FSYS1
> @@ -890,10 +889,8 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
> dev_index -= 2;
> }
>
> - val = readl(addr);
> - val &= ~(0xff << ((dev_index << 4) + 8));
> - val |= (div & 0xff) << ((dev_index << 4) + 8);
> - writel(val, addr);
> + clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
> + (div & 0xff) << ((dev_index << 4) + 8));
> }
>
> /* exynos4x12: set the mmc clock */
> @@ -902,7 +899,6 @@ static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
> struct exynos4x12_clock *clk =
> (struct exynos4x12_clock *)samsung_get_base_clock();
> unsigned int addr;
> - unsigned int val;
>
> /*
> * CLK_DIV_FSYS1
> @@ -917,10 +913,8 @@ static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
> dev_index -= 2;
> }
>
> - val = readl(addr);
> - val &= ~(0xff << ((dev_index << 4) + 8));
> - val |= (div & 0xff) << ((dev_index << 4) + 8);
> - writel(val, addr);
> + clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
> + (div & 0xff) << ((dev_index << 4) + 8));
> }
>
> /* exynos5: set the mmc clock */
> @@ -929,7 +923,6 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
> struct exynos5_clock *clk =
> (struct exynos5_clock *)samsung_get_base_clock();
> unsigned int addr;
> - unsigned int val;
>
> /*
> * CLK_DIV_FSYS1
> @@ -944,10 +937,8 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
> dev_index -= 2;
> }
>
> - val = readl(addr);
> - val &= ~(0xff << ((dev_index << 4) + 8));
> - val |= (div & 0xff) << ((dev_index << 4) + 8);
> - writel(val, addr);
> + clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
> + (div & 0xff) << ((dev_index << 4) + 8));
> }
>
> /* exynos5: set the mmc clock */
> @@ -956,7 +947,7 @@ static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
> struct exynos5420_clock *clk =
> (struct exynos5420_clock *)samsung_get_base_clock();
> unsigned int addr;
> - unsigned int val, shift;
> + unsigned int shift;
>
> /*
> * CLK_DIV_FSYS1
> @@ -967,10 +958,7 @@ static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
> addr = (unsigned int)&clk->div_fsys1;
> shift = dev_index * 10;
>
> - val = readl(addr);
> - val &= ~(0x3ff << shift);
> - val |= (div & 0x3ff) << shift;
> - writel(val, addr);
> + clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift);
> }
>
> /* get_lcd_clk: return lcd clock frequency */
> @@ -1061,7 +1049,6 @@ void exynos4_set_lcd_clk(void)
> {
> struct exynos4_clock *clk =
> (struct exynos4_clock *)samsung_get_base_clock();
> - unsigned int cfg = 0;
>
> /*
> * CLK_GATE_BLOCK
> @@ -1073,9 +1060,7 @@ void exynos4_set_lcd_clk(void)
> * CLK_LCD1 [5]
> * CLK_GPS [7]
> */
> - cfg = readl(&clk->gate_block);
> - cfg |= 1 << 4;
> - writel(cfg, &clk->gate_block);
> + setbits_le32(&clk->gate_block, 1 << 4);
>
> /*
> * CLK_SRC_LCD0
> @@ -1085,10 +1070,7 @@ void exynos4_set_lcd_clk(void)
> * MIPI0_SEL [12:15]
> * set lcd0 src clock 0x6: SCLK_MPLL
> */
> - cfg = readl(&clk->src_lcd0);
> - cfg &= ~(0xf);
> - cfg |= 0x6;
> - writel(cfg, &clk->src_lcd0);
> + clrsetbits_le32(&clk->src_lcd0, 0x9, 0x6);
>
> /*
> * CLK_GATE_IP_LCD0
> @@ -1100,9 +1082,7 @@ void exynos4_set_lcd_clk(void)
> * CLK_PPMULCD0 [5]
> * Gating all clocks for FIMD0
> */
> - cfg = readl(&clk->gate_ip_lcd0);
> - cfg |= 1 << 0;
> - writel(cfg, &clk->gate_ip_lcd0);
> + setbits_le32(&clk->gate_ip_lcd0, 1 << 0);
>
> /*
> * CLK_DIV_LCD0
> @@ -1114,16 +1094,13 @@ void exynos4_set_lcd_clk(void)
> * MIPI0_PRE_RATIO [23:20]
> * set fimd ratio
> */
> - cfg &= ~(0xf);
> - cfg |= 0x1;
> - writel(cfg, &clk->div_lcd0);
> + clrsetbits_le32(&clk->div_lcd0, 0xe, 0x1);
> }
>
> void exynos5_set_lcd_clk(void)
> {
> struct exynos5_clock *clk =
> (struct exynos5_clock *)samsung_get_base_clock();
> - unsigned int cfg = 0;
>
> /*
> * CLK_GATE_BLOCK
> @@ -1135,9 +1112,7 @@ void exynos5_set_lcd_clk(void)
> * CLK_LCD1 [5]
> * CLK_GPS [7]
> */
> - cfg = readl(&clk->gate_block);
> - cfg |= 1 << 4;
> - writel(cfg, &clk->gate_block);
> + setbits_le32(&clk->gate_block, 1 << 4);
>
> /*
> * CLK_SRC_LCD0
> @@ -1147,10 +1122,7 @@ void exynos5_set_lcd_clk(void)
> * MIPI0_SEL [12:15]
> * set lcd0 src clock 0x6: SCLK_MPLL
> */
> - cfg = readl(&clk->src_disp1_0);
> - cfg &= ~(0xf);
> - cfg |= 0x6;
> - writel(cfg, &clk->src_disp1_0);
> + clrsetbits_le32(&clk->src_disp1_0, 0x9, 0x6);
>
> /*
> * CLK_GATE_IP_LCD0
> @@ -1162,9 +1134,7 @@ void exynos5_set_lcd_clk(void)
> * CLK_PPMULCD0 [5]
> * Gating all clocks for FIMD0
> */
> - cfg = readl(&clk->gate_ip_disp1);
> - cfg |= 1 << 0;
> - writel(cfg, &clk->gate_ip_disp1);
> + setbits_le32(&clk->gate_ip_disp1, 1 << 0);
>
> /*
> * CLK_DIV_LCD0
> @@ -1176,16 +1146,13 @@ void exynos5_set_lcd_clk(void)
> * MIPI0_PRE_RATIO [23:20]
> * set fimd ratio
> */
> - cfg &= ~(0xf);
> - cfg |= 0x0;
> - writel(cfg, &clk->div_disp1_0);
> + clrbits_le32(&clk->div_disp1_0, 0xf);
> }
>
> void exynos4_set_mipi_clk(void)
> {
> struct exynos4_clock *clk =
> (struct exynos4_clock *)samsung_get_base_clock();
> - unsigned int cfg = 0;
>
> /*
> * CLK_SRC_LCD0
> @@ -1195,10 +1162,7 @@ void exynos4_set_mipi_clk(void)
> * MIPI0_SEL [12:15]
> * set mipi0 src clock 0x6: SCLK_MPLL
> */
> - cfg = readl(&clk->src_lcd0);
> - cfg &= ~(0xf << 12);
> - cfg |= (0x6 << 12);
> - writel(cfg, &clk->src_lcd0);
> + clrsetbits_le32(&clk->src_lcd0, 0x9 << 12, 0x6 << 12);
>
> /*
> * CLK_SRC_MASK_LCD0
> @@ -1208,9 +1172,7 @@ void exynos4_set_mipi_clk(void)
> * MIPI0_MASK [12]
> * set src mask mipi0 0x1: Unmask
> */
> - cfg = readl(&clk->src_mask_lcd0);
> - cfg |= (0x1 << 12);
> - writel(cfg, &clk->src_mask_lcd0);
> + setbits_le32(&clk->src_mask_lcd0, 0x1 << 12);
>
> /*
> * CLK_GATE_IP_LCD0
> @@ -1222,9 +1184,7 @@ void exynos4_set_mipi_clk(void)
> * CLK_PPMULCD0 [5]
> * Gating all clocks for MIPI0
> */
> - cfg = readl(&clk->gate_ip_lcd0);
> - cfg |= 1 << 3;
> - writel(cfg, &clk->gate_ip_lcd0);
> + setbits_le32(&clk->gate_ip_lcd0, 1 << 3);
>
> /*
> * CLK_DIV_LCD0
> @@ -1236,9 +1196,7 @@ void exynos4_set_mipi_clk(void)
> * MIPI0_PRE_RATIO [23:20]
> * set mipi ratio
> */
> - cfg &= ~(0xf << 16);
> - cfg |= (0x1 << 16);
> - writel(cfg, &clk->div_lcd0);
> + clrsetbits_le32(&clk->div_lcd0, 0xe << 16, 0x1 << 16);
> }
>
> /*
>
next prev parent reply other threads:[~2014-01-15 5:40 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-15 5:27 [U-Boot] [PATCH v2] arm: exynos: change to use clrbits macro instead of readl/writel function Inha Song
2014-01-15 5:40 ` Jaehoon Chung [this message]
2014-01-15 16:33 ` Gerhard Sittig
2014-01-16 7:50 ` Minkyu Kang
2014-01-16 8:20 ` Inha Song
2014-01-16 8:27 ` Jaehoon Chung
2014-01-16 8:34 ` Minkyu Kang
2014-01-16 9:04 ` Jaehoon Chung
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=52D61F33.1060406@samsung.com \
--to=jh80.chung@samsung.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.