From: "Steven J. Hill" <Steven.Hill@imgtec.com>
To: David Daney <ddaney.cavm@gmail.com>
Cc: LMOL <linux-mips@linux-mips.org>
Subject: Re: [PATCH] MIPS: lib: Optimize partial checksum ops using prefetching.
Date: Tue, 21 Jan 2014 14:16:23 -0600 [thread overview]
Message-ID: <52DED597.1040607@imgtec.com> (raw)
In-Reply-To: <52DEBBA6.9070701@gmail.com>
On 01/21/2014 12:25 PM, David Daney wrote:
> On 01/21/2014 08:18 AM, Steven J. Hill wrote:
>> From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
>>
>> Use the PREF instruction to optimize partial checksum operations.
>>
>> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
>> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
>
> NACK. The proper latench and cacheline stride vary by CPU, you cannot
> just hard code them for 32-byte cacheline size with some random latency.
>
> This will make some CPUs slower.
>
Note that memcpy.S already uses fixed cache lines (32 bytes) so this is
merely doing the same thing. I assume you have some empirical evidence
concerning other CPUs being slower?
next prev parent reply other threads:[~2014-01-21 20:17 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-21 16:18 [PATCH] MIPS: lib: Optimize partial checksum ops using prefetching Steven J. Hill
2014-01-21 17:37 ` Florian Fainelli
2014-01-21 18:25 ` David Daney
2014-01-21 20:16 ` Steven J. Hill [this message]
2014-01-21 20:25 ` Florian Fainelli
2014-01-21 20:49 ` Ralf Baechle
2014-01-21 20:58 ` Steven J. Hill
2014-01-21 20:58 ` Steven J. Hill
2014-01-21 21:03 ` David Daney
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