From: Sricharan R <r.sricharan@ti.com>
To: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-omap@vger.kernel.org, Vinod Koul <vinod.koul@intel.com>,
Dan Williams <dan.j.williams@intel.com>
Subject: Re: [PATCH RFC 08/26] dmaengine: omap-dma: consolidate setup of CCR
Date: Wed, 22 Jan 2014 18:25:57 +0530 [thread overview]
Message-ID: <52DFBFDD.8040506@ti.com> (raw)
In-Reply-To: <E1VyjuU-0005EQ-H5@rmk-PC.arm.linux.org.uk>
Hi Russell,
On Thursday 02 January 2014 08:40 PM, Russell King wrote:
> Consolidate the setup of the channel control register. Prepare the
> basic value in the preparation of the DMA descriptor, and write it into
> the register upon descriptor execution.
>
> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
> ---
> drivers/dma/omap-dma.c | 133 ++++++++++++++++-------------------------------
> 1 files changed, 45 insertions(+), 88 deletions(-)
>
> diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
> index 98928f7209f6..796f882da03c 100644
> --- a/drivers/dma/omap-dma.c
> +++ b/drivers/dma/omap-dma.c
> @@ -58,8 +58,7 @@ struct omap_desc {
>
> int16_t fi; /* for OMAP_DMA_SYNC_PACKET */
> uint8_t es; /* OMAP_DMA_DATA_TYPE_xxx */
> - uint8_t sync_mode; /* OMAP_DMA_SYNC_xxx */
> - uint8_t sync_type; /* OMAP_DMA_xxx_SYNC* */
> + uint32_t ccr; /* CCR value */
> uint16_t cicr; /* CICR value */
> uint32_t csdp; /* CSDP value */
>
> @@ -228,7 +227,6 @@ static void omap_dma_start_desc(struct omap_chan *c)
> {
> struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
> struct omap_desc *d;
> - uint32_t val;
>
> if (!vd) {
> c->desc = NULL;
> @@ -240,23 +238,15 @@ static void omap_dma_start_desc(struct omap_chan *c)
> c->desc = d = to_omap_dma_desc(&vd->tx);
> c->sgidx = 0;
>
> - if (d->dir == DMA_DEV_TO_MEM) {
> - val = c->plat->dma_read(CCR, c->dma_ch);
> - val &= ~(0x03 << 14 | 0x03 << 12);
> - val |= OMAP_DMA_AMODE_POST_INC << 14;
> - val |= OMAP_DMA_AMODE_CONSTANT << 12;
> - c->plat->dma_write(val, CCR, c->dma_ch);
> + c->plat->dma_write(d->ccr, CCR, c->dma_ch);
> + if (dma_omap1())
> + c->plat->dma_write(d->ccr >> 16, CCR2, c->dma_ch);
>
> + if (d->dir == DMA_DEV_TO_MEM) {
> c->plat->dma_write(d->dev_addr, CSSA, c->dma_ch);
> c->plat->dma_write(0, CSEI, c->dma_ch);
> c->plat->dma_write(d->fi, CSFI, c->dma_ch);
> } else {
> - val = c->plat->dma_read(CCR, c->dma_ch);
> - val &= ~(0x03 << 12 | 0x03 << 14);
> - val |= OMAP_DMA_AMODE_CONSTANT << 14;
> - val |= OMAP_DMA_AMODE_POST_INC << 12;
> - c->plat->dma_write(val, CCR, c->dma_ch);
> -
> c->plat->dma_write(d->dev_addr, CDSA, c->dma_ch);
> c->plat->dma_write(0, CDEI, c->dma_ch);
> c->plat->dma_write(d->fi, CDFI, c->dma_ch);
> @@ -264,47 +254,6 @@ static void omap_dma_start_desc(struct omap_chan *c)
>
> c->plat->dma_write(d->csdp, CSDP, c->dma_ch);
>
> - if (dma_omap1()) {
> - val = c->plat->dma_read(CCR, c->dma_ch);
> - val &= ~(1 << 5);
> - if (d->sync_mode == OMAP_DMA_SYNC_FRAME)
> - val |= 1 << 5;
> - c->plat->dma_write(val, CCR, c->dma_ch);
> -
> - val = c->plat->dma_read(CCR2, c->dma_ch);
> - val &= ~(1 << 2);
> - if (d->sync_mode == OMAP_DMA_SYNC_BLOCK)
> - val |= 1 << 2;
> - c->plat->dma_write(val, CCR2, c->dma_ch);
> - }
> -
> - if (dma_omap2plus() && c->dma_sig) {
> - val = c->plat->dma_read(CCR, c->dma_ch);
> -
> - /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
> - val &= ~(1 << 24 | 1 << 23 | 3 << 19 | 1 << 18 | 1 << 5 | 0x1f);
> - val |= (c->dma_sig & ~0x1f) << 14;
> - val |= c->dma_sig & 0x1f;
> -
> - if (d->sync_mode & OMAP_DMA_SYNC_FRAME)
> - val |= 1 << 5;
> -
> - if (d->sync_mode & OMAP_DMA_SYNC_BLOCK)
> - val |= 1 << 18;
> -
> - switch (d->sync_type) {
> - case OMAP_DMA_DST_SYNC_PREFETCH:/* dest synch */
> - val |= 1 << 23; /* Prefetch */
> - break;
> - case 0:
> - break;
> - default:
> - val |= 1 << 24; /* source synch */
> - break;
> - }
> - c->plat->dma_write(val, CCR, c->dma_ch);
> - }
> -
> omap_dma_start_sg(c, d, 0);
> }
>
> @@ -543,19 +492,17 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
> struct scatterlist *sgent;
> struct omap_desc *d;
> dma_addr_t dev_addr;
> - unsigned i, j = 0, es, en, frame_bytes, sync_type;
> + unsigned i, j = 0, es, en, frame_bytes;
> u32 burst;
>
> if (dir == DMA_DEV_TO_MEM) {
> dev_addr = c->cfg.src_addr;
> dev_width = c->cfg.src_addr_width;
> burst = c->cfg.src_maxburst;
> - sync_type = OMAP_DMA_SRC_SYNC;
> } else if (dir == DMA_MEM_TO_DEV) {
> dev_addr = c->cfg.dst_addr;
> dev_width = c->cfg.dst_addr_width;
> burst = c->cfg.dst_maxburst;
> - sync_type = OMAP_DMA_DST_SYNC;
> } else {
> dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
> return NULL;
> @@ -584,12 +531,20 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
> d->dir = dir;
> d->dev_addr = dev_addr;
> d->es = es;
> - d->sync_mode = OMAP_DMA_SYNC_FRAME;
> - d->sync_type = sync_type;
> +
> + d->ccr = 0;
> + if (dir == DMA_DEV_TO_MEM)
> + d->ccr |= OMAP_DMA_AMODE_POST_INC << 14 |
> + OMAP_DMA_AMODE_CONSTANT << 12;
> + else
> + d->ccr |= OMAP_DMA_AMODE_CONSTANT << 14 |
> + OMAP_DMA_AMODE_POST_INC << 12;
> +
> d->cicr = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
> d->csdp = es;
>
> if (dma_omap1()) {
> + d->ccr |= 1 << 5; /* frame sync */
> d->cicr |= OMAP1_DMA_TOUT_IRQ;
>
> if (dir == DMA_DEV_TO_MEM)
> @@ -599,6 +554,13 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
> d->csdp |= OMAP_DMA_PORT_TIPB << 9 |
> OMAP_DMA_PORT_EMIFF << 2;
> } else if (dma_omap2plus()) {
> + d->ccr |= (c->dma_sig & ~0x1f) << 14;
> + d->ccr |= c->dma_sig & 0x1f;
> + d->ccr |= 1 << 5; /* frame sync */
> +
> + if (dir == DMA_DEV_TO_MEM)
> + d->ccr |= 1 << 24; /* source synch */
> +
> d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
> }
>
> @@ -635,19 +597,17 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
> enum dma_slave_buswidth dev_width;
> struct omap_desc *d;
> dma_addr_t dev_addr;
> - unsigned es, sync_type;
> + unsigned es;
> u32 burst;
>
> if (dir == DMA_DEV_TO_MEM) {
> dev_addr = c->cfg.src_addr;
> dev_width = c->cfg.src_addr_width;
> burst = c->cfg.src_maxburst;
> - sync_type = OMAP_DMA_SRC_SYNC;
> } else if (dir == DMA_MEM_TO_DEV) {
> dev_addr = c->cfg.dst_addr;
> dev_width = c->cfg.dst_addr_width;
> burst = c->cfg.dst_maxburst;
> - sync_type = OMAP_DMA_DST_SYNC;
> } else {
> dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
> return NULL;
> @@ -677,15 +637,21 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
> d->dev_addr = dev_addr;
> d->fi = burst;
> d->es = es;
> - if (burst)
> - d->sync_mode = OMAP_DMA_SYNC_PACKET;
> - else
> - d->sync_mode = OMAP_DMA_SYNC_ELEMENT;
> - d->sync_type = sync_type;
> d->sg[0].addr = buf_addr;
> d->sg[0].en = period_len / es_bytes[es];
> d->sg[0].fn = buf_len / period_len;
> d->sglen = 1;
> +
> + d->ccr = 0;
> + if (__dma_omap15xx(od->plat->dma_attr))
> + d->ccr = 3 << 8;
> + if (dir == DMA_DEV_TO_MEM)
> + d->ccr |= OMAP_DMA_AMODE_POST_INC << 14 |
> + OMAP_DMA_AMODE_CONSTANT << 12;
> + else
> + d->ccr |= OMAP_DMA_AMODE_CONSTANT << 14 |
> + OMAP_DMA_AMODE_POST_INC << 12;
> +
> d->cicr = OMAP_DMA_DROP_IRQ;
> if (flags & DMA_PREP_INTERRUPT)
> d->cicr |= OMAP_DMA_FRAME_IRQ;
> @@ -702,23 +668,22 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
> d->csdp |= OMAP_DMA_PORT_MPUI << 9 |
> OMAP_DMA_PORT_EMIFF << 2;
> } else if (dma_omap2plus()) {
> + d->ccr |= (c->dma_sig & ~0x1f) << 14;
> + d->ccr |= c->dma_sig & 0x1f;
> +
> + if (burst)
> + d->ccr |= 1 << 18 | 1 << 5; /* packet */
> +
> + if (dir == DMA_DEV_TO_MEM)
> + d->ccr |= 1 << 24; /* source synch */
> +
> d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
>
> /* src and dst burst mode 16 */
> d->csdp |= 3 << 14 | 3 << 7;
> }
>
> - if (!c->cyclic) {
> - c->cyclic = true;
> -
> - if (__dma_omap15xx(od->plat->dma_attr)) {
> - uint32_t val;
> -
> - val = c->plat->dma_read(CCR, c->dma_ch);
> - val |= 3 << 8;
> - c->plat->dma_write(val, CCR, c->dma_ch);
> - }
> - }
> + c->cyclic = true;
>
> return vchan_tx_prep(&c->vc, &d->vd, flags);
> }
> @@ -762,14 +727,6 @@ static int omap_dma_terminate_all(struct omap_chan *c)
> if (c->cyclic) {
> c->cyclic = false;
> c->paused = false;
> -
> - if (__dma_omap15xx(od->plat->dma_attr)) {
> - uint32_t val;
> -
> - val = c->plat->dma_read(CCR, c->dma_ch);
> - val &= ~(3 << 8);
> - c->plat->dma_write(val, CCR, c->dma_ch);
> - }
> }
>
> vchan_get_all_descriptors(&c->vc, &head);
Setting up of DMA_DST_SYNC_PREFETCH is missing after this ?
Regards,
Sricharan
WARNING: multiple messages have this Message-ID (diff)
From: r.sricharan@ti.com (Sricharan R)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH RFC 08/26] dmaengine: omap-dma: consolidate setup of CCR
Date: Wed, 22 Jan 2014 18:25:57 +0530 [thread overview]
Message-ID: <52DFBFDD.8040506@ti.com> (raw)
In-Reply-To: <E1VyjuU-0005EQ-H5@rmk-PC.arm.linux.org.uk>
Hi Russell,
On Thursday 02 January 2014 08:40 PM, Russell King wrote:
> Consolidate the setup of the channel control register. Prepare the
> basic value in the preparation of the DMA descriptor, and write it into
> the register upon descriptor execution.
>
> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
> ---
> drivers/dma/omap-dma.c | 133 ++++++++++++++++-------------------------------
> 1 files changed, 45 insertions(+), 88 deletions(-)
>
> diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
> index 98928f7209f6..796f882da03c 100644
> --- a/drivers/dma/omap-dma.c
> +++ b/drivers/dma/omap-dma.c
> @@ -58,8 +58,7 @@ struct omap_desc {
>
> int16_t fi; /* for OMAP_DMA_SYNC_PACKET */
> uint8_t es; /* OMAP_DMA_DATA_TYPE_xxx */
> - uint8_t sync_mode; /* OMAP_DMA_SYNC_xxx */
> - uint8_t sync_type; /* OMAP_DMA_xxx_SYNC* */
> + uint32_t ccr; /* CCR value */
> uint16_t cicr; /* CICR value */
> uint32_t csdp; /* CSDP value */
>
> @@ -228,7 +227,6 @@ static void omap_dma_start_desc(struct omap_chan *c)
> {
> struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
> struct omap_desc *d;
> - uint32_t val;
>
> if (!vd) {
> c->desc = NULL;
> @@ -240,23 +238,15 @@ static void omap_dma_start_desc(struct omap_chan *c)
> c->desc = d = to_omap_dma_desc(&vd->tx);
> c->sgidx = 0;
>
> - if (d->dir == DMA_DEV_TO_MEM) {
> - val = c->plat->dma_read(CCR, c->dma_ch);
> - val &= ~(0x03 << 14 | 0x03 << 12);
> - val |= OMAP_DMA_AMODE_POST_INC << 14;
> - val |= OMAP_DMA_AMODE_CONSTANT << 12;
> - c->plat->dma_write(val, CCR, c->dma_ch);
> + c->plat->dma_write(d->ccr, CCR, c->dma_ch);
> + if (dma_omap1())
> + c->plat->dma_write(d->ccr >> 16, CCR2, c->dma_ch);
>
> + if (d->dir == DMA_DEV_TO_MEM) {
> c->plat->dma_write(d->dev_addr, CSSA, c->dma_ch);
> c->plat->dma_write(0, CSEI, c->dma_ch);
> c->plat->dma_write(d->fi, CSFI, c->dma_ch);
> } else {
> - val = c->plat->dma_read(CCR, c->dma_ch);
> - val &= ~(0x03 << 12 | 0x03 << 14);
> - val |= OMAP_DMA_AMODE_CONSTANT << 14;
> - val |= OMAP_DMA_AMODE_POST_INC << 12;
> - c->plat->dma_write(val, CCR, c->dma_ch);
> -
> c->plat->dma_write(d->dev_addr, CDSA, c->dma_ch);
> c->plat->dma_write(0, CDEI, c->dma_ch);
> c->plat->dma_write(d->fi, CDFI, c->dma_ch);
> @@ -264,47 +254,6 @@ static void omap_dma_start_desc(struct omap_chan *c)
>
> c->plat->dma_write(d->csdp, CSDP, c->dma_ch);
>
> - if (dma_omap1()) {
> - val = c->plat->dma_read(CCR, c->dma_ch);
> - val &= ~(1 << 5);
> - if (d->sync_mode == OMAP_DMA_SYNC_FRAME)
> - val |= 1 << 5;
> - c->plat->dma_write(val, CCR, c->dma_ch);
> -
> - val = c->plat->dma_read(CCR2, c->dma_ch);
> - val &= ~(1 << 2);
> - if (d->sync_mode == OMAP_DMA_SYNC_BLOCK)
> - val |= 1 << 2;
> - c->plat->dma_write(val, CCR2, c->dma_ch);
> - }
> -
> - if (dma_omap2plus() && c->dma_sig) {
> - val = c->plat->dma_read(CCR, c->dma_ch);
> -
> - /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
> - val &= ~(1 << 24 | 1 << 23 | 3 << 19 | 1 << 18 | 1 << 5 | 0x1f);
> - val |= (c->dma_sig & ~0x1f) << 14;
> - val |= c->dma_sig & 0x1f;
> -
> - if (d->sync_mode & OMAP_DMA_SYNC_FRAME)
> - val |= 1 << 5;
> -
> - if (d->sync_mode & OMAP_DMA_SYNC_BLOCK)
> - val |= 1 << 18;
> -
> - switch (d->sync_type) {
> - case OMAP_DMA_DST_SYNC_PREFETCH:/* dest synch */
> - val |= 1 << 23; /* Prefetch */
> - break;
> - case 0:
> - break;
> - default:
> - val |= 1 << 24; /* source synch */
> - break;
> - }
> - c->plat->dma_write(val, CCR, c->dma_ch);
> - }
> -
> omap_dma_start_sg(c, d, 0);
> }
>
> @@ -543,19 +492,17 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
> struct scatterlist *sgent;
> struct omap_desc *d;
> dma_addr_t dev_addr;
> - unsigned i, j = 0, es, en, frame_bytes, sync_type;
> + unsigned i, j = 0, es, en, frame_bytes;
> u32 burst;
>
> if (dir == DMA_DEV_TO_MEM) {
> dev_addr = c->cfg.src_addr;
> dev_width = c->cfg.src_addr_width;
> burst = c->cfg.src_maxburst;
> - sync_type = OMAP_DMA_SRC_SYNC;
> } else if (dir == DMA_MEM_TO_DEV) {
> dev_addr = c->cfg.dst_addr;
> dev_width = c->cfg.dst_addr_width;
> burst = c->cfg.dst_maxburst;
> - sync_type = OMAP_DMA_DST_SYNC;
> } else {
> dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
> return NULL;
> @@ -584,12 +531,20 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
> d->dir = dir;
> d->dev_addr = dev_addr;
> d->es = es;
> - d->sync_mode = OMAP_DMA_SYNC_FRAME;
> - d->sync_type = sync_type;
> +
> + d->ccr = 0;
> + if (dir == DMA_DEV_TO_MEM)
> + d->ccr |= OMAP_DMA_AMODE_POST_INC << 14 |
> + OMAP_DMA_AMODE_CONSTANT << 12;
> + else
> + d->ccr |= OMAP_DMA_AMODE_CONSTANT << 14 |
> + OMAP_DMA_AMODE_POST_INC << 12;
> +
> d->cicr = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
> d->csdp = es;
>
> if (dma_omap1()) {
> + d->ccr |= 1 << 5; /* frame sync */
> d->cicr |= OMAP1_DMA_TOUT_IRQ;
>
> if (dir == DMA_DEV_TO_MEM)
> @@ -599,6 +554,13 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
> d->csdp |= OMAP_DMA_PORT_TIPB << 9 |
> OMAP_DMA_PORT_EMIFF << 2;
> } else if (dma_omap2plus()) {
> + d->ccr |= (c->dma_sig & ~0x1f) << 14;
> + d->ccr |= c->dma_sig & 0x1f;
> + d->ccr |= 1 << 5; /* frame sync */
> +
> + if (dir == DMA_DEV_TO_MEM)
> + d->ccr |= 1 << 24; /* source synch */
> +
> d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
> }
>
> @@ -635,19 +597,17 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
> enum dma_slave_buswidth dev_width;
> struct omap_desc *d;
> dma_addr_t dev_addr;
> - unsigned es, sync_type;
> + unsigned es;
> u32 burst;
>
> if (dir == DMA_DEV_TO_MEM) {
> dev_addr = c->cfg.src_addr;
> dev_width = c->cfg.src_addr_width;
> burst = c->cfg.src_maxburst;
> - sync_type = OMAP_DMA_SRC_SYNC;
> } else if (dir == DMA_MEM_TO_DEV) {
> dev_addr = c->cfg.dst_addr;
> dev_width = c->cfg.dst_addr_width;
> burst = c->cfg.dst_maxburst;
> - sync_type = OMAP_DMA_DST_SYNC;
> } else {
> dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
> return NULL;
> @@ -677,15 +637,21 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
> d->dev_addr = dev_addr;
> d->fi = burst;
> d->es = es;
> - if (burst)
> - d->sync_mode = OMAP_DMA_SYNC_PACKET;
> - else
> - d->sync_mode = OMAP_DMA_SYNC_ELEMENT;
> - d->sync_type = sync_type;
> d->sg[0].addr = buf_addr;
> d->sg[0].en = period_len / es_bytes[es];
> d->sg[0].fn = buf_len / period_len;
> d->sglen = 1;
> +
> + d->ccr = 0;
> + if (__dma_omap15xx(od->plat->dma_attr))
> + d->ccr = 3 << 8;
> + if (dir == DMA_DEV_TO_MEM)
> + d->ccr |= OMAP_DMA_AMODE_POST_INC << 14 |
> + OMAP_DMA_AMODE_CONSTANT << 12;
> + else
> + d->ccr |= OMAP_DMA_AMODE_CONSTANT << 14 |
> + OMAP_DMA_AMODE_POST_INC << 12;
> +
> d->cicr = OMAP_DMA_DROP_IRQ;
> if (flags & DMA_PREP_INTERRUPT)
> d->cicr |= OMAP_DMA_FRAME_IRQ;
> @@ -702,23 +668,22 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
> d->csdp |= OMAP_DMA_PORT_MPUI << 9 |
> OMAP_DMA_PORT_EMIFF << 2;
> } else if (dma_omap2plus()) {
> + d->ccr |= (c->dma_sig & ~0x1f) << 14;
> + d->ccr |= c->dma_sig & 0x1f;
> +
> + if (burst)
> + d->ccr |= 1 << 18 | 1 << 5; /* packet */
> +
> + if (dir == DMA_DEV_TO_MEM)
> + d->ccr |= 1 << 24; /* source synch */
> +
> d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
>
> /* src and dst burst mode 16 */
> d->csdp |= 3 << 14 | 3 << 7;
> }
>
> - if (!c->cyclic) {
> - c->cyclic = true;
> -
> - if (__dma_omap15xx(od->plat->dma_attr)) {
> - uint32_t val;
> -
> - val = c->plat->dma_read(CCR, c->dma_ch);
> - val |= 3 << 8;
> - c->plat->dma_write(val, CCR, c->dma_ch);
> - }
> - }
> + c->cyclic = true;
>
> return vchan_tx_prep(&c->vc, &d->vd, flags);
> }
> @@ -762,14 +727,6 @@ static int omap_dma_terminate_all(struct omap_chan *c)
> if (c->cyclic) {
> c->cyclic = false;
> c->paused = false;
> -
> - if (__dma_omap15xx(od->plat->dma_attr)) {
> - uint32_t val;
> -
> - val = c->plat->dma_read(CCR, c->dma_ch);
> - val &= ~(3 << 8);
> - c->plat->dma_write(val, CCR, c->dma_ch);
> - }
> }
>
> vchan_get_all_descriptors(&c->vc, &head);
Setting up of DMA_DST_SYNC_PREFETCH is missing after this ?
Regards,
Sricharan
next prev parent reply other threads:[~2014-01-22 12:56 UTC|newest]
Thread overview: 106+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-02 15:08 [PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine Russell King - ARM Linux
2014-01-02 15:08 ` Russell King - ARM Linux
2014-01-02 15:08 ` [PATCH RFC 01/26] dmaengine: omap-dma: use devm_kzalloc() to allocate omap_dmadev Russell King
2014-01-02 15:08 ` Russell King
2014-01-02 15:09 ` [PATCH RFC 02/26] dmaengine: omap-dma: provide a hook to get the underlying DMA platform ops Russell King
2014-01-02 15:09 ` Russell King
2014-01-02 15:09 ` [PATCH RFC 03/26] dmaengine: omap-dma: program hardware directly Russell King
2014-01-02 15:09 ` Russell King
2014-01-22 12:54 ` Sricharan R
2014-01-22 12:54 ` Sricharan R
2014-01-22 14:13 ` Russell King - ARM Linux
2014-01-22 14:13 ` Russell King - ARM Linux
2014-01-02 15:09 ` [PATCH RFC 04/26] dmaengine: omap-dma: consolidate writes to DMA registers Russell King
2014-01-02 15:09 ` Russell King
2014-01-02 15:09 ` [PATCH RFC 05/26] dmaengine: omap-dma: control start/stop directly Russell King
2014-01-02 15:09 ` Russell King
2014-01-13 22:18 ` Tony Lindgren
2014-01-13 22:18 ` Tony Lindgren
2014-01-02 15:09 ` [PATCH RFC 06/26] dmaengine: omap-dma: move reading of dma position to omap-dma.c Russell King
2014-01-02 15:09 ` Russell King
2014-01-02 15:10 ` [PATCH RFC 07/26] dmaengine: omap-dma: consolidate setup of CSDP Russell King
2014-01-02 15:10 ` Russell King
2014-01-02 15:10 ` [PATCH RFC 08/26] dmaengine: omap-dma: consolidate setup of CCR Russell King
2014-01-02 15:10 ` Russell King
2014-01-13 22:14 ` Tony Lindgren
2014-01-13 22:14 ` Tony Lindgren
2014-01-13 23:12 ` Russell King - ARM Linux
2014-01-13 23:12 ` Russell King - ARM Linux
2014-01-14 13:39 ` Russell King - ARM Linux
2014-01-14 13:39 ` Russell King - ARM Linux
2014-01-14 17:04 ` Tony Lindgren
2014-01-14 17:04 ` Tony Lindgren
2014-01-22 12:55 ` Sricharan R [this message]
2014-01-22 12:55 ` Sricharan R
2014-01-22 14:19 ` Russell King - ARM Linux
2014-01-22 14:19 ` Russell King - ARM Linux
2014-01-22 14:39 ` Santosh Shilimkar
2014-01-22 14:39 ` Santosh Shilimkar
2014-01-02 15:10 ` [PATCH RFC 09/26] dmaengine: omap-dma: provide register definitions Russell King
2014-01-02 15:10 ` Russell King
2014-01-02 15:10 ` [PATCH RFC 10/26] dmaengine: omap-dma: move CCR buffering disable errata out of the fast path Russell King
2014-01-02 15:10 ` Russell King
2014-01-02 15:10 ` [PATCH RFC 11/26] dmaengine: omap-dma: consolidate clearing channel status register Russell King
2014-01-02 15:10 ` Russell King
2014-01-02 15:10 ` [PATCH RFC 12/26] dmaengine: omap-dma: improve efficiency loading C.SA/C.EI/C.FI registers Russell King
2014-01-02 15:10 ` Russell King
2014-01-02 15:11 ` [PATCH RFC 13/26] dmaengine: omap-dma: move clnk_ctrl setting to preparation functions Russell King
2014-01-02 15:11 ` Russell King
2014-01-02 15:11 ` [PATCH RFC 14/26] dmaengine: omap-dma: move barrier to omap_dma_start_desc() Russell King
2014-01-02 15:11 ` Russell King
2014-01-02 15:11 ` [PATCH RFC 15/26] dmaengine: omap-dma: use cached CCR value when enabling DMA Russell King
2014-01-02 15:11 ` Russell King
2014-01-02 15:11 ` [PATCH RFC 16/26] dmaengine: omap-dma: provide register read/write functions Russell King
2014-01-02 15:11 ` Russell King
2014-01-02 15:11 ` [PATCH RFC 17/26] dmaengine: omap-dma: cleanup errata 3.3 handling Russell King
2014-01-02 15:11 ` Russell King
2014-01-02 15:11 ` [PATCH RFC 18/26] ARM: omap: remove references to disable_irq_lch Russell King
2014-01-02 15:11 ` Russell King
2014-01-02 15:12 ` [PATCH RFC 19/26] ARM: omap: remove almost-const variables Russell King
2014-01-02 15:12 ` Russell King
2014-01-02 15:12 ` [PATCH RFC 20/26] ARM: omap: clean up DMA register accesses Russell King
2014-01-02 15:12 ` Russell King
2014-01-02 15:49 ` Andy Shevchenko
2014-01-02 15:49 ` Andy Shevchenko
2014-01-02 16:07 ` Russell King - ARM Linux
2014-01-02 16:07 ` Russell King - ARM Linux
2014-01-02 15:12 ` [PATCH RFC 21/26] ARM: omap: dma: get rid of errata global Russell King
2014-01-02 15:12 ` Russell King
2014-01-02 15:12 ` [PATCH RFC 22/26] ARM: omap: move dma channel allocation into plat-omap code Russell King
2014-01-02 15:12 ` Russell King
2014-01-02 15:46 ` Andy Shevchenko
2014-01-02 15:46 ` Andy Shevchenko
2014-01-02 15:12 ` [PATCH RFC 23/26] ARM: omap: dma: get rid of 'p' allocation and clean up Russell King
2014-01-02 15:12 ` Russell King
2014-01-02 15:12 ` [PATCH RFC 24/26] dmaengine: omap-dma: move register read/writes into omap-dma.c Russell King
2014-01-02 15:12 ` Russell King
2014-01-02 15:13 ` [PATCH RFC 25/26] dmaengine: omap-dma: move IRQ handling to omap-dma Russell King
2014-01-02 15:13 ` Russell King
2014-01-02 15:13 ` [PATCH RFC 26/26] ARM: omap2: ensure dma platform device has resources Russell King
2014-01-02 15:13 ` Russell King
2014-01-08 1:21 ` [PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine Tony Lindgren
2014-01-08 1:21 ` Tony Lindgren
2014-01-09 15:24 ` Russell King - ARM Linux
2014-01-09 15:24 ` Russell King - ARM Linux
2014-01-13 14:18 ` Russell King - ARM Linux
2014-01-13 14:18 ` Russell King - ARM Linux
2014-01-13 17:37 ` Tony Lindgren
2014-01-13 17:37 ` Tony Lindgren
2014-01-13 18:55 ` Russell King - ARM Linux
2014-01-13 18:55 ` Russell King - ARM Linux
2014-01-13 19:26 ` Tony Lindgren
2014-01-13 19:26 ` Tony Lindgren
2014-01-13 20:34 ` Russell King - ARM Linux
2014-01-13 20:34 ` Russell King - ARM Linux
2014-01-13 21:02 ` Tony Lindgren
2014-01-13 21:02 ` Tony Lindgren
2014-01-13 21:11 ` Russell King - ARM Linux
2014-01-13 21:11 ` Russell King - ARM Linux
2014-01-13 21:21 ` Tony Lindgren
2014-01-13 21:21 ` Tony Lindgren
2014-01-13 21:28 ` Russell King - ARM Linux
2014-01-13 21:28 ` Russell King - ARM Linux
2014-01-13 22:03 ` Tony Lindgren
2014-01-13 22:03 ` Tony Lindgren
2014-01-09 12:37 ` Vinod Koul
2014-01-09 12:37 ` Vinod Koul
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=52DFBFDD.8040506@ti.com \
--to=r.sricharan@ti.com \
--cc=dan.j.williams@intel.com \
--cc=dmaengine@vger.kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-omap@vger.kernel.org \
--cc=rmk+kernel@arm.linux.org.uk \
--cc=vinod.koul@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.