[U-Boot] [PATCH] ARM: tegra: don't exceed AVP limits when configuring PLLP

[Stephen Warren <swarren@wwwdotorg.org>]

On 01/22/2014 01:21 PM, Stephen Warren wrote:
> From: Jimmy Zhang <jimmzhang@nvidia.com>
> 
> Based on the Tegra114 TRM, the system clock (which is the AVP clock) can
> run up to 275MHz. On power on, the default sytem clock source is set to
> PLLP_OUT0. In function clock_early_init(), PLLP_OUT0 will be set to
> 408MHz which is beyond system clock's upper limit.
> 
> The fix is to set the system clock to CLK_M before initializing PLLP,
> and then switch back to PLLP_OUT4, which has an appropriate divider
> configured, after PLLP has been configured
> 
> Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
> [swarren, significantly refactored the changes, so that AVP only runs on
> clk_m for the short duration that PLLP is being reconfigured. Fixed
> Tegra30 too]

I think I need to revise this one patch; while going through the
Tegra124 patches, I found function adjust_pllp_out_freqs(), which really
should be used by this patch.