* [Qemu-devel] [PULL 01/49] exec: Delay CPU_LOG_TB_CPU until we actually execute a TB
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
@ 2014-01-07 20:59 ` Richard Henderson
2014-01-07 20:59 ` [Qemu-devel] [PULL 02/49] target-i386: Push DisasContext into load/store helpers Richard Henderson
` (47 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
The previous placement could result in duplicate logging while
still processing interrupts.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
cpu-exec.c | 36 +++++++++++++++++++-----------------
1 file changed, 19 insertions(+), 17 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 30cfa2a..3c4800f 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -53,7 +53,25 @@ void cpu_resume_from_signal(CPUArchState *env, void *puc)
static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, uint8_t *tb_ptr)
{
CPUArchState *env = cpu->env_ptr;
- uintptr_t next_tb = tcg_qemu_tb_exec(env, tb_ptr);
+ uintptr_t next_tb;
+
+#if defined(DEBUG_DISAS)
+ if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
+#if defined(TARGET_I386)
+ log_cpu_state(cpu, CPU_DUMP_CCOP);
+#elif defined(TARGET_M68K)
+ /* ??? Should not modify env state for dumping. */
+ cpu_m68k_flush_flags(env, env->cc_op);
+ env->cc_op = CC_OP_FLAGS;
+ env->sr = (env->sr & 0xffe0) | env->cc_dest | (env->cc_x << 4);
+ log_cpu_state(cpu, 0);
+#else
+ log_cpu_state(cpu, 0);
+#endif
+ }
+#endif /* DEBUG_DISAS */
+
+ next_tb = tcg_qemu_tb_exec(env, tb_ptr);
if ((next_tb & TB_EXIT_MASK) > TB_EXIT_IDX1) {
/* We didn't start executing this TB (eg because the instruction
* counter hit zero); we must restore the guest PC to the address
@@ -579,22 +597,6 @@ int cpu_exec(CPUArchState *env)
env->exception_index = EXCP_INTERRUPT;
cpu_loop_exit(env);
}
-#if defined(DEBUG_DISAS)
- if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
- /* restore flags in standard format */
-#if defined(TARGET_I386)
- log_cpu_state(cpu, CPU_DUMP_CCOP);
-#elif defined(TARGET_M68K)
- cpu_m68k_flush_flags(env, env->cc_op);
- env->cc_op = CC_OP_FLAGS;
- env->sr = (env->sr & 0xffe0)
- | env->cc_dest | (env->cc_x << 4);
- log_cpu_state(cpu, 0);
-#else
- log_cpu_state(cpu, 0);
-#endif
- }
-#endif /* DEBUG_DISAS */
spin_lock(&tcg_ctx.tb_ctx.tb_lock);
tb = tb_find_fast(env);
/* Note: we do it here to avoid a gcc bug on Mac OS X when
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 02/49] target-i386: Push DisasContext into load/store helpers
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
2014-01-07 20:59 ` [Qemu-devel] [PULL 01/49] exec: Delay CPU_LOG_TB_CPU until we actually execute a TB Richard Henderson
@ 2014-01-07 20:59 ` Richard Henderson
2014-01-07 20:59 ` [Qemu-devel] [PULL 03/49] target-i386: Stop encoding DisasContext.mem_index Richard Henderson
` (46 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Rather than add s->mem_index into a combined size+mem_index
argument, pass the context down. This will allow cleaning
up s->mem_index later.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 331 +++++++++++++++++++++++++-----------------------
1 file changed, 170 insertions(+), 161 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 7916e5b..8c5c16b 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -584,9 +584,9 @@ static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
}
#endif
-static inline void gen_op_lds_T0_A0(int idx)
+static inline void gen_op_lds_T0_A0(DisasContext *s, int idx)
{
- int mem_index = (idx >> 2) - 1;
+ int mem_index = (s->mem_index >> 2) - 1;
switch(idx & 3) {
case OT_BYTE:
tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
@@ -601,9 +601,9 @@ static inline void gen_op_lds_T0_A0(int idx)
}
}
-static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0)
+static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
{
- int mem_index = (idx >> 2) - 1;
+ int mem_index = (s->mem_index >> 2) - 1;
switch(idx & 3) {
case OT_BYTE:
tcg_gen_qemu_ld8u(t0, a0, mem_index);
@@ -625,24 +625,24 @@ static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0)
}
/* XXX: always use ldu or lds */
-static inline void gen_op_ld_T0_A0(int idx)
+static inline void gen_op_ld_T0_A0(DisasContext *s, int idx)
{
- gen_op_ld_v(idx, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, idx, cpu_T[0], cpu_A0);
}
-static inline void gen_op_ldu_T0_A0(int idx)
+static inline void gen_op_ldu_T0_A0(DisasContext *s, int idx)
{
- gen_op_ld_v(idx, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, idx, cpu_T[0], cpu_A0);
}
-static inline void gen_op_ld_T1_A0(int idx)
+static inline void gen_op_ld_T1_A0(DisasContext *s, int idx)
{
- gen_op_ld_v(idx, cpu_T[1], cpu_A0);
+ gen_op_ld_v(s, idx, cpu_T[1], cpu_A0);
}
-static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0)
+static inline void gen_op_st_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
{
- int mem_index = (idx >> 2) - 1;
+ int mem_index = (s->mem_index >> 2) - 1;
switch(idx & 3) {
case OT_BYTE:
tcg_gen_qemu_st8(t0, a0, mem_index);
@@ -663,14 +663,14 @@ static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0)
}
}
-static inline void gen_op_st_T0_A0(int idx)
+static inline void gen_op_st_T0_A0(DisasContext *s, int idx)
{
- gen_op_st_v(idx, cpu_T[0], cpu_A0);
+ gen_op_st_v(s, idx, cpu_T[0], cpu_A0);
}
-static inline void gen_op_st_T1_A0(int idx)
+static inline void gen_op_st_T1_A0(DisasContext *s, int idx)
{
- gen_op_st_v(idx, cpu_T[1], cpu_A0);
+ gen_op_st_v(s, idx, cpu_T[1], cpu_A0);
}
static inline void gen_jmp_im(target_ulong pc)
@@ -867,9 +867,9 @@ static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
static inline void gen_movs(DisasContext *s, int ot)
{
gen_string_movl_A0_ESI(s);
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
gen_string_movl_A0_EDI(s);
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_ESI);
gen_op_add_reg_T0(s->aflag, R_EDI);
@@ -1294,7 +1294,7 @@ static inline void gen_stos(DisasContext *s, int ot)
{
gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
gen_string_movl_A0_EDI(s);
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_EDI);
}
@@ -1302,7 +1302,7 @@ static inline void gen_stos(DisasContext *s, int ot)
static inline void gen_lods(DisasContext *s, int ot)
{
gen_string_movl_A0_ESI(s);
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
gen_op_mov_reg_T0(ot, R_EAX);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_ESI);
@@ -1311,7 +1311,7 @@ static inline void gen_lods(DisasContext *s, int ot)
static inline void gen_scas(DisasContext *s, int ot)
{
gen_string_movl_A0_EDI(s);
- gen_op_ld_T1_A0(ot + s->mem_index);
+ gen_op_ld_T1_A0(s, ot);
gen_op(s, OP_CMPL, ot, R_EAX);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_EDI);
@@ -1320,7 +1320,7 @@ static inline void gen_scas(DisasContext *s, int ot)
static inline void gen_cmps(DisasContext *s, int ot)
{
gen_string_movl_A0_EDI(s);
- gen_op_ld_T1_A0(ot + s->mem_index);
+ gen_op_ld_T1_A0(s, ot);
gen_string_movl_A0_ESI(s);
gen_op(s, OP_CMPL, ot, OR_TMP0);
gen_op_movl_T0_Dshift(ot);
@@ -1336,12 +1336,12 @@ static inline void gen_ins(DisasContext *s, int ot)
/* Note: we must do this dummy write first to be restartable in
case of page fault. */
gen_op_movl_T0_0();
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_EDI);
if (use_icount)
@@ -1353,7 +1353,7 @@ static inline void gen_outs(DisasContext *s, int ot)
if (use_icount)
gen_io_start();
gen_string_movl_A0_ESI(s);
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
@@ -1473,7 +1473,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
if (d != OR_TMP0) {
gen_op_mov_TN_reg(ot, 0, d);
} else {
- gen_op_ld_T0_A0(ot + s1->mem_index);
+ gen_op_ld_T0_A0(s1, ot);
}
switch(op) {
case OP_ADCL:
@@ -1483,7 +1483,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
if (d != OR_TMP0)
gen_op_mov_reg_T0(ot, d);
else
- gen_op_st_T0_A0(ot + s1->mem_index);
+ gen_op_st_T0_A0(s1, ot);
gen_op_update3_cc(cpu_tmp4);
set_cc_op(s1, CC_OP_ADCB + ot);
break;
@@ -1494,7 +1494,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
if (d != OR_TMP0)
gen_op_mov_reg_T0(ot, d);
else
- gen_op_st_T0_A0(ot + s1->mem_index);
+ gen_op_st_T0_A0(s1, ot);
gen_op_update3_cc(cpu_tmp4);
set_cc_op(s1, CC_OP_SBBB + ot);
break;
@@ -1503,7 +1503,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
if (d != OR_TMP0)
gen_op_mov_reg_T0(ot, d);
else
- gen_op_st_T0_A0(ot + s1->mem_index);
+ gen_op_st_T0_A0(s1, ot);
gen_op_update2_cc();
set_cc_op(s1, CC_OP_ADDB + ot);
break;
@@ -1513,7 +1513,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
if (d != OR_TMP0)
gen_op_mov_reg_T0(ot, d);
else
- gen_op_st_T0_A0(ot + s1->mem_index);
+ gen_op_st_T0_A0(s1, ot);
gen_op_update2_cc();
set_cc_op(s1, CC_OP_SUBB + ot);
break;
@@ -1523,7 +1523,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
if (d != OR_TMP0)
gen_op_mov_reg_T0(ot, d);
else
- gen_op_st_T0_A0(ot + s1->mem_index);
+ gen_op_st_T0_A0(s1, ot);
gen_op_update1_cc();
set_cc_op(s1, CC_OP_LOGICB + ot);
break;
@@ -1532,7 +1532,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
if (d != OR_TMP0)
gen_op_mov_reg_T0(ot, d);
else
- gen_op_st_T0_A0(ot + s1->mem_index);
+ gen_op_st_T0_A0(s1, ot);
gen_op_update1_cc();
set_cc_op(s1, CC_OP_LOGICB + ot);
break;
@@ -1541,7 +1541,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
if (d != OR_TMP0)
gen_op_mov_reg_T0(ot, d);
else
- gen_op_st_T0_A0(ot + s1->mem_index);
+ gen_op_st_T0_A0(s1, ot);
gen_op_update1_cc();
set_cc_op(s1, CC_OP_LOGICB + ot);
break;
@@ -1560,7 +1560,7 @@ static void gen_inc(DisasContext *s1, int ot, int d, int c)
if (d != OR_TMP0)
gen_op_mov_TN_reg(ot, 0, d);
else
- gen_op_ld_T0_A0(ot + s1->mem_index);
+ gen_op_ld_T0_A0(s1, ot);
gen_compute_eflags_c(s1, cpu_cc_src);
if (c > 0) {
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
@@ -1572,7 +1572,7 @@ static void gen_inc(DisasContext *s1, int ot, int d, int c)
if (d != OR_TMP0)
gen_op_mov_reg_T0(ot, d);
else
- gen_op_st_T0_A0(ot + s1->mem_index);
+ gen_op_st_T0_A0(s1, ot);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
}
@@ -1628,7 +1628,7 @@ static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
/* load */
if (op1 == OR_TMP0) {
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
} else {
gen_op_mov_TN_reg(ot, 0, op1);
}
@@ -1653,7 +1653,7 @@ static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
/* store */
if (op1 == OR_TMP0) {
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
} else {
gen_op_mov_reg_T0(ot, op1);
}
@@ -1668,7 +1668,7 @@ static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
/* load */
if (op1 == OR_TMP0)
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
else
gen_op_mov_TN_reg(ot, 0, op1);
@@ -1692,7 +1692,7 @@ static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
/* store */
if (op1 == OR_TMP0)
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
else
gen_op_mov_reg_T0(ot, op1);
@@ -1719,7 +1719,7 @@ static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, int is_right)
/* load */
if (op1 == OR_TMP0) {
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
} else {
gen_op_mov_TN_reg(ot, 0, op1);
}
@@ -1760,7 +1760,7 @@ static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, int is_right)
/* store */
if (op1 == OR_TMP0) {
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
} else {
gen_op_mov_reg_T0(ot, op1);
}
@@ -1809,7 +1809,7 @@ static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
/* load */
if (op1 == OR_TMP0) {
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
} else {
gen_op_mov_TN_reg(ot, 0, op1);
}
@@ -1855,7 +1855,7 @@ static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
/* store */
if (op1 == OR_TMP0) {
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
} else {
gen_op_mov_reg_T0(ot, op1);
}
@@ -1891,7 +1891,7 @@ static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
/* load */
if (op1 == OR_TMP0)
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
else
gen_op_mov_TN_reg(ot, 0, op1);
@@ -1932,7 +1932,7 @@ static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
}
/* store */
if (op1 == OR_TMP0)
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
else
gen_op_mov_reg_T0(ot, op1);
}
@@ -1946,7 +1946,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1,
/* load */
if (op1 == OR_TMP0) {
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
} else {
gen_op_mov_TN_reg(ot, 0, op1);
}
@@ -2014,7 +2014,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1,
/* store */
if (op1 == OR_TMP0) {
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
} else {
gen_op_mov_reg_T0(ot, op1);
}
@@ -2363,9 +2363,9 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
if (is_store) {
if (reg != OR_TMP0)
gen_op_mov_TN_reg(ot, 0, reg);
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
} else {
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
if (reg != OR_TMP0)
gen_op_mov_reg_T0(ot, reg);
}
@@ -2566,10 +2566,10 @@ static void gen_push_T0(DisasContext *s)
gen_op_movq_A0_reg(R_ESP);
if (s->dflag) {
gen_op_addq_A0_im(-8);
- gen_op_st_T0_A0(OT_QUAD + s->mem_index);
+ gen_op_st_T0_A0(s, OT_QUAD);
} else {
gen_op_addq_A0_im(-2);
- gen_op_st_T0_A0(OT_WORD + s->mem_index);
+ gen_op_st_T0_A0(s, OT_WORD);
}
gen_op_mov_reg_A0(2, R_ESP);
} else
@@ -2590,7 +2590,7 @@ static void gen_push_T0(DisasContext *s)
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
gen_op_addl_A0_seg(s, R_SS);
}
- gen_op_st_T0_A0(s->dflag + 1 + s->mem_index);
+ gen_op_st_T0_A0(s, s->dflag + 1);
if (s->ss32 && !s->addseg)
gen_op_mov_reg_A0(1, R_ESP);
else
@@ -2607,10 +2607,10 @@ static void gen_push_T1(DisasContext *s)
gen_op_movq_A0_reg(R_ESP);
if (s->dflag) {
gen_op_addq_A0_im(-8);
- gen_op_st_T1_A0(OT_QUAD + s->mem_index);
+ gen_op_st_T1_A0(s, OT_QUAD);
} else {
gen_op_addq_A0_im(-2);
- gen_op_st_T0_A0(OT_WORD + s->mem_index);
+ gen_op_st_T0_A0(s, OT_WORD);
}
gen_op_mov_reg_A0(2, R_ESP);
} else
@@ -2629,7 +2629,7 @@ static void gen_push_T1(DisasContext *s)
gen_op_andl_A0_ffff();
gen_op_addl_A0_seg(s, R_SS);
}
- gen_op_st_T1_A0(s->dflag + 1 + s->mem_index);
+ gen_op_st_T1_A0(s, s->dflag + 1);
if (s->ss32 && !s->addseg)
gen_op_mov_reg_A0(1, R_ESP);
@@ -2644,7 +2644,7 @@ static void gen_pop_T0(DisasContext *s)
#ifdef TARGET_X86_64
if (CODE64(s)) {
gen_op_movq_A0_reg(R_ESP);
- gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index);
+ gen_op_ld_T0_A0(s, s->dflag ? OT_QUAD : OT_WORD);
} else
#endif
{
@@ -2656,7 +2656,7 @@ static void gen_pop_T0(DisasContext *s)
gen_op_andl_A0_ffff();
gen_op_addl_A0_seg(s, R_SS);
}
- gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index);
+ gen_op_ld_T0_A0(s, s->dflag + 1);
}
}
@@ -2695,7 +2695,7 @@ static void gen_pusha(DisasContext *s)
gen_op_addl_A0_seg(s, R_SS);
for(i = 0;i < 8; i++) {
gen_op_mov_TN_reg(OT_LONG, 0, 7 - i);
- gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index);
+ gen_op_st_T0_A0(s, OT_WORD + s->dflag);
gen_op_addl_A0_im(2 << s->dflag);
}
gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
@@ -2715,7 +2715,7 @@ static void gen_popa(DisasContext *s)
for(i = 0;i < 8; i++) {
/* ESP is not reloaded */
if (i != 3) {
- gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index);
+ gen_op_ld_T0_A0(s, OT_WORD + s->dflag);
gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i);
}
gen_op_addl_A0_im(2 << s->dflag);
@@ -2739,7 +2739,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
/* push bp */
gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
if (level) {
/* XXX: must save state */
gen_helper_enter64_level(cpu_env, tcg_const_i32(level),
@@ -2764,7 +2764,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
gen_op_addl_A0_seg(s, R_SS);
/* push bp */
gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
if (level) {
/* XXX: must save state */
gen_helper_enter_level(cpu_env, tcg_const_i32(level),
@@ -2846,23 +2846,23 @@ static void gen_jmp(DisasContext *s, target_ulong eip)
gen_jmp_tb(s, eip, 0);
}
-static inline void gen_ldq_env_A0(int idx, int offset)
+static inline void gen_ldq_env_A0(DisasContext *s, int offset)
{
- int mem_index = (idx >> 2) - 1;
+ int mem_index = (s->mem_index >> 2) - 1;
tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
}
-static inline void gen_stq_env_A0(int idx, int offset)
+static inline void gen_stq_env_A0(DisasContext *s, int offset)
{
- int mem_index = (idx >> 2) - 1;
+ int mem_index = (s->mem_index >> 2) - 1;
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
}
-static inline void gen_ldo_env_A0(int idx, int offset)
+static inline void gen_ldo_env_A0(DisasContext *s, int offset)
{
- int mem_index = (idx >> 2) - 1;
+ int mem_index = (s->mem_index >> 2) - 1;
tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
@@ -2870,9 +2870,9 @@ static inline void gen_ldo_env_A0(int idx, int offset)
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
}
-static inline void gen_sto_env_A0(int idx, int offset)
+static inline void gen_sto_env_A0(DisasContext *s, int offset)
{
- int mem_index = (idx >> 2) - 1;
+ int mem_index = (s->mem_index >> 2) - 1;
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
@@ -3312,7 +3312,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod == 3)
goto illegal_op;
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
+ gen_stq_env_A0(s, offsetof(CPUX86State, fpregs[reg].mmx));
break;
case 0x1e7: /* movntdq */
case 0x02b: /* movntps */
@@ -3320,13 +3320,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod == 3)
goto illegal_op;
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
+ gen_sto_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
break;
case 0x3f0: /* lddqu */
if (mod == 3)
goto illegal_op;
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
+ gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
break;
case 0x22b: /* movntss */
case 0x32b: /* movntsd */
@@ -3334,12 +3334,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
goto illegal_op;
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
if (b1 & 1) {
- gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,
- xmm_regs[reg]));
+ gen_stq_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
} else {
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_L(0)));
- gen_op_st_T0_A0(OT_LONG + s->mem_index);
+ gen_op_st_T0_A0(s, OT_LONG);
}
break;
case 0x6e: /* movd mm, ea */
@@ -3377,7 +3376,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x6f: /* movq mm, ea */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
+ gen_ldq_env_A0(s, offsetof(CPUX86State, fpregs[reg].mmx));
} else {
rm = (modrm & 7);
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
@@ -3394,7 +3393,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x26f: /* movdqu xmm, ea */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
+ gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
} else {
rm = (modrm & 7) | REX_B(s);
gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]),
@@ -3404,7 +3403,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x210: /* movss xmm, ea */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T0_A0(OT_LONG + s->mem_index);
+ gen_op_ld_T0_A0(s, OT_LONG);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
gen_op_movl_T0_0();
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
@@ -3419,7 +3418,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x310: /* movsd xmm, ea */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
+ gen_ldq_env_A0(s, offsetof(CPUX86State,
+ xmm_regs[reg].XMM_Q(0)));
gen_op_movl_T0_0();
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
@@ -3433,7 +3433,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x112: /* movlpd */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
+ gen_ldq_env_A0(s, offsetof(CPUX86State,
+ xmm_regs[reg].XMM_Q(0)));
} else {
/* movhlps */
rm = (modrm & 7) | REX_B(s);
@@ -3444,7 +3445,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x212: /* movsldup */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
+ gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
} else {
rm = (modrm & 7) | REX_B(s);
gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
@@ -3460,7 +3461,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x312: /* movddup */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
+ gen_ldq_env_A0(s, offsetof(CPUX86State,
+ xmm_regs[reg].XMM_Q(0)));
} else {
rm = (modrm & 7) | REX_B(s);
gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
@@ -3473,7 +3475,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x116: /* movhpd */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
+ gen_ldq_env_A0(s, offsetof(CPUX86State,
+ xmm_regs[reg].XMM_Q(1)));
} else {
/* movlhps */
rm = (modrm & 7) | REX_B(s);
@@ -3484,7 +3487,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x216: /* movshdup */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
+ gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
} else {
rm = (modrm & 7) | REX_B(s);
gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
@@ -3549,7 +3552,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x27e: /* movq xmm, ea */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
+ gen_ldq_env_A0(s, offsetof(CPUX86State,
+ xmm_regs[reg].XMM_Q(0)));
} else {
rm = (modrm & 7) | REX_B(s);
gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
@@ -3560,7 +3564,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x7f: /* movq ea, mm */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
+ gen_stq_env_A0(s, offsetof(CPUX86State, fpregs[reg].mmx));
} else {
rm = (modrm & 7);
gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
@@ -3575,7 +3579,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x27f: /* movdqu ea, xmm */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
+ gen_sto_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
} else {
rm = (modrm & 7) | REX_B(s);
gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]),
@@ -3586,7 +3590,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
- gen_op_st_T0_A0(OT_LONG + s->mem_index);
+ gen_op_st_T0_A0(s, OT_LONG);
} else {
rm = (modrm & 7) | REX_B(s);
gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
@@ -3596,7 +3600,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x311: /* movsd ea, xmm */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
+ gen_stq_env_A0(s, offsetof(CPUX86State,
+ xmm_regs[reg].XMM_Q(0)));
} else {
rm = (modrm & 7) | REX_B(s);
gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
@@ -3607,7 +3612,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x113: /* movlpd */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
+ gen_stq_env_A0(s, offsetof(CPUX86State,
+ xmm_regs[reg].XMM_Q(0)));
} else {
goto illegal_op;
}
@@ -3616,7 +3622,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x117: /* movhpd */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
+ gen_stq_env_A0(s, offsetof(CPUX86State,
+ xmm_regs[reg].XMM_Q(1)));
} else {
goto illegal_op;
}
@@ -3682,7 +3689,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
op2_offset = offsetof(CPUX86State,mmx_t0);
- gen_ldq_env_A0(s->mem_index, op2_offset);
+ gen_ldq_env_A0(s, op2_offset);
} else {
rm = (modrm & 7);
op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
@@ -3727,7 +3734,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
op2_offset = offsetof(CPUX86State,xmm_t0);
- gen_ldo_env_A0(s->mem_index, op2_offset);
+ gen_ldo_env_A0(s, op2_offset);
} else {
rm = (modrm & 7) | REX_B(s);
op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
@@ -3758,9 +3765,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
if ((b >> 8) & 1) {
- gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0)));
+ gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_t0.XMM_Q(0)));
} else {
- gen_op_ld_T0_A0(OT_LONG + s->mem_index);
+ gen_op_ld_T0_A0(s, OT_LONG);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
}
op2_offset = offsetof(CPUX86State,xmm_t0);
@@ -3823,7 +3830,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x1d6: /* movq ea, xmm */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
+ gen_stq_env_A0(s, offsetof(CPUX86State,
+ xmm_regs[reg].XMM_Q(0)));
} else {
rm = (modrm & 7) | REX_B(s);
gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
@@ -3894,7 +3902,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
- gen_ldq_env_A0(s->mem_index, op2_offset +
+ gen_ldq_env_A0(s, op2_offset +
offsetof(XMMReg, XMM_Q(0)));
break;
case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
@@ -3912,10 +3920,10 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
offsetof(XMMReg, XMM_W(0)));
break;
case 0x2a: /* movntqda */
- gen_ldo_env_A0(s->mem_index, op1_offset);
+ gen_ldo_env_A0(s, op1_offset);
return;
default:
- gen_ldo_env_A0(s->mem_index, op2_offset);
+ gen_ldo_env_A0(s, op2_offset);
}
}
} else {
@@ -3925,7 +3933,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
} else {
op2_offset = offsetof(CPUX86State,mmx_t0);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_ldq_env_A0(s->mem_index, op2_offset);
+ gen_ldq_env_A0(s, op2_offset);
}
}
if (sse_fn_epp == SSE_SPECIAL) {
@@ -4490,7 +4498,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
} else {
op2_offset = offsetof(CPUX86State,xmm_t0);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_ldo_env_A0(s->mem_index, op2_offset);
+ gen_ldo_env_A0(s, op2_offset);
}
} else {
op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
@@ -4499,7 +4507,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
} else {
op2_offset = offsetof(CPUX86State,mmx_t0);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_ldq_env_A0(s->mem_index, op2_offset);
+ gen_ldq_env_A0(s, op2_offset);
}
}
val = cpu_ldub_code(env, s->pc++);
@@ -4572,14 +4580,15 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
/* specific case for SSE single instructions */
if (b1 == 2) {
/* 32 bit access */
- gen_op_ld_T0_A0(OT_LONG + s->mem_index);
+ gen_op_ld_T0_A0(s, OT_LONG);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
} else {
/* 64 bit access */
- gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0)));
+ gen_ldq_env_A0(s, offsetof(CPUX86State,
+ xmm_t0.XMM_D(0)));
}
} else {
- gen_ldo_env_A0(s->mem_index, op2_offset);
+ gen_ldo_env_A0(s, op2_offset);
}
} else {
rm = (modrm & 7) | REX_B(s);
@@ -4590,7 +4599,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
op2_offset = offsetof(CPUX86State,mmx_t0);
- gen_ldq_env_A0(s->mem_index, op2_offset);
+ gen_ldq_env_A0(s, op2_offset);
} else {
rm = (modrm & 7);
op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
@@ -4887,7 +4896,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T1_A0(ot + s->mem_index);
+ gen_op_ld_T1_A0(s, ot);
} else if (op == OP_XORL && rm == reg) {
goto xor_zero;
} else {
@@ -4975,7 +4984,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (op == 0)
s->rip_offset = insn_const_size(ot);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
} else {
gen_op_mov_TN_reg(ot, 0, rm);
}
@@ -4990,7 +4999,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 2: /* not */
tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
if (mod != 3) {
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
} else {
gen_op_mov_reg_T0(ot, rm);
}
@@ -4998,7 +5007,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 3: /* neg */
tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
if (mod != 3) {
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
} else {
gen_op_mov_reg_T0(ot, rm);
}
@@ -5187,7 +5196,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
if (op >= 2 && op != 3 && op != 5)
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
} else {
gen_op_mov_TN_reg(ot, 0, rm);
}
@@ -5218,9 +5227,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_eob(s);
break;
case 3: /* lcall Ev */
- gen_op_ld_T1_A0(ot + s->mem_index);
+ gen_op_ld_T1_A0(s, ot);
gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
- gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
+ gen_op_ldu_T0_A0(s, OT_WORD);
do_lcall:
if (s->pe && !s->vm86) {
gen_update_cc_op(s);
@@ -5244,9 +5253,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_eob(s);
break;
case 5: /* ljmp Ev */
- gen_op_ld_T1_A0(ot + s->mem_index);
+ gen_op_ld_T1_A0(s, ot);
gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
- gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
+ gen_op_ldu_T0_A0(s, OT_WORD);
do_ljmp:
if (s->pe && !s->vm86) {
gen_update_cc_op(s);
@@ -5409,9 +5418,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
gen_op_mov_TN_reg(ot, 0, reg);
- gen_op_ld_T1_A0(ot + s->mem_index);
+ gen_op_ld_T1_A0(s, ot);
gen_op_addl_T0_T1();
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
gen_op_mov_reg_T1(ot, reg);
}
gen_op_update2_cc();
@@ -5441,7 +5450,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
tcg_gen_mov_tl(a0, cpu_A0);
- gen_op_ld_v(ot + s->mem_index, t0, a0);
+ gen_op_ld_v(s, ot, t0, a0);
rm = 0; /* avoid warning */
}
label1 = gen_new_label();
@@ -5459,11 +5468,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* perform no-op store cycle like physical cpu; must be
before changing accumulator to ensure idempotency if
the store faults and the instruction is restarted */
- gen_op_st_v(ot + s->mem_index, t0, a0);
+ gen_op_st_v(s, ot, t0, a0);
gen_op_mov_reg_v(ot, R_EAX, t0);
tcg_gen_br(label2);
gen_set_label(label1);
- gen_op_st_v(ot + s->mem_index, t1, a0);
+ gen_op_st_v(s, ot, t1, a0);
}
gen_set_label(label2);
tcg_gen_mov_tl(cpu_cc_src, t0);
@@ -5671,7 +5680,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
val = insn_get(env, s, ot);
gen_op_movl_T0_im(val);
if (mod != 3)
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
else
gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s));
break;
@@ -5757,9 +5766,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
if (b & 8) {
- gen_op_lds_T0_A0(ot + s->mem_index);
+ gen_op_lds_T0_A0(s, ot);
} else {
- gen_op_ldu_T0_A0(ot + s->mem_index);
+ gen_op_ldu_T0_A0(s, ot);
}
gen_op_mov_reg_T0(d_ot, reg);
}
@@ -5810,11 +5819,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
gen_add_A0_ds_seg(s);
if ((b & 2) == 0) {
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
gen_op_mov_reg_T0(ot, R_EAX);
} else {
gen_op_mov_TN_reg(ot, 0, R_EAX);
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
}
}
break;
@@ -5838,7 +5847,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
}
gen_add_A0_ds_seg(s);
- gen_op_ldu_T0_A0(OT_BYTE + s->mem_index);
+ gen_op_ldu_T0_A0(s, OT_BYTE);
gen_op_mov_reg_T0(OT_BYTE, R_EAX);
break;
case 0xb0 ... 0xb7: /* mov R, Ib */
@@ -5895,8 +5904,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* for xchg, lock is implicit */
if (!(prefixes & PREFIX_LOCK))
gen_helper_lock();
- gen_op_ld_T1_A0(ot + s->mem_index);
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_ld_T1_A0(s, ot);
+ gen_op_st_T0_A0(s, ot);
if (!(prefixes & PREFIX_LOCK))
gen_helper_unlock();
gen_op_mov_reg_T1(ot, reg);
@@ -5926,10 +5935,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod == 3)
goto illegal_op;
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T1_A0(ot + s->mem_index);
+ gen_op_ld_T1_A0(s, ot);
gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
/* load the segment first to handle exceptions properly */
- gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
+ gen_op_ldu_T0_A0(s, OT_WORD);
gen_movl_seg_T0(s, op, pc_start - s->cs_base);
/* then put the data */
gen_op_mov_reg_T1(ot, reg);
@@ -6053,12 +6062,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
switch(op >> 4) {
case 0:
- gen_op_ld_T0_A0(OT_LONG + s->mem_index);
+ gen_op_ld_T0_A0(s, OT_LONG);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_flds_FT0(cpu_env, cpu_tmp2_i32);
break;
case 1:
- gen_op_ld_T0_A0(OT_LONG + s->mem_index);
+ gen_op_ld_T0_A0(s, OT_LONG);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
break;
@@ -6069,7 +6078,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 3:
default:
- gen_op_lds_T0_A0(OT_WORD + s->mem_index);
+ gen_op_lds_T0_A0(s, OT_WORD);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
break;
@@ -6092,12 +6101,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0:
switch(op >> 4) {
case 0:
- gen_op_ld_T0_A0(OT_LONG + s->mem_index);
+ gen_op_ld_T0_A0(s, OT_LONG);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_flds_ST0(cpu_env, cpu_tmp2_i32);
break;
case 1:
- gen_op_ld_T0_A0(OT_LONG + s->mem_index);
+ gen_op_ld_T0_A0(s, OT_LONG);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
break;
@@ -6108,7 +6117,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 3:
default:
- gen_op_lds_T0_A0(OT_WORD + s->mem_index);
+ gen_op_lds_T0_A0(s, OT_WORD);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
break;
@@ -6120,7 +6129,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 1:
gen_helper_fisttl_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(OT_LONG + s->mem_index);
+ gen_op_st_T0_A0(s, OT_LONG);
break;
case 2:
gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env);
@@ -6131,7 +6140,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
default:
gen_helper_fistt_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(OT_WORD + s->mem_index);
+ gen_op_st_T0_A0(s, OT_WORD);
break;
}
gen_helper_fpop(cpu_env);
@@ -6141,12 +6150,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0:
gen_helper_fsts_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(OT_LONG + s->mem_index);
+ gen_op_st_T0_A0(s, OT_LONG);
break;
case 1:
gen_helper_fistl_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(OT_LONG + s->mem_index);
+ gen_op_st_T0_A0(s, OT_LONG);
break;
case 2:
gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env);
@@ -6157,7 +6166,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
default:
gen_helper_fist_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(OT_WORD + s->mem_index);
+ gen_op_st_T0_A0(s, OT_WORD);
break;
}
if ((op & 7) == 3)
@@ -6171,7 +6180,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
break;
case 0x0d: /* fldcw mem */
- gen_op_ld_T0_A0(OT_WORD + s->mem_index);
+ gen_op_ld_T0_A0(s, OT_WORD);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fldcw(cpu_env, cpu_tmp2_i32);
break;
@@ -6183,7 +6192,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x0f: /* fnstcw mem */
gen_helper_fnstcw(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(OT_WORD + s->mem_index);
+ gen_op_st_T0_A0(s, OT_WORD);
break;
case 0x1d: /* fldt mem */
gen_update_cc_op(s);
@@ -6209,7 +6218,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x2f: /* fnstsw mem */
gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(OT_WORD + s->mem_index);
+ gen_op_st_T0_A0(s, OT_WORD);
break;
case 0x3c: /* fbld */
gen_update_cc_op(s);
@@ -6780,7 +6789,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_stack_A0(s);
/* pop offset */
- gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
+ gen_op_ld_T0_A0(s, 1 + s->dflag);
if (s->dflag == 0)
gen_op_andl_T0_ffff();
/* NOTE: keeping EIP updated is not a problem in case of
@@ -6788,7 +6797,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_jmp_T0();
/* pop selector */
gen_op_addl_A0_im(2 << s->dflag);
- gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
+ gen_op_ld_T0_A0(s, 1 + s->dflag);
gen_op_movl_seg_T0_vm(R_CS);
/* add stack offset */
gen_stack_update(s, val + (4 << s->dflag));
@@ -7035,7 +7044,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod != 3) {
s->rip_offset = 1;
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
} else {
gen_op_mov_TN_reg(ot, 0, rm);
}
@@ -7071,7 +7080,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot);
tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot);
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
} else {
gen_op_mov_TN_reg(ot, 0, rm);
}
@@ -7106,7 +7115,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
set_cc_op(s, CC_OP_SARB + ot);
if (op != 0) {
if (mod != 3)
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
else
gen_op_mov_reg_T0(ot, rm);
tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
@@ -7571,12 +7580,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
- gen_op_st_T0_A0(OT_WORD + s->mem_index);
+ gen_op_st_T0_A0(s, OT_WORD);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
if (!s->dflag)
gen_op_andl_T0_im(0xffffff);
- gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
+ gen_op_st_T0_A0(s, CODE64(s) + OT_LONG);
break;
case 1:
if (mod == 3) {
@@ -7634,12 +7643,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
- gen_op_st_T0_A0(OT_WORD + s->mem_index);
+ gen_op_st_T0_A0(s, OT_WORD);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
if (!s->dflag)
gen_op_andl_T0_im(0xffffff);
- gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
+ gen_op_st_T0_A0(s, CODE64(s) + OT_LONG);
}
break;
case 2: /* lgdt */
@@ -7734,9 +7743,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_svm_check_intercept(s, pc_start,
op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T1_A0(OT_WORD + s->mem_index);
+ gen_op_ld_T1_A0(s, OT_WORD);
gen_add_A0_im(s, 2);
- gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
+ gen_op_ld_T0_A0(s, CODE64(s) + OT_LONG);
if (!s->dflag)
gen_op_andl_T0_im(0xffffff);
if (op == 2) {
@@ -7855,9 +7864,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
if (d_ot == OT_QUAD) {
- gen_op_lds_T0_A0(OT_LONG + s->mem_index);
+ gen_op_lds_T0_A0(s, OT_LONG);
} else {
- gen_op_ld_T0_A0(OT_LONG + s->mem_index);
+ gen_op_ld_T0_A0(s, OT_LONG);
}
gen_op_mov_reg_T0(d_ot, reg);
}
@@ -7879,7 +7888,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = modrm & 7;
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
+ gen_op_ld_v(s, ot, t0, cpu_A0);
a0 = tcg_temp_local_new();
tcg_gen_mov_tl(a0, cpu_A0);
} else {
@@ -7897,7 +7906,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_movi_tl(t2, CC_Z);
gen_set_label(label1);
if (mod != 3) {
- gen_op_st_v(ot + s->mem_index, t0, a0);
+ gen_op_st_v(s, ot, t0, a0);
tcg_temp_free(a0);
} else {
gen_op_mov_reg_v(ot, rm, t0);
@@ -8105,12 +8114,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
if (op == 2) {
- gen_op_ld_T0_A0(OT_LONG + s->mem_index);
+ gen_op_ld_T0_A0(s, OT_LONG);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_ldmxcsr(cpu_env, cpu_tmp2_i32);
} else {
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
- gen_op_st_T0_A0(OT_LONG + s->mem_index);
+ gen_op_st_T0_A0(s, OT_LONG);
}
break;
case 5: /* lfence */
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 03/49] target-i386: Stop encoding DisasContext.mem_index
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
2014-01-07 20:59 ` [Qemu-devel] [PULL 01/49] exec: Delay CPU_LOG_TB_CPU until we actually execute a TB Richard Henderson
2014-01-07 20:59 ` [Qemu-devel] [PULL 02/49] target-i386: Push DisasContext into load/store helpers Richard Henderson
@ 2014-01-07 20:59 ` Richard Henderson
2014-01-07 20:59 ` [Qemu-devel] [PULL 04/49] target-i386: Use new tcg_gen_qemu_ld_* helpers Richard Henderson
` (45 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Now that we don't combine mem_index with operand size info,
we don't need to encode it. Which tidies many places that
access it.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 67 ++++++++++++++++++-------------------------------
1 file changed, 25 insertions(+), 42 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 8c5c16b..40e4826 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -586,7 +586,7 @@ static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
static inline void gen_op_lds_T0_A0(DisasContext *s, int idx)
{
- int mem_index = (s->mem_index >> 2) - 1;
+ int mem_index = s->mem_index;
switch(idx & 3) {
case OT_BYTE:
tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
@@ -603,7 +603,7 @@ static inline void gen_op_lds_T0_A0(DisasContext *s, int idx)
static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
{
- int mem_index = (s->mem_index >> 2) - 1;
+ int mem_index = s->mem_index;
switch(idx & 3) {
case OT_BYTE:
tcg_gen_qemu_ld8u(t0, a0, mem_index);
@@ -642,7 +642,7 @@ static inline void gen_op_ld_T1_A0(DisasContext *s, int idx)
static inline void gen_op_st_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
{
- int mem_index = (s->mem_index >> 2) - 1;
+ int mem_index = s->mem_index;
switch(idx & 3) {
case OT_BYTE:
tcg_gen_qemu_st8(t0, a0, mem_index);
@@ -2848,21 +2848,19 @@ static void gen_jmp(DisasContext *s, target_ulong eip)
static inline void gen_ldq_env_A0(DisasContext *s, int offset)
{
- int mem_index = (s->mem_index >> 2) - 1;
- tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
+ tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
}
static inline void gen_stq_env_A0(DisasContext *s, int offset)
{
- int mem_index = (s->mem_index >> 2) - 1;
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
- tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
+ tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
}
static inline void gen_ldo_env_A0(DisasContext *s, int offset)
{
- int mem_index = (s->mem_index >> 2) - 1;
+ int mem_index = s->mem_index;
tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
@@ -2872,7 +2870,7 @@ static inline void gen_ldo_env_A0(DisasContext *s, int offset)
static inline void gen_sto_env_A0(DisasContext *s, int offset)
{
- int mem_index = (s->mem_index >> 2) - 1;
+ int mem_index = s->mem_index;
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
@@ -3907,15 +3905,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
- tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, s->mem_index);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset +
offsetof(XMMReg, XMM_L(0)));
break;
case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
- tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0, s->mem_index);
tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset +
offsetof(XMMReg, XMM_W(0)));
break;
@@ -4375,8 +4371,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod == 3)
gen_op_mov_reg_T0(ot, rm);
else
- tcg_gen_qemu_st8(cpu_T[0], cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_st8(cpu_T[0], cpu_A0, s->mem_index);
break;
case 0x15: /* pextrw */
tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
@@ -4384,8 +4379,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod == 3)
gen_op_mov_reg_T0(ot, rm);
else
- tcg_gen_qemu_st16(cpu_T[0], cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_st16(cpu_T[0], cpu_A0, s->mem_index);
break;
case 0x16:
if (ot == OT_LONG) { /* pextrd */
@@ -4396,8 +4390,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod == 3)
gen_op_mov_reg_v(ot, rm, cpu_T[0]);
else
- tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_st32(cpu_T[0], cpu_A0, s->mem_index);
} else { /* pextrq */
#ifdef TARGET_X86_64
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
@@ -4407,7 +4400,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64);
else
tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
- (s->mem_index >> 2) - 1);
+ s->mem_index);
#else
goto illegal_op;
#endif
@@ -4419,15 +4412,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod == 3)
gen_op_mov_reg_T0(ot, rm);
else
- tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_st32(cpu_T[0], cpu_A0, s->mem_index);
break;
case 0x20: /* pinsrb */
if (mod == 3)
gen_op_mov_TN_reg(OT_LONG, 0, rm);
else
- tcg_gen_qemu_ld8u(cpu_T[0], cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_ld8u(cpu_T[0], cpu_A0, s->mem_index);
tcg_gen_st8_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_B(val & 15)));
break;
@@ -4437,8 +4428,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
offsetof(CPUX86State,xmm_regs[rm]
.XMM_L((val >> 6) & 3)));
} else {
- tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, s->mem_index);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
}
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
@@ -4466,8 +4456,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod == 3)
gen_op_mov_v_reg(ot, cpu_tmp0, rm);
else
- tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, s->mem_index);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
offsetof(CPUX86State,
@@ -4478,7 +4467,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm);
else
tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
- (s->mem_index >> 2) - 1);
+ s->mem_index);
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(val & 1)));
@@ -6072,8 +6061,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
break;
case 2:
- tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
gen_helper_fldl_FT0(cpu_env, cpu_tmp1_i64);
break;
case 3:
@@ -6111,8 +6099,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
break;
case 2:
- tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
gen_helper_fldl_ST0(cpu_env, cpu_tmp1_i64);
break;
case 3:
@@ -6133,8 +6120,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 2:
gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env);
- tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
break;
case 3:
default:
@@ -6159,8 +6145,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 2:
gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env);
- tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
break;
case 3:
default:
@@ -6232,14 +6217,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_helper_fpop(cpu_env);
break;
case 0x3d: /* fildll */
- tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
gen_helper_fildll_ST0(cpu_env, cpu_tmp1_i64);
break;
case 0x3f: /* fistpll */
gen_helper_fistll_ST0(cpu_tmp1_i64, cpu_env);
- tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
gen_helper_fpop(cpu_env);
break;
default:
@@ -8320,7 +8303,7 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu,
/* select memory access functions */
dc->mem_index = 0;
if (flags & HF_SOFTMMU_MASK) {
- dc->mem_index = (cpu_mmu_index(env) + 1) << 2;
+ dc->mem_index = cpu_mmu_index(env);
}
dc->cpuid_features = env->features[FEAT_1_EDX];
dc->cpuid_ext_features = env->features[FEAT_1_ECX];
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 04/49] target-i386: Use new tcg_gen_qemu_ld_* helpers
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (2 preceding siblings ...)
2014-01-07 20:59 ` [Qemu-devel] [PULL 03/49] target-i386: Stop encoding DisasContext.mem_index Richard Henderson
@ 2014-01-07 20:59 ` Richard Henderson
2014-01-07 20:59 ` [Qemu-devel] [PULL 05/49] target-i386: Use new tcg_gen_qemu_st_* helpers Richard Henderson
` (44 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
In preference to the older helpers. Loads only in this patch.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 84 ++++++++++++++++++-------------------------------
1 file changed, 31 insertions(+), 53 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 40e4826..a169524 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -586,42 +586,12 @@ static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
static inline void gen_op_lds_T0_A0(DisasContext *s, int idx)
{
- int mem_index = s->mem_index;
- switch(idx & 3) {
- case OT_BYTE:
- tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
- break;
- case OT_WORD:
- tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);
- break;
- default:
- case OT_LONG:
- tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);
- break;
- }
+ tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0, s->mem_index, idx | MO_LE | MO_SIGN);
}
static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
{
- int mem_index = s->mem_index;
- switch(idx & 3) {
- case OT_BYTE:
- tcg_gen_qemu_ld8u(t0, a0, mem_index);
- break;
- case OT_WORD:
- tcg_gen_qemu_ld16u(t0, a0, mem_index);
- break;
- case OT_LONG:
- tcg_gen_qemu_ld32u(t0, a0, mem_index);
- break;
- default:
- case OT_QUAD:
- /* Should never happen on 32-bit targets. */
-#ifdef TARGET_X86_64
- tcg_gen_qemu_ld64(t0, a0, mem_index);
-#endif
- break;
- }
+ tcg_gen_qemu_ld_tl(t0, a0, s->mem_index, idx | MO_LE);
}
/* XXX: always use ldu or lds */
@@ -2848,7 +2818,7 @@ static void gen_jmp(DisasContext *s, target_ulong eip)
static inline void gen_ldq_env_A0(DisasContext *s, int offset)
{
- tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
+ tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ);
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
}
@@ -2861,10 +2831,10 @@ static inline void gen_stq_env_A0(DisasContext *s, int offset)
static inline void gen_ldo_env_A0(DisasContext *s, int offset)
{
int mem_index = s->mem_index;
- tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
+ tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0, mem_index, MO_LEQ);
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
- tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index);
+ tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_tmp0, mem_index, MO_LEQ);
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
}
@@ -3905,13 +3875,14 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
- tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, s->mem_index);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
+ tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUL);
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset +
offsetof(XMMReg, XMM_L(0)));
break;
case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
- tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0, s->mem_index);
+ tcg_gen_qemu_ld_tl(cpu_tmp0, cpu_A0,
+ s->mem_index, MO_LEUW);
tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset +
offsetof(XMMReg, XMM_W(0)));
break;
@@ -4415,10 +4386,12 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_qemu_st32(cpu_T[0], cpu_A0, s->mem_index);
break;
case 0x20: /* pinsrb */
- if (mod == 3)
+ if (mod == 3) {
gen_op_mov_TN_reg(OT_LONG, 0, rm);
- else
- tcg_gen_qemu_ld8u(cpu_T[0], cpu_A0, s->mem_index);
+ } else {
+ tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0,
+ s->mem_index, MO_UB);
+ }
tcg_gen_st8_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_B(val & 15)));
break;
@@ -4428,8 +4401,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
offsetof(CPUX86State,xmm_regs[rm]
.XMM_L((val >> 6) & 3)));
} else {
- tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, s->mem_index);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
+ tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUL);
}
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
offsetof(CPUX86State,xmm_regs[reg]
@@ -4453,21 +4426,24 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x22:
if (ot == OT_LONG) { /* pinsrd */
- if (mod == 3)
+ if (mod == 3) {
gen_op_mov_v_reg(ot, cpu_tmp0, rm);
- else
- tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, s->mem_index);
+ } else {
+ tcg_gen_qemu_ld_tl(cpu_tmp0, cpu_A0,
+ s->mem_index, MO_LEUL);
+ }
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
offsetof(CPUX86State,
xmm_regs[reg].XMM_L(val & 3)));
} else { /* pinsrq */
#ifdef TARGET_X86_64
- if (mod == 3)
+ if (mod == 3) {
gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm);
- else
- tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
- s->mem_index);
+ } else {
+ tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0,
+ s->mem_index, MO_LEQ);
+ }
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(val & 1)));
@@ -6061,7 +6037,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
break;
case 2:
- tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
+ tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0,
+ s->mem_index, MO_LEQ);
gen_helper_fldl_FT0(cpu_env, cpu_tmp1_i64);
break;
case 3:
@@ -6099,7 +6076,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
break;
case 2:
- tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
+ tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0,
+ s->mem_index, MO_LEQ);
gen_helper_fldl_ST0(cpu_env, cpu_tmp1_i64);
break;
case 3:
@@ -6217,7 +6195,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_helper_fpop(cpu_env);
break;
case 0x3d: /* fildll */
- tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
+ tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ);
gen_helper_fildll_ST0(cpu_env, cpu_tmp1_i64);
break;
case 0x3f: /* fistpll */
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 05/49] target-i386: Use new tcg_gen_qemu_st_* helpers
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (3 preceding siblings ...)
2014-01-07 20:59 ` [Qemu-devel] [PULL 04/49] target-i386: Use new tcg_gen_qemu_ld_* helpers Richard Henderson
@ 2014-01-07 20:59 ` Richard Henderson
2014-01-07 20:59 ` [Qemu-devel] [PULL 06/49] target-i386: Replace OT_* constants with MO_* constants Richard Henderson
` (43 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
In preference to the older helpers. Stores only in this patch.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 75 ++++++++++++++++++++++---------------------------
1 file changed, 34 insertions(+), 41 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index a169524..c69fcdc 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -612,25 +612,7 @@ static inline void gen_op_ld_T1_A0(DisasContext *s, int idx)
static inline void gen_op_st_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
{
- int mem_index = s->mem_index;
- switch(idx & 3) {
- case OT_BYTE:
- tcg_gen_qemu_st8(t0, a0, mem_index);
- break;
- case OT_WORD:
- tcg_gen_qemu_st16(t0, a0, mem_index);
- break;
- case OT_LONG:
- tcg_gen_qemu_st32(t0, a0, mem_index);
- break;
- default:
- case OT_QUAD:
- /* Should never happen on 32-bit targets. */
-#ifdef TARGET_X86_64
- tcg_gen_qemu_st64(t0, a0, mem_index);
-#endif
- break;
- }
+ tcg_gen_qemu_st_tl(t0, a0, s->mem_index, idx | MO_LE);
}
static inline void gen_op_st_T0_A0(DisasContext *s, int idx)
@@ -2825,7 +2807,7 @@ static inline void gen_ldq_env_A0(DisasContext *s, int offset)
static inline void gen_stq_env_A0(DisasContext *s, int offset)
{
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
- tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
+ tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ);
}
static inline void gen_ldo_env_A0(DisasContext *s, int offset)
@@ -2842,10 +2824,10 @@ static inline void gen_sto_env_A0(DisasContext *s, int offset)
{
int mem_index = s->mem_index;
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
- tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
+ tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0, mem_index, MO_LEQ);
tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
- tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index);
+ tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_tmp0, mem_index, MO_LEQ);
}
static inline void gen_op_movo(int d_offset, int s_offset)
@@ -4339,18 +4321,22 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x14: /* pextrb */
tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_B(val & 15)));
- if (mod == 3)
+ if (mod == 3) {
gen_op_mov_reg_T0(ot, rm);
- else
- tcg_gen_qemu_st8(cpu_T[0], cpu_A0, s->mem_index);
+ } else {
+ tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
+ s->mem_index, MO_UB);
+ }
break;
case 0x15: /* pextrw */
tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_W(val & 7)));
- if (mod == 3)
+ if (mod == 3) {
gen_op_mov_reg_T0(ot, rm);
- else
- tcg_gen_qemu_st16(cpu_T[0], cpu_A0, s->mem_index);
+ } else {
+ tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
+ s->mem_index, MO_LEUW);
+ }
break;
case 0x16:
if (ot == OT_LONG) { /* pextrd */
@@ -4358,20 +4344,23 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
offsetof(CPUX86State,
xmm_regs[reg].XMM_L(val & 3)));
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- if (mod == 3)
+ if (mod == 3) {
gen_op_mov_reg_v(ot, rm, cpu_T[0]);
- else
- tcg_gen_qemu_st32(cpu_T[0], cpu_A0, s->mem_index);
+ } else {
+ tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
+ s->mem_index, MO_LEUL);
+ }
} else { /* pextrq */
#ifdef TARGET_X86_64
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(val & 1)));
- if (mod == 3)
+ if (mod == 3) {
gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64);
- else
- tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
- s->mem_index);
+ } else {
+ tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0,
+ s->mem_index, MO_LEQ);
+ }
#else
goto illegal_op;
#endif
@@ -4380,10 +4369,12 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x17: /* extractps */
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_L(val & 3)));
- if (mod == 3)
+ if (mod == 3) {
gen_op_mov_reg_T0(ot, rm);
- else
- tcg_gen_qemu_st32(cpu_T[0], cpu_A0, s->mem_index);
+ } else {
+ tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
+ s->mem_index, MO_LEUL);
+ }
break;
case 0x20: /* pinsrb */
if (mod == 3) {
@@ -6098,7 +6089,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 2:
gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env);
- tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
+ tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0,
+ s->mem_index, MO_LEQ);
break;
case 3:
default:
@@ -6123,7 +6115,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 2:
gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env);
- tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
+ tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0,
+ s->mem_index, MO_LEQ);
break;
case 3:
default:
@@ -6200,7 +6193,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x3f: /* fistpll */
gen_helper_fistll_ST0(cpu_tmp1_i64, cpu_env);
- tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
+ tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ);
gen_helper_fpop(cpu_env);
break;
default:
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 06/49] target-i386: Replace OT_* constants with MO_* constants
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (4 preceding siblings ...)
2014-01-07 20:59 ` [Qemu-devel] [PULL 05/49] target-i386: Use new tcg_gen_qemu_st_* helpers Richard Henderson
@ 2014-01-07 20:59 ` Richard Henderson
2014-01-07 20:59 ` [Qemu-devel] [PULL 07/49] target-i386: Remove gen_op_ld_T0_A0 Richard Henderson
` (42 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
The MO_8/16/32/64 constants have the same encoding and meaning
as the OT_BYTE/WORD/LONG/QUAD. Since we rely on them being the
same, for the qemu_ld/st helpers, standardize on the common names.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 714 ++++++++++++++++++++++++------------------------
1 file changed, 354 insertions(+), 360 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index c69fcdc..e7e18e3 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -163,14 +163,6 @@ enum {
JCC_LE,
};
-/* operand size */
-enum {
- OT_BYTE = 0,
- OT_WORD,
- OT_LONG,
- OT_QUAD,
-};
-
enum {
/* I386 int registers */
OR_EAX, /* MUST be even numbered */
@@ -373,24 +365,24 @@ static inline bool byte_reg_is_xH(int reg)
static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)
{
switch(ot) {
- case OT_BYTE:
+ case MO_8:
if (!byte_reg_is_xH(reg)) {
tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 8);
} else {
tcg_gen_deposit_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], t0, 8, 8);
}
break;
- case OT_WORD:
+ case MO_16:
tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 16);
break;
default: /* XXX this shouldn't be reached; abort? */
- case OT_LONG:
+ case MO_32:
/* For x86_64, this sets the higher half of register to zero.
For i386, this is equivalent to a mov. */
tcg_gen_ext32u_tl(cpu_regs[reg], t0);
break;
#ifdef TARGET_X86_64
- case OT_QUAD:
+ case MO_64:
tcg_gen_mov_tl(cpu_regs[reg], t0);
break;
#endif
@@ -410,17 +402,17 @@ static inline void gen_op_mov_reg_T1(int ot, int reg)
static inline void gen_op_mov_reg_A0(int size, int reg)
{
switch(size) {
- case OT_BYTE:
+ case MO_8:
tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_A0, 0, 16);
break;
default: /* XXX this shouldn't be reached; abort? */
- case OT_WORD:
+ case MO_16:
/* For x86_64, this sets the higher half of register to zero.
For i386, this is equivalent to a mov. */
tcg_gen_ext32u_tl(cpu_regs[reg], cpu_A0);
break;
#ifdef TARGET_X86_64
- case OT_LONG:
+ case MO_32:
tcg_gen_mov_tl(cpu_regs[reg], cpu_A0);
break;
#endif
@@ -429,7 +421,7 @@ static inline void gen_op_mov_reg_A0(int size, int reg)
static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg)
{
- if (ot == OT_BYTE && byte_reg_is_xH(reg)) {
+ if (ot == MO_8 && byte_reg_is_xH(reg)) {
tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8);
tcg_gen_ext8u_tl(t0, t0);
} else {
@@ -485,11 +477,11 @@ static inline void gen_op_jmp_T0(void)
static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
{
switch(size) {
- case OT_BYTE:
+ case MO_8:
tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16);
break;
- case OT_WORD:
+ case MO_16:
tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
/* For x86_64, this sets the higher half of register to zero.
For i386, this is equivalent to a nop. */
@@ -497,7 +489,7 @@ static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
break;
#ifdef TARGET_X86_64
- case OT_LONG:
+ case MO_32:
tcg_gen_addi_tl(cpu_regs[reg], cpu_regs[reg], val);
break;
#endif
@@ -507,11 +499,11 @@ static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
static inline void gen_op_add_reg_T0(int size, int reg)
{
switch(size) {
- case OT_BYTE:
+ case MO_8:
tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16);
break;
- case OT_WORD:
+ case MO_16:
tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
/* For x86_64, this sets the higher half of register to zero.
For i386, this is equivalent to a nop. */
@@ -519,7 +511,7 @@ static inline void gen_op_add_reg_T0(int size, int reg)
tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
break;
#ifdef TARGET_X86_64
- case OT_LONG:
+ case MO_32:
tcg_gen_add_tl(cpu_regs[reg], cpu_regs[reg], cpu_T[0]);
break;
#endif
@@ -696,14 +688,14 @@ static inline void gen_op_movl_T0_Dshift(int ot)
static TCGv gen_ext_tl(TCGv dst, TCGv src, int size, bool sign)
{
switch (size) {
- case OT_BYTE:
+ case MO_8:
if (sign) {
tcg_gen_ext8s_tl(dst, src);
} else {
tcg_gen_ext8u_tl(dst, src);
}
return dst;
- case OT_WORD:
+ case MO_16:
if (sign) {
tcg_gen_ext16s_tl(dst, src);
} else {
@@ -711,7 +703,7 @@ static TCGv gen_ext_tl(TCGv dst, TCGv src, int size, bool sign)
}
return dst;
#ifdef TARGET_X86_64
- case OT_LONG:
+ case MO_32:
if (sign) {
tcg_gen_ext32s_tl(dst, src);
} else {
@@ -751,13 +743,13 @@ static inline void gen_op_jz_ecx(int size, int label1)
static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n)
{
switch (ot) {
- case OT_BYTE:
+ case MO_8:
gen_helper_inb(v, n);
break;
- case OT_WORD:
+ case MO_16:
gen_helper_inw(v, n);
break;
- case OT_LONG:
+ case MO_32:
gen_helper_inl(v, n);
break;
}
@@ -766,13 +758,13 @@ static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n)
static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n)
{
switch (ot) {
- case OT_BYTE:
+ case MO_8:
gen_helper_outb(v, n);
break;
- case OT_WORD:
+ case MO_16:
gen_helper_outw(v, n);
break;
- case OT_LONG:
+ case MO_32:
gen_helper_outl(v, n);
break;
}
@@ -791,13 +783,13 @@ static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
state_saved = 1;
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
switch (ot) {
- case OT_BYTE:
+ case MO_8:
gen_helper_check_iob(cpu_env, cpu_tmp2_i32);
break;
- case OT_WORD:
+ case MO_16:
gen_helper_check_iow(cpu_env, cpu_tmp2_i32);
break;
- case OT_LONG:
+ case MO_32:
gen_helper_check_iol(cpu_env, cpu_tmp2_i32);
break;
}
@@ -1244,7 +1236,7 @@ static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
static inline void gen_stos(DisasContext *s, int ot)
{
- gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
+ gen_op_mov_TN_reg(MO_32, 0, R_EAX);
gen_string_movl_A0_EDI(s);
gen_op_st_T0_A0(s, ot);
gen_op_movl_T0_Dshift(ot);
@@ -1289,7 +1281,7 @@ static inline void gen_ins(DisasContext *s, int ot)
case of page fault. */
gen_op_movl_T0_0();
gen_op_st_T0_A0(s, ot);
- gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
+ gen_op_mov_TN_reg(MO_16, 1, R_EDX);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
@@ -1307,7 +1299,7 @@ static inline void gen_outs(DisasContext *s, int ot)
gen_string_movl_A0_ESI(s);
gen_op_ld_T0_A0(s, ot);
- gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
+ gen_op_mov_TN_reg(MO_16, 1, R_EDX);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
@@ -1576,7 +1568,7 @@ static void gen_shift_flags(DisasContext *s, int ot, TCGv result, TCGv shm1,
static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
int is_right, int is_arith)
{
- target_ulong mask = (ot == OT_QUAD ? 0x3f : 0x1f);
+ target_ulong mask = (ot == MO_64 ? 0x3f : 0x1f);
/* load */
if (op1 == OR_TMP0) {
@@ -1616,7 +1608,7 @@ static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
int is_right, int is_arith)
{
- int mask = (ot == OT_QUAD ? 0x3f : 0x1f);
+ int mask = (ot == MO_64 ? 0x3f : 0x1f);
/* load */
if (op1 == OR_TMP0)
@@ -1666,7 +1658,7 @@ static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2)
static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, int is_right)
{
- target_ulong mask = (ot == OT_QUAD ? 0x3f : 0x1f);
+ target_ulong mask = (ot == MO_64 ? 0x3f : 0x1f);
TCGv_i32 t0, t1;
/* load */
@@ -1679,18 +1671,18 @@ static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, int is_right)
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
switch (ot) {
- case OT_BYTE:
+ case MO_8:
/* Replicate the 8-bit input so that a 32-bit rotate works. */
tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
tcg_gen_muli_tl(cpu_T[0], cpu_T[0], 0x01010101);
goto do_long;
- case OT_WORD:
+ case MO_16:
/* Replicate the 16-bit input so that a 32-bit rotate works. */
tcg_gen_deposit_tl(cpu_T[0], cpu_T[0], cpu_T[0], 16, 16);
goto do_long;
do_long:
#ifdef TARGET_X86_64
- case OT_LONG:
+ case MO_32:
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
if (is_right) {
@@ -1756,7 +1748,7 @@ static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, int is_right)
static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
int is_right)
{
- int mask = (ot == OT_QUAD ? 0x3f : 0x1f);
+ int mask = (ot == MO_64 ? 0x3f : 0x1f);
int shift;
/* load */
@@ -1770,7 +1762,7 @@ static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
if (op2 != 0) {
switch (ot) {
#ifdef TARGET_X86_64
- case OT_LONG:
+ case MO_32:
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
if (is_right) {
tcg_gen_rotri_i32(cpu_tmp2_i32, cpu_tmp2_i32, op2);
@@ -1787,10 +1779,10 @@ static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
tcg_gen_rotli_tl(cpu_T[0], cpu_T[0], op2);
}
break;
- case OT_BYTE:
+ case MO_8:
mask = 7;
goto do_shifts;
- case OT_WORD:
+ case MO_16:
mask = 15;
do_shifts:
shift = op2 & mask;
@@ -1849,34 +1841,34 @@ static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
if (is_right) {
switch (ot) {
- case OT_BYTE:
+ case MO_8:
gen_helper_rcrb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
- case OT_WORD:
+ case MO_16:
gen_helper_rcrw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
- case OT_LONG:
+ case MO_32:
gen_helper_rcrl(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
#ifdef TARGET_X86_64
- case OT_QUAD:
+ case MO_64:
gen_helper_rcrq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
#endif
}
} else {
switch (ot) {
- case OT_BYTE:
+ case MO_8:
gen_helper_rclb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
- case OT_WORD:
+ case MO_16:
gen_helper_rclw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
- case OT_LONG:
+ case MO_32:
gen_helper_rcll(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
#ifdef TARGET_X86_64
- case OT_QUAD:
+ case MO_64:
gen_helper_rclq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
#endif
@@ -1893,7 +1885,7 @@ static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1,
bool is_right, TCGv count_in)
{
- target_ulong mask = (ot == OT_QUAD ? 63 : 31);
+ target_ulong mask = (ot == MO_64 ? 63 : 31);
TCGv count;
/* load */
@@ -1907,7 +1899,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1,
tcg_gen_andi_tl(count, count_in, mask);
switch (ot) {
- case OT_WORD:
+ case MO_16:
/* Note: we implement the Intel behaviour for shift count > 16.
This means "shrdw C, B, A" shifts A:B:A >> C. Build the B:A
portion by constructing it as a 32-bit value. */
@@ -1920,7 +1912,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1,
}
/* FALLTHRU */
#ifdef TARGET_X86_64
- case OT_LONG:
+ case MO_32:
/* Concatenate the two 32-bit values and use a 64-bit shift. */
tcg_gen_subi_tl(cpu_tmp0, count, 1);
if (is_right) {
@@ -1946,7 +1938,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1,
tcg_gen_shl_tl(cpu_T[1], cpu_T[1], cpu_tmp4);
} else {
tcg_gen_shl_tl(cpu_tmp0, cpu_T[0], cpu_tmp0);
- if (ot == OT_WORD) {
+ if (ot == MO_16) {
/* Only needed if count > 16, for Intel behaviour. */
tcg_gen_subfi_tl(cpu_tmp4, 33, count);
tcg_gen_shr_tl(cpu_tmp4, cpu_T[1], cpu_tmp4);
@@ -2329,16 +2321,16 @@ static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, int ot)
uint32_t ret;
switch(ot) {
- case OT_BYTE:
+ case MO_8:
ret = cpu_ldub_code(env, s->pc);
s->pc++;
break;
- case OT_WORD:
+ case MO_16:
ret = cpu_lduw_code(env, s->pc);
s->pc += 2;
break;
default:
- case OT_LONG:
+ case MO_32:
ret = cpu_ldl_code(env, s->pc);
s->pc += 4;
break;
@@ -2348,10 +2340,11 @@ static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, int ot)
static inline int insn_const_size(unsigned int ot)
{
- if (ot <= OT_LONG)
+ if (ot <= MO_32) {
return 1 << ot;
- else
+ } else {
return 4;
+ }
}
static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)
@@ -2518,10 +2511,10 @@ static void gen_push_T0(DisasContext *s)
gen_op_movq_A0_reg(R_ESP);
if (s->dflag) {
gen_op_addq_A0_im(-8);
- gen_op_st_T0_A0(s, OT_QUAD);
+ gen_op_st_T0_A0(s, MO_64);
} else {
gen_op_addq_A0_im(-2);
- gen_op_st_T0_A0(s, OT_WORD);
+ gen_op_st_T0_A0(s, MO_16);
}
gen_op_mov_reg_A0(2, R_ESP);
} else
@@ -2559,10 +2552,10 @@ static void gen_push_T1(DisasContext *s)
gen_op_movq_A0_reg(R_ESP);
if (s->dflag) {
gen_op_addq_A0_im(-8);
- gen_op_st_T1_A0(s, OT_QUAD);
+ gen_op_st_T1_A0(s, MO_64);
} else {
gen_op_addq_A0_im(-2);
- gen_op_st_T0_A0(s, OT_WORD);
+ gen_op_st_T0_A0(s, MO_16);
}
gen_op_mov_reg_A0(2, R_ESP);
} else
@@ -2596,7 +2589,7 @@ static void gen_pop_T0(DisasContext *s)
#ifdef TARGET_X86_64
if (CODE64(s)) {
gen_op_movq_A0_reg(R_ESP);
- gen_op_ld_T0_A0(s, s->dflag ? OT_QUAD : OT_WORD);
+ gen_op_ld_T0_A0(s, s->dflag ? MO_64 : MO_16);
} else
#endif
{
@@ -2646,11 +2639,11 @@ static void gen_pusha(DisasContext *s)
if (s->addseg)
gen_op_addl_A0_seg(s, R_SS);
for(i = 0;i < 8; i++) {
- gen_op_mov_TN_reg(OT_LONG, 0, 7 - i);
- gen_op_st_T0_A0(s, OT_WORD + s->dflag);
+ gen_op_mov_TN_reg(MO_32, 0, 7 - i);
+ gen_op_st_T0_A0(s, MO_16 + s->dflag);
gen_op_addl_A0_im(2 << s->dflag);
}
- gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
+ gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
}
/* NOTE: wrap around in 16 bit not fully handled */
@@ -2667,12 +2660,12 @@ static void gen_popa(DisasContext *s)
for(i = 0;i < 8; i++) {
/* ESP is not reloaded */
if (i != 3) {
- gen_op_ld_T0_A0(s, OT_WORD + s->dflag);
- gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i);
+ gen_op_ld_T0_A0(s, MO_16 + s->dflag);
+ gen_op_mov_reg_T0(MO_16 + s->dflag, 7 - i);
}
gen_op_addl_A0_im(2 << s->dflag);
}
- gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
+ gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
}
static void gen_enter(DisasContext *s, int esp_addend, int level)
@@ -2682,7 +2675,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
level &= 0x1f;
#ifdef TARGET_X86_64
if (CODE64(s)) {
- ot = s->dflag ? OT_QUAD : OT_WORD;
+ ot = s->dflag ? MO_64 : MO_16;
opsize = 1 << ot;
gen_op_movl_A0_reg(R_ESP);
@@ -2690,21 +2683,21 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
/* push bp */
- gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
+ gen_op_mov_TN_reg(MO_32, 0, R_EBP);
gen_op_st_T0_A0(s, ot);
if (level) {
/* XXX: must save state */
gen_helper_enter64_level(cpu_env, tcg_const_i32(level),
- tcg_const_i32((ot == OT_QUAD)),
+ tcg_const_i32((ot == MO_64)),
cpu_T[1]);
}
gen_op_mov_reg_T1(ot, R_EBP);
tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
- gen_op_mov_reg_T1(OT_QUAD, R_ESP);
+ gen_op_mov_reg_T1(MO_64, R_ESP);
} else
#endif
{
- ot = s->dflag + OT_WORD;
+ ot = s->dflag + MO_16;
opsize = 2 << s->dflag;
gen_op_movl_A0_reg(R_ESP);
@@ -2715,7 +2708,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
if (s->addseg)
gen_op_addl_A0_seg(s, R_SS);
/* push bp */
- gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
+ gen_op_mov_TN_reg(MO_32, 0, R_EBP);
gen_op_st_T0_A0(s, ot);
if (level) {
/* XXX: must save state */
@@ -2725,7 +2718,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
}
gen_op_mov_reg_T1(ot, R_EBP);
tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
- gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
+ gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
}
}
@@ -3288,18 +3281,18 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
} else {
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_L(0)));
- gen_op_st_T0_A0(s, OT_LONG);
+ gen_op_st_T0_A0(s, MO_32);
}
break;
case 0x6e: /* movd mm, ea */
#ifdef TARGET_X86_64
if (s->dflag == 2) {
- gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 0);
+ gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0);
tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
} else
#endif
{
- gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 0);
+ gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 0);
tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
offsetof(CPUX86State,fpregs[reg].mmx));
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
@@ -3309,14 +3302,14 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x16e: /* movd xmm, ea */
#ifdef TARGET_X86_64
if (s->dflag == 2) {
- gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 0);
+ gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0);
tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
offsetof(CPUX86State,xmm_regs[reg]));
gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]);
} else
#endif
{
- gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 0);
+ gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 0);
tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
offsetof(CPUX86State,xmm_regs[reg]));
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
@@ -3353,7 +3346,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x210: /* movss xmm, ea */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T0_A0(s, OT_LONG);
+ gen_op_ld_T0_A0(s, MO_32);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
gen_op_movl_T0_0();
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
@@ -3476,13 +3469,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (s->dflag == 2) {
tcg_gen_ld_i64(cpu_T[0], cpu_env,
offsetof(CPUX86State,fpregs[reg].mmx));
- gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 1);
+ gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1);
} else
#endif
{
tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));
- gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 1);
+ gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 1);
}
break;
case 0x17e: /* movd ea, xmm */
@@ -3490,13 +3483,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (s->dflag == 2) {
tcg_gen_ld_i64(cpu_T[0], cpu_env,
offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
- gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 1);
+ gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1);
} else
#endif
{
tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
- gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 1);
+ gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 1);
}
break;
case 0x27e: /* movq xmm, ea */
@@ -3540,7 +3533,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
- gen_op_st_T0_A0(s, OT_LONG);
+ gen_op_st_T0_A0(s, MO_32);
} else {
rm = (modrm & 7) | REX_B(s);
gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
@@ -3623,7 +3616,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
offsetof(CPUX86State,xmm_regs[rm]));
gen_helper_movmskps(cpu_tmp2_i32, cpu_env, cpu_ptr0);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_mov_reg_T0(OT_LONG, reg);
+ gen_op_mov_reg_T0(MO_32, reg);
break;
case 0x150: /* movmskpd */
rm = (modrm & 7) | REX_B(s);
@@ -3631,7 +3624,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
offsetof(CPUX86State,xmm_regs[rm]));
gen_helper_movmskpd(cpu_tmp2_i32, cpu_env, cpu_ptr0);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_mov_reg_T0(OT_LONG, reg);
+ gen_op_mov_reg_T0(MO_32, reg);
break;
case 0x02a: /* cvtpi2ps */
case 0x12a: /* cvtpi2pd */
@@ -3659,11 +3652,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x22a: /* cvtsi2ss */
case 0x32a: /* cvtsi2sd */
- ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
+ ot = (s->dflag == 2) ? MO_64 : MO_32;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
- if (ot == OT_LONG) {
+ if (ot == MO_32) {
SSEFunc_0_epi sse_fn_epi = sse_op_table3ai[(b >> 8) & 1];
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
sse_fn_epi(cpu_env, cpu_ptr0, cpu_tmp2_i32);
@@ -3711,13 +3704,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x32c: /* cvttsd2si */
case 0x22d: /* cvtss2si */
case 0x32d: /* cvtsd2si */
- ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
+ ot = (s->dflag == 2) ? MO_64 : MO_32;
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
if ((b >> 8) & 1) {
gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_t0.XMM_Q(0)));
} else {
- gen_op_ld_T0_A0(s, OT_LONG);
+ gen_op_ld_T0_A0(s, MO_32);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
}
op2_offset = offsetof(CPUX86State,xmm_t0);
@@ -3726,7 +3719,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
}
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
- if (ot == OT_LONG) {
+ if (ot == MO_32) {
SSEFunc_i_ep sse_fn_i_ep =
sse_op_table3bi[((b >> 7) & 2) | (b & 1)];
sse_fn_i_ep(cpu_tmp2_i32, cpu_env, cpu_ptr0);
@@ -3745,7 +3738,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0xc4: /* pinsrw */
case 0x1c4:
s->rip_offset = 1;
- gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
+ gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
val = cpu_ldub_code(env, s->pc++);
if (b1) {
val &= 7;
@@ -3761,7 +3754,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x1c5:
if (mod != 3)
goto illegal_op;
- ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
+ ot = (s->dflag == 2) ? MO_64 : MO_32;
val = cpu_ldub_code(env, s->pc++);
if (b1) {
val &= 7;
@@ -3817,7 +3810,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
}
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
reg = ((modrm >> 3) & 7) | rex_r;
- gen_op_mov_reg_T0(OT_LONG, reg);
+ gen_op_mov_reg_T0(MO_32, reg);
break;
case 0x138:
@@ -3914,20 +3907,20 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
goto illegal_op;
}
if ((b & 0xff) == 0xf0) {
- ot = OT_BYTE;
+ ot = MO_8;
} else if (s->dflag != 2) {
- ot = (s->prefix & PREFIX_DATA ? OT_WORD : OT_LONG);
+ ot = (s->prefix & PREFIX_DATA ? MO_16 : MO_32);
} else {
- ot = OT_QUAD;
+ ot = MO_64;
}
- gen_op_mov_TN_reg(OT_LONG, 0, reg);
+ gen_op_mov_TN_reg(MO_32, 0, reg);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
gen_helper_crc32(cpu_T[0], cpu_tmp2_i32,
cpu_T[0], tcg_const_i32(8 << ot));
- ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
+ ot = (s->dflag == 2) ? MO_64 : MO_32;
gen_op_mov_reg_T0(ot, reg);
break;
@@ -3946,9 +3939,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
goto illegal_op;
}
if (s->dflag != 2) {
- ot = (s->prefix & PREFIX_DATA ? OT_WORD : OT_LONG);
+ ot = (s->prefix & PREFIX_DATA ? MO_16 : MO_32);
} else {
- ot = OT_QUAD;
+ ot = MO_64;
}
/* Load the data incoming to the bswap. Note that the TCG
@@ -3959,27 +3952,27 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
} else {
switch (ot) {
- case OT_WORD:
+ case MO_16:
tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[reg]);
break;
default:
tcg_gen_ext32u_tl(cpu_T[0], cpu_regs[reg]);
break;
- case OT_QUAD:
+ case MO_64:
tcg_gen_mov_tl(cpu_T[0], cpu_regs[reg]);
break;
}
}
switch (ot) {
- case OT_WORD:
+ case MO_16:
tcg_gen_bswap16_tl(cpu_T[0], cpu_T[0]);
break;
default:
tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]);
break;
#ifdef TARGET_X86_64
- case OT_QUAD:
+ case MO_64:
tcg_gen_bswap64_tl(cpu_T[0], cpu_T[0]);
break;
#endif
@@ -3998,7 +3991,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
+ ot = s->dflag == 2 ? MO_64 : MO_32;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
tcg_gen_andc_tl(cpu_T[0], cpu_regs[s->vex_v], cpu_T[0]);
gen_op_mov_reg_T0(ot, reg);
@@ -4012,7 +4005,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
+ ot = s->dflag == 2 ? MO_64 : MO_32;
{
TCGv bound, zero;
@@ -4022,7 +4015,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_ext8u_tl(cpu_A0, cpu_regs[s->vex_v]);
tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_A0);
- bound = tcg_const_tl(ot == OT_QUAD ? 63 : 31);
+ bound = tcg_const_tl(ot == MO_64 ? 63 : 31);
zero = tcg_const_tl(0);
tcg_gen_movcond_tl(TCG_COND_LEU, cpu_T[0], cpu_A0, bound,
cpu_T[0], zero);
@@ -4052,11 +4045,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
+ ot = s->dflag == 2 ? MO_64 : MO_32;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
tcg_gen_ext8u_tl(cpu_T[1], cpu_regs[s->vex_v]);
{
- TCGv bound = tcg_const_tl(ot == OT_QUAD ? 63 : 31);
+ TCGv bound = tcg_const_tl(ot == MO_64 ? 63 : 31);
/* Note that since we're using BMILG (in order to get O
cleared) we need to store the inverse into C. */
tcg_gen_setcond_tl(TCG_COND_LT, cpu_cc_src,
@@ -4079,7 +4072,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
+ ot = s->dflag == 2 ? MO_64 : MO_32;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
switch (ot) {
default:
@@ -4091,7 +4084,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp3_i32);
break;
#ifdef TARGET_X86_64
- case OT_QUAD:
+ case MO_64:
tcg_gen_mulu2_i64(cpu_regs[s->vex_v], cpu_regs[reg],
cpu_T[0], cpu_regs[R_EDX]);
break;
@@ -4105,7 +4098,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
+ ot = s->dflag == 2 ? MO_64 : MO_32;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
/* Note that by zero-extending the mask operand, we
automatically handle zero-extending the result. */
@@ -4123,7 +4116,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
+ ot = s->dflag == 2 ? MO_64 : MO_32;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
/* Note that by zero-extending the mask operand, we
automatically handle zero-extending the result. */
@@ -4143,7 +4136,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
TCGv carry_in, carry_out, zero;
int end_op;
- ot = (s->dflag == 2 ? OT_QUAD : OT_LONG);
+ ot = (s->dflag == 2 ? MO_64 : MO_32);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
/* Re-use the carry-out from a previous round. */
@@ -4187,7 +4180,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
switch (ot) {
#ifdef TARGET_X86_64
- case OT_LONG:
+ case MO_32:
/* If we know TL is 64-bit, and we want a 32-bit
result, just do everything in 64-bit arithmetic. */
tcg_gen_ext32u_i64(cpu_regs[reg], cpu_regs[reg]);
@@ -4222,9 +4215,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = (s->dflag == 2 ? OT_QUAD : OT_LONG);
+ ot = (s->dflag == 2 ? MO_64 : MO_32);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- if (ot == OT_QUAD) {
+ if (ot == MO_64) {
tcg_gen_andi_tl(cpu_T[1], cpu_regs[s->vex_v], 63);
} else {
tcg_gen_andi_tl(cpu_T[1], cpu_regs[s->vex_v], 31);
@@ -4232,12 +4225,12 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (b == 0x1f7) {
tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
} else if (b == 0x2f7) {
- if (ot != OT_QUAD) {
+ if (ot != MO_64) {
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
}
tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
} else {
- if (ot != OT_QUAD) {
+ if (ot != MO_64) {
tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
}
tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
@@ -4254,7 +4247,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
+ ot = s->dflag == 2 ? MO_64 : MO_32;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
switch (reg & 7) {
@@ -4311,7 +4304,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
goto illegal_op;
if (sse_fn_eppi == SSE_SPECIAL) {
- ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
+ ot = (s->dflag == 2) ? MO_64 : MO_32;
rm = (modrm & 7) | REX_B(s);
if (mod != 3)
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
@@ -4339,7 +4332,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
}
break;
case 0x16:
- if (ot == OT_LONG) { /* pextrd */
+ if (ot == MO_32) { /* pextrd */
tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
offsetof(CPUX86State,
xmm_regs[reg].XMM_L(val & 3)));
@@ -4378,7 +4371,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x20: /* pinsrb */
if (mod == 3) {
- gen_op_mov_TN_reg(OT_LONG, 0, rm);
+ gen_op_mov_TN_reg(MO_32, 0, rm);
} else {
tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0,
s->mem_index, MO_UB);
@@ -4416,7 +4409,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
xmm_regs[reg].XMM_L(3)));
break;
case 0x22:
- if (ot == OT_LONG) { /* pinsrd */
+ if (ot == MO_32) { /* pinsrd */
if (mod == 3) {
gen_op_mov_v_reg(ot, cpu_tmp0, rm);
} else {
@@ -4494,10 +4487,10 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
+ ot = s->dflag == 2 ? MO_64 : MO_32;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
b = cpu_ldub_code(env, s->pc++);
- if (ot == OT_QUAD) {
+ if (ot == MO_64) {
tcg_gen_rotri_tl(cpu_T[0], cpu_T[0], b & 63);
} else {
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
@@ -4536,7 +4529,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
/* specific case for SSE single instructions */
if (b1 == 2) {
/* 32 bit access */
- gen_op_ld_T0_A0(s, OT_LONG);
+ gen_op_ld_T0_A0(s, MO_32);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
} else {
/* 64 bit access */
@@ -4819,9 +4812,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
f = (b >> 1) & 3;
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
switch(f) {
case 0: /* OP Ev, Gv */
@@ -4879,9 +4872,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
int val;
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
@@ -4907,7 +4900,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
val = insn_get(env, s, ot);
break;
case 0x83:
- val = (int8_t)insn_get(env, s, OT_BYTE);
+ val = (int8_t)insn_get(env, s, MO_8);
break;
}
gen_op_movl_T1_im(val);
@@ -4918,19 +4911,19 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/**************************/
/* inc, dec, and other misc arith */
case 0x40 ... 0x47: /* inc Gv */
- ot = dflag ? OT_LONG : OT_WORD;
+ ot = dflag ? MO_32 : MO_16;
gen_inc(s, ot, OR_EAX + (b & 7), 1);
break;
case 0x48 ... 0x4f: /* dec Gv */
- ot = dflag ? OT_LONG : OT_WORD;
+ ot = dflag ? MO_32 : MO_16;
gen_inc(s, ot, OR_EAX + (b & 7), -1);
break;
case 0xf6: /* GRP3 */
case 0xf7:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
@@ -4972,32 +4965,32 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 4: /* mul */
switch(ot) {
- case OT_BYTE:
- gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
+ case MO_8:
+ gen_op_mov_TN_reg(MO_8, 1, R_EAX);
tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(OT_WORD, R_EAX);
+ gen_op_mov_reg_T0(MO_16, R_EAX);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00);
set_cc_op(s, CC_OP_MULB);
break;
- case OT_WORD:
- gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
+ case MO_16:
+ gen_op_mov_TN_reg(MO_16, 1, R_EAX);
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(OT_WORD, R_EAX);
+ gen_op_mov_reg_T0(MO_16, R_EAX);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
- gen_op_mov_reg_T0(OT_WORD, R_EDX);
+ gen_op_mov_reg_T0(MO_16, R_EDX);
tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
set_cc_op(s, CC_OP_MULW);
break;
default:
- case OT_LONG:
+ case MO_32:
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_regs[R_EAX]);
tcg_gen_mulu2_i32(cpu_tmp2_i32, cpu_tmp3_i32,
@@ -5009,7 +5002,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
set_cc_op(s, CC_OP_MULL);
break;
#ifdef TARGET_X86_64
- case OT_QUAD:
+ case MO_64:
tcg_gen_mulu2_i64(cpu_regs[R_EAX], cpu_regs[R_EDX],
cpu_T[0], cpu_regs[R_EAX]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]);
@@ -5021,34 +5014,34 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 5: /* imul */
switch(ot) {
- case OT_BYTE:
- gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
+ case MO_8:
+ gen_op_mov_TN_reg(MO_8, 1, R_EAX);
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(OT_WORD, R_EAX);
+ gen_op_mov_reg_T0(MO_16, R_EAX);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
set_cc_op(s, CC_OP_MULB);
break;
- case OT_WORD:
- gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
+ case MO_16:
+ gen_op_mov_TN_reg(MO_16, 1, R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(OT_WORD, R_EAX);
+ gen_op_mov_reg_T0(MO_16, R_EAX);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
- gen_op_mov_reg_T0(OT_WORD, R_EDX);
+ gen_op_mov_reg_T0(MO_16, R_EDX);
set_cc_op(s, CC_OP_MULW);
break;
default:
- case OT_LONG:
+ case MO_32:
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_regs[R_EAX]);
tcg_gen_muls2_i32(cpu_tmp2_i32, cpu_tmp3_i32,
@@ -5062,7 +5055,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
set_cc_op(s, CC_OP_MULL);
break;
#ifdef TARGET_X86_64
- case OT_QUAD:
+ case MO_64:
tcg_gen_muls2_i64(cpu_regs[R_EAX], cpu_regs[R_EDX],
cpu_T[0], cpu_regs[R_EAX]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]);
@@ -5075,21 +5068,21 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 6: /* div */
switch(ot) {
- case OT_BYTE:
+ case MO_8:
gen_jmp_im(pc_start - s->cs_base);
gen_helper_divb_AL(cpu_env, cpu_T[0]);
break;
- case OT_WORD:
+ case MO_16:
gen_jmp_im(pc_start - s->cs_base);
gen_helper_divw_AX(cpu_env, cpu_T[0]);
break;
default:
- case OT_LONG:
+ case MO_32:
gen_jmp_im(pc_start - s->cs_base);
gen_helper_divl_EAX(cpu_env, cpu_T[0]);
break;
#ifdef TARGET_X86_64
- case OT_QUAD:
+ case MO_64:
gen_jmp_im(pc_start - s->cs_base);
gen_helper_divq_EAX(cpu_env, cpu_T[0]);
break;
@@ -5098,21 +5091,21 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 7: /* idiv */
switch(ot) {
- case OT_BYTE:
+ case MO_8:
gen_jmp_im(pc_start - s->cs_base);
gen_helper_idivb_AL(cpu_env, cpu_T[0]);
break;
- case OT_WORD:
+ case MO_16:
gen_jmp_im(pc_start - s->cs_base);
gen_helper_idivw_AX(cpu_env, cpu_T[0]);
break;
default:
- case OT_LONG:
+ case MO_32:
gen_jmp_im(pc_start - s->cs_base);
gen_helper_idivl_EAX(cpu_env, cpu_T[0]);
break;
#ifdef TARGET_X86_64
- case OT_QUAD:
+ case MO_64:
gen_jmp_im(pc_start - s->cs_base);
gen_helper_idivq_EAX(cpu_env, cpu_T[0]);
break;
@@ -5127,9 +5120,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xfe: /* GRP4 */
case 0xff: /* GRP5 */
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
@@ -5141,12 +5134,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (CODE64(s)) {
if (op == 2 || op == 4) {
/* operand size for jumps is 64 bit */
- ot = OT_QUAD;
+ ot = MO_64;
} else if (op == 3 || op == 5) {
- ot = dflag ? OT_LONG + (rex_w == 1) : OT_WORD;
+ ot = dflag ? MO_32 + (rex_w == 1) : MO_16;
} else if (op == 6) {
/* default push size is 64 bit */
- ot = dflag ? OT_QUAD : OT_WORD;
+ ot = dflag ? MO_64 : MO_16;
}
}
if (mod != 3) {
@@ -5184,8 +5177,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 3: /* lcall Ev */
gen_op_ld_T1_A0(s, ot);
- gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
- gen_op_ldu_T0_A0(s, OT_WORD);
+ gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
+ gen_op_ldu_T0_A0(s, MO_16);
do_lcall:
if (s->pe && !s->vm86) {
gen_update_cc_op(s);
@@ -5210,8 +5203,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 5: /* ljmp Ev */
gen_op_ld_T1_A0(s, ot);
- gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
- gen_op_ldu_T0_A0(s, OT_WORD);
+ gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
+ gen_op_ldu_T0_A0(s, MO_16);
do_ljmp:
if (s->pe && !s->vm86) {
gen_update_cc_op(s);
@@ -5237,9 +5230,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x84: /* test Ev, Gv */
case 0x85:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
@@ -5253,9 +5246,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xa8: /* test eAX, Iv */
case 0xa9:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
val = insn_get(env, s, ot);
gen_op_mov_TN_reg(ot, 0, OR_EAX);
@@ -5267,45 +5260,45 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x98: /* CWDE/CBW */
#ifdef TARGET_X86_64
if (dflag == 2) {
- gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
+ gen_op_mov_TN_reg(MO_32, 0, R_EAX);
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(OT_QUAD, R_EAX);
+ gen_op_mov_reg_T0(MO_64, R_EAX);
} else
#endif
if (dflag == 1) {
- gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
+ gen_op_mov_TN_reg(MO_16, 0, R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(OT_LONG, R_EAX);
+ gen_op_mov_reg_T0(MO_32, R_EAX);
} else {
- gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX);
+ gen_op_mov_TN_reg(MO_8, 0, R_EAX);
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(OT_WORD, R_EAX);
+ gen_op_mov_reg_T0(MO_16, R_EAX);
}
break;
case 0x99: /* CDQ/CWD */
#ifdef TARGET_X86_64
if (dflag == 2) {
- gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
+ gen_op_mov_TN_reg(MO_64, 0, R_EAX);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
- gen_op_mov_reg_T0(OT_QUAD, R_EDX);
+ gen_op_mov_reg_T0(MO_64, R_EDX);
} else
#endif
if (dflag == 1) {
- gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
+ gen_op_mov_TN_reg(MO_32, 0, R_EAX);
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
- gen_op_mov_reg_T0(OT_LONG, R_EDX);
+ gen_op_mov_reg_T0(MO_32, R_EDX);
} else {
- gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
+ gen_op_mov_TN_reg(MO_16, 0, R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
- gen_op_mov_reg_T0(OT_WORD, R_EDX);
+ gen_op_mov_reg_T0(MO_16, R_EDX);
}
break;
case 0x1af: /* imul Gv, Ev */
case 0x69: /* imul Gv, Ev, I */
case 0x6b:
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
if (b == 0x69)
@@ -5317,21 +5310,21 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
val = insn_get(env, s, ot);
gen_op_movl_T1_im(val);
} else if (b == 0x6b) {
- val = (int8_t)insn_get(env, s, OT_BYTE);
+ val = (int8_t)insn_get(env, s, MO_8);
gen_op_movl_T1_im(val);
} else {
gen_op_mov_TN_reg(ot, 1, reg);
}
switch (ot) {
#ifdef TARGET_X86_64
- case OT_QUAD:
+ case MO_64:
tcg_gen_muls2_i64(cpu_regs[reg], cpu_T[1], cpu_T[0], cpu_T[1]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[reg]);
tcg_gen_sari_tl(cpu_cc_src, cpu_cc_dst, 63);
tcg_gen_sub_tl(cpu_cc_src, cpu_cc_src, cpu_T[1]);
break;
#endif
- case OT_LONG:
+ case MO_32:
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
tcg_gen_muls2_i32(cpu_tmp2_i32, cpu_tmp3_i32,
@@ -5358,9 +5351,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x1c0:
case 0x1c1: /* xadd Ev, Gv */
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -5389,9 +5382,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
TCGv t0, t1, t2, a0;
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -5470,14 +5463,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/**************************/
/* push/pop */
case 0x50 ... 0x57: /* push */
- gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s));
+ gen_op_mov_TN_reg(MO_32, 0, (b & 7) | REX_B(s));
gen_push_T0(s);
break;
case 0x58 ... 0x5f: /* pop */
if (CODE64(s)) {
- ot = dflag ? OT_QUAD : OT_WORD;
+ ot = dflag ? MO_64 : MO_16;
} else {
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
}
gen_pop_T0(s);
/* NOTE: order is important for pop %sp */
@@ -5497,22 +5490,22 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x68: /* push Iv */
case 0x6a:
if (CODE64(s)) {
- ot = dflag ? OT_QUAD : OT_WORD;
+ ot = dflag ? MO_64 : MO_16;
} else {
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
}
if (b == 0x68)
val = insn_get(env, s, ot);
else
- val = (int8_t)insn_get(env, s, OT_BYTE);
+ val = (int8_t)insn_get(env, s, MO_8);
gen_op_movl_T0_im(val);
gen_push_T0(s);
break;
case 0x8f: /* pop Ev */
if (CODE64(s)) {
- ot = dflag ? OT_QUAD : OT_WORD;
+ ot = dflag ? MO_64 : MO_16;
} else {
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
}
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
@@ -5542,20 +5535,20 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xc9: /* leave */
/* XXX: exception not precise (ESP is updated before potential exception) */
if (CODE64(s)) {
- gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP);
- gen_op_mov_reg_T0(OT_QUAD, R_ESP);
+ gen_op_mov_TN_reg(MO_64, 0, R_EBP);
+ gen_op_mov_reg_T0(MO_64, R_ESP);
} else if (s->ss32) {
- gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
- gen_op_mov_reg_T0(OT_LONG, R_ESP);
+ gen_op_mov_TN_reg(MO_32, 0, R_EBP);
+ gen_op_mov_reg_T0(MO_32, R_ESP);
} else {
- gen_op_mov_TN_reg(OT_WORD, 0, R_EBP);
- gen_op_mov_reg_T0(OT_WORD, R_ESP);
+ gen_op_mov_TN_reg(MO_16, 0, R_EBP);
+ gen_op_mov_reg_T0(MO_16, R_ESP);
}
gen_pop_T0(s);
if (CODE64(s)) {
- ot = dflag ? OT_QUAD : OT_WORD;
+ ot = dflag ? MO_64 : MO_16;
} else {
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
}
gen_op_mov_reg_T0(ot, R_EBP);
gen_pop_update(s);
@@ -5612,9 +5605,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x88:
case 0x89: /* mov Gv, Ev */
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
@@ -5624,9 +5617,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xc6:
case 0xc7: /* mov Ev, Iv */
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
if (mod != 3) {
@@ -5643,9 +5636,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x8a:
case 0x8b: /* mov Ev, Gv */
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = OT_WORD + dflag;
+ ot = MO_16 + dflag;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
@@ -5657,7 +5650,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
reg = (modrm >> 3) & 7;
if (reg >= 6 || reg == R_CS)
goto illegal_op;
- gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
+ gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
if (reg == R_SS) {
/* if reg == SS, inhibit interrupts/trace */
@@ -5680,9 +5673,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_op_movl_T0_seg(reg);
if (mod == 3)
- ot = OT_WORD + dflag;
+ ot = MO_16 + dflag;
else
- ot = OT_WORD;
+ ot = MO_16;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
break;
@@ -5693,9 +5686,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
{
int d_ot;
/* d_ot is the size of destination */
- d_ot = dflag + OT_WORD;
+ d_ot = dflag + MO_16;
/* ot is the size of source */
- ot = (b & 1) + OT_BYTE;
+ ot = (b & 1) + MO_8;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -5704,17 +5697,17 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod == 3) {
gen_op_mov_TN_reg(ot, 0, rm);
switch(ot | (b & 8)) {
- case OT_BYTE:
+ case MO_8:
tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
break;
- case OT_BYTE | 8:
+ case MO_8 | 8:
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
break;
- case OT_WORD:
+ case MO_16:
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
break;
default:
- case OT_WORD | 8:
+ case MO_16 | 8:
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
break;
}
@@ -5732,7 +5725,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x8d: /* lea */
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
if (mod == 3)
@@ -5744,7 +5737,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
s->addseg = 0;
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
s->addseg = val;
- gen_op_mov_reg_A0(ot - OT_WORD, reg);
+ gen_op_mov_reg_A0(ot - MO_16, reg);
break;
case 0xa0: /* mov EAX, Ov */
@@ -5755,9 +5748,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
target_ulong offset_addr;
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
#ifdef TARGET_X86_64
if (s->aflag == 2) {
offset_addr = cpu_ldq_code(env, s->pc);
@@ -5767,9 +5760,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
#endif
{
if (s->aflag) {
- offset_addr = insn_get(env, s, OT_LONG);
+ offset_addr = insn_get(env, s, MO_32);
} else {
- offset_addr = insn_get(env, s, OT_WORD);
+ offset_addr = insn_get(env, s, MO_16);
}
gen_op_movl_A0_im(offset_addr);
}
@@ -5787,14 +5780,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
#ifdef TARGET_X86_64
if (s->aflag == 2) {
gen_op_movq_A0_reg(R_EBX);
- gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
+ gen_op_mov_TN_reg(MO_64, 0, R_EAX);
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
} else
#endif
{
gen_op_movl_A0_reg(R_EBX);
- gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
+ gen_op_mov_TN_reg(MO_32, 0, R_EAX);
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
if (s->aflag == 0)
@@ -5803,13 +5796,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
}
gen_add_A0_ds_seg(s);
- gen_op_ldu_T0_A0(s, OT_BYTE);
- gen_op_mov_reg_T0(OT_BYTE, R_EAX);
+ gen_op_ldu_T0_A0(s, MO_8);
+ gen_op_mov_reg_T0(MO_8, R_EAX);
break;
case 0xb0 ... 0xb7: /* mov R, Ib */
- val = insn_get(env, s, OT_BYTE);
+ val = insn_get(env, s, MO_8);
gen_op_movl_T0_im(val);
- gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s));
+ gen_op_mov_reg_T0(MO_8, (b & 7) | REX_B(s));
break;
case 0xb8 ... 0xbf: /* mov R, Iv */
#ifdef TARGET_X86_64
@@ -5820,11 +5813,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
s->pc += 8;
reg = (b & 7) | REX_B(s);
gen_movtl_T0_im(tmp);
- gen_op_mov_reg_T0(OT_QUAD, reg);
+ gen_op_mov_reg_T0(MO_64, reg);
} else
#endif
{
- ot = dflag ? OT_LONG : OT_WORD;
+ ot = dflag ? MO_32 : MO_16;
val = insn_get(env, s, ot);
reg = (b & 7) | REX_B(s);
gen_op_movl_T0_im(val);
@@ -5834,16 +5827,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x91 ... 0x97: /* xchg R, EAX */
do_xchg_reg_eax:
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
reg = (b & 7) | REX_B(s);
rm = R_EAX;
goto do_xchg_reg;
case 0x86:
case 0x87: /* xchg Ev, Gv */
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -5884,7 +5877,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x1b5: /* lgs Gv */
op = R_GS;
do_lxx:
- ot = dflag ? OT_LONG : OT_WORD;
+ ot = dflag ? MO_32 : MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -5892,9 +5885,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
gen_op_ld_T1_A0(s, ot);
- gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
+ gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
/* load the segment first to handle exceptions properly */
- gen_op_ldu_T0_A0(s, OT_WORD);
+ gen_op_ldu_T0_A0(s, MO_16);
gen_movl_seg_T0(s, op, pc_start - s->cs_base);
/* then put the data */
gen_op_mov_reg_T1(ot, reg);
@@ -5913,9 +5906,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
grp2:
{
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
@@ -5969,7 +5962,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
op = 1;
shift = 0;
do_shiftd:
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
@@ -6018,12 +6011,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
switch(op >> 4) {
case 0:
- gen_op_ld_T0_A0(s, OT_LONG);
+ gen_op_ld_T0_A0(s, MO_32);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_flds_FT0(cpu_env, cpu_tmp2_i32);
break;
case 1:
- gen_op_ld_T0_A0(s, OT_LONG);
+ gen_op_ld_T0_A0(s, MO_32);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
break;
@@ -6034,7 +6027,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 3:
default:
- gen_op_lds_T0_A0(s, OT_WORD);
+ gen_op_lds_T0_A0(s, MO_16);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
break;
@@ -6057,12 +6050,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0:
switch(op >> 4) {
case 0:
- gen_op_ld_T0_A0(s, OT_LONG);
+ gen_op_ld_T0_A0(s, MO_32);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_flds_ST0(cpu_env, cpu_tmp2_i32);
break;
case 1:
- gen_op_ld_T0_A0(s, OT_LONG);
+ gen_op_ld_T0_A0(s, MO_32);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
break;
@@ -6073,7 +6066,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 3:
default:
- gen_op_lds_T0_A0(s, OT_WORD);
+ gen_op_lds_T0_A0(s, MO_16);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
break;
@@ -6085,7 +6078,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 1:
gen_helper_fisttl_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, OT_LONG);
+ gen_op_st_T0_A0(s, MO_32);
break;
case 2:
gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env);
@@ -6096,7 +6089,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
default:
gen_helper_fistt_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, OT_WORD);
+ gen_op_st_T0_A0(s, MO_16);
break;
}
gen_helper_fpop(cpu_env);
@@ -6106,12 +6099,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0:
gen_helper_fsts_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, OT_LONG);
+ gen_op_st_T0_A0(s, MO_32);
break;
case 1:
gen_helper_fistl_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, OT_LONG);
+ gen_op_st_T0_A0(s, MO_32);
break;
case 2:
gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env);
@@ -6122,7 +6115,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
default:
gen_helper_fist_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, OT_WORD);
+ gen_op_st_T0_A0(s, MO_16);
break;
}
if ((op & 7) == 3)
@@ -6136,7 +6129,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
break;
case 0x0d: /* fldcw mem */
- gen_op_ld_T0_A0(s, OT_WORD);
+ gen_op_ld_T0_A0(s, MO_16);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fldcw(cpu_env, cpu_tmp2_i32);
break;
@@ -6148,7 +6141,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x0f: /* fnstcw mem */
gen_helper_fnstcw(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, OT_WORD);
+ gen_op_st_T0_A0(s, MO_16);
break;
case 0x1d: /* fldt mem */
gen_update_cc_op(s);
@@ -6174,7 +6167,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x2f: /* fnstsw mem */
gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, OT_WORD);
+ gen_op_st_T0_A0(s, MO_16);
break;
case 0x3c: /* fbld */
gen_update_cc_op(s);
@@ -6459,7 +6452,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0:
gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_mov_reg_T0(OT_WORD, R_EAX);
+ gen_op_mov_reg_T0(MO_16, R_EAX);
break;
default:
goto illegal_op;
@@ -6517,9 +6510,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xa4: /* movsS */
case 0xa5:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
@@ -6531,9 +6524,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xaa: /* stosS */
case 0xab:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
@@ -6544,9 +6537,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xac: /* lodsS */
case 0xad:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
} else {
@@ -6556,9 +6549,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xae: /* scasS */
case 0xaf:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
if (prefixes & PREFIX_REPNZ) {
gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
} else if (prefixes & PREFIX_REPZ) {
@@ -6571,9 +6564,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xa6: /* cmpsS */
case 0xa7:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
if (prefixes & PREFIX_REPNZ) {
gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
} else if (prefixes & PREFIX_REPZ) {
@@ -6585,10 +6578,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x6c: /* insS */
case 0x6d:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag ? OT_LONG : OT_WORD;
- gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
+ ot = dflag ? MO_32 : MO_16;
+ gen_op_mov_TN_reg(MO_16, 0, R_EDX);
gen_op_andl_T0_ffff();
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
@@ -6604,10 +6597,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x6e: /* outsS */
case 0x6f:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag ? OT_LONG : OT_WORD;
- gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
+ ot = dflag ? MO_32 : MO_16;
+ gen_op_mov_TN_reg(MO_16, 0, R_EDX);
gen_op_andl_T0_ffff();
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes) | 4);
@@ -6627,9 +6620,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xe4:
case 0xe5:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag ? OT_LONG : OT_WORD;
+ ot = dflag ? MO_32 : MO_16;
val = cpu_ldub_code(env, s->pc++);
gen_op_movl_T0_im(val);
gen_check_io(s, ot, pc_start - s->cs_base,
@@ -6647,9 +6640,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xe6:
case 0xe7:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag ? OT_LONG : OT_WORD;
+ ot = dflag ? MO_32 : MO_16;
val = cpu_ldub_code(env, s->pc++);
gen_op_movl_T0_im(val);
gen_check_io(s, ot, pc_start - s->cs_base,
@@ -6669,10 +6662,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xec:
case 0xed:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag ? OT_LONG : OT_WORD;
- gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
+ ot = dflag ? MO_32 : MO_16;
+ gen_op_mov_TN_reg(MO_16, 0, R_EDX);
gen_op_andl_T0_ffff();
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
@@ -6689,10 +6682,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xee:
case 0xef:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag ? OT_LONG : OT_WORD;
- gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
+ ot = dflag ? MO_32 : MO_16;
+ gen_op_mov_TN_reg(MO_16, 0, R_EDX);
gen_op_andl_T0_ffff();
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes));
@@ -6786,9 +6779,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xe8: /* call im */
{
if (dflag)
- tval = (int32_t)insn_get(env, s, OT_LONG);
+ tval = (int32_t)insn_get(env, s, MO_32);
else
- tval = (int16_t)insn_get(env, s, OT_WORD);
+ tval = (int16_t)insn_get(env, s, MO_16);
next_eip = s->pc - s->cs_base;
tval += next_eip;
if (s->dflag == 0)
@@ -6806,9 +6799,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (CODE64(s))
goto illegal_op;
- ot = dflag ? OT_LONG : OT_WORD;
+ ot = dflag ? MO_32 : MO_16;
offset = insn_get(env, s, ot);
- selector = insn_get(env, s, OT_WORD);
+ selector = insn_get(env, s, MO_16);
gen_op_movl_T0_im(selector);
gen_op_movl_T1_imu(offset);
@@ -6816,9 +6809,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto do_lcall;
case 0xe9: /* jmp im */
if (dflag)
- tval = (int32_t)insn_get(env, s, OT_LONG);
+ tval = (int32_t)insn_get(env, s, MO_32);
else
- tval = (int16_t)insn_get(env, s, OT_WORD);
+ tval = (int16_t)insn_get(env, s, MO_16);
tval += s->pc - s->cs_base;
if (s->dflag == 0)
tval &= 0xffff;
@@ -6832,29 +6825,29 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (CODE64(s))
goto illegal_op;
- ot = dflag ? OT_LONG : OT_WORD;
+ ot = dflag ? MO_32 : MO_16;
offset = insn_get(env, s, ot);
- selector = insn_get(env, s, OT_WORD);
+ selector = insn_get(env, s, MO_16);
gen_op_movl_T0_im(selector);
gen_op_movl_T1_imu(offset);
}
goto do_ljmp;
case 0xeb: /* jmp Jb */
- tval = (int8_t)insn_get(env, s, OT_BYTE);
+ tval = (int8_t)insn_get(env, s, MO_8);
tval += s->pc - s->cs_base;
if (s->dflag == 0)
tval &= 0xffff;
gen_jmp(s, tval);
break;
case 0x70 ... 0x7f: /* jcc Jb */
- tval = (int8_t)insn_get(env, s, OT_BYTE);
+ tval = (int8_t)insn_get(env, s, MO_8);
goto do_jcc;
case 0x180 ... 0x18f: /* jcc Jv */
if (dflag) {
- tval = (int32_t)insn_get(env, s, OT_LONG);
+ tval = (int32_t)insn_get(env, s, MO_32);
} else {
- tval = (int16_t)insn_get(env, s, OT_WORD);
+ tval = (int16_t)insn_get(env, s, MO_16);
}
do_jcc:
next_eip = s->pc - s->cs_base;
@@ -6867,13 +6860,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x190 ... 0x19f: /* setcc Gv */
modrm = cpu_ldub_code(env, s->pc++);
gen_setcc1(s, b, cpu_T[0]);
- gen_ldst_modrm(env, s, modrm, OT_BYTE, OR_TMP0, 1);
+ gen_ldst_modrm(env, s, modrm, MO_8, OR_TMP0, 1);
break;
case 0x140 ... 0x14f: /* cmov Gv, Ev */
if (!(s->cpuid_features & CPUID_CMOV)) {
goto illegal_op;
}
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
gen_cmovcc1(env, s, ot, b, modrm, reg);
@@ -6952,7 +6945,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x9e: /* sahf */
if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
goto illegal_op;
- gen_op_mov_TN_reg(OT_BYTE, 0, R_AH);
+ gen_op_mov_TN_reg(MO_8, 0, R_AH);
gen_compute_eflags(s);
tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C);
@@ -6964,7 +6957,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_compute_eflags(s);
/* Note: gen_compute_eflags() only gives the condition codes */
tcg_gen_ori_tl(cpu_T[0], cpu_cc_src, 0x02);
- gen_op_mov_reg_T0(OT_BYTE, R_AH);
+ gen_op_mov_reg_T0(MO_8, R_AH);
break;
case 0xf5: /* cmc */
gen_compute_eflags(s);
@@ -6990,7 +6983,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/************************/
/* bit operations */
case 0x1ba: /* bt/bts/btr/btc Gv, im */
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
op = (modrm >> 3) & 7;
mod = (modrm >> 6) & 3;
@@ -7021,12 +7014,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x1bb: /* btc */
op = 3;
do_btx:
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
- gen_op_mov_TN_reg(OT_LONG, 1, reg);
+ gen_op_mov_TN_reg(MO_32, 1, reg);
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
/* specific case: we need to add a displacement */
@@ -7078,7 +7071,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x1bc: /* bsf / tzcnt */
case 0x1bd: /* bsr / lzcnt */
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
@@ -7277,7 +7270,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x62: /* bound */
if (CODE64(s))
goto illegal_op;
- ot = dflag ? OT_LONG : OT_WORD;
+ ot = dflag ? MO_32 : MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = (modrm >> 3) & 7;
mod = (modrm >> 6) & 3;
@@ -7287,7 +7280,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
gen_jmp_im(pc_start - s->cs_base);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
- if (ot == OT_WORD) {
+ if (ot == MO_16) {
gen_helper_boundw(cpu_env, cpu_A0, cpu_tmp2_i32);
} else {
gen_helper_boundl(cpu_env, cpu_A0, cpu_tmp2_i32);
@@ -7297,16 +7290,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
reg = (b & 7) | REX_B(s);
#ifdef TARGET_X86_64
if (dflag == 2) {
- gen_op_mov_TN_reg(OT_QUAD, 0, reg);
+ gen_op_mov_TN_reg(MO_64, 0, reg);
tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(OT_QUAD, reg);
+ gen_op_mov_reg_T0(MO_64, reg);
} else
#endif
{
- gen_op_mov_TN_reg(OT_LONG, 0, reg);
+ gen_op_mov_TN_reg(MO_32, 0, reg);
tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(OT_LONG, reg);
+ gen_op_mov_reg_T0(MO_32, reg);
}
break;
case 0xd6: /* salc */
@@ -7314,7 +7307,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_compute_eflags_c(s, cpu_T[0]);
tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(OT_BYTE, R_EAX);
+ gen_op_mov_reg_T0(MO_8, R_EAX);
break;
case 0xe0: /* loopnz */
case 0xe1: /* loopz */
@@ -7323,7 +7316,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
{
int l1, l2, l3;
- tval = (int8_t)insn_get(env, s, OT_BYTE);
+ tval = (int8_t)insn_get(env, s, MO_8);
next_eip = s->pc - s->cs_base;
tval += next_eip;
if (s->dflag == 0)
@@ -7464,7 +7457,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector));
- ot = OT_WORD;
+ ot = MO_16;
if (mod == 3)
ot += s->dflag;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
@@ -7476,7 +7469,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE);
- gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
+ gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
gen_jmp_im(pc_start - s->cs_base);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_lldt(cpu_env, cpu_tmp2_i32);
@@ -7487,7 +7480,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector));
- ot = OT_WORD;
+ ot = MO_16;
if (mod == 3)
ot += s->dflag;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
@@ -7499,7 +7492,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE);
- gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
+ gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
gen_jmp_im(pc_start - s->cs_base);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_ltr(cpu_env, cpu_tmp2_i32);
@@ -7509,7 +7502,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 5: /* verw */
if (!s->pe || s->vm86)
goto illegal_op;
- gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
+ gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
gen_update_cc_op(s);
if (op == 4) {
gen_helper_verr(cpu_env, cpu_T[0]);
@@ -7534,12 +7527,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
- gen_op_st_T0_A0(s, OT_WORD);
+ gen_op_st_T0_A0(s, MO_16);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
if (!s->dflag)
gen_op_andl_T0_im(0xffffff);
- gen_op_st_T0_A0(s, CODE64(s) + OT_LONG);
+ gen_op_st_T0_A0(s, CODE64(s) + MO_32);
break;
case 1:
if (mod == 3) {
@@ -7597,12 +7590,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
- gen_op_st_T0_A0(s, OT_WORD);
+ gen_op_st_T0_A0(s, MO_16);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
if (!s->dflag)
gen_op_andl_T0_im(0xffffff);
- gen_op_st_T0_A0(s, CODE64(s) + OT_LONG);
+ gen_op_st_T0_A0(s, CODE64(s) + MO_32);
}
break;
case 2: /* lgdt */
@@ -7697,9 +7690,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_svm_check_intercept(s, pc_start,
op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T1_A0(s, OT_WORD);
+ gen_op_ld_T1_A0(s, MO_16);
gen_add_A0_im(s, 2);
- gen_op_ld_T0_A0(s, CODE64(s) + OT_LONG);
+ gen_op_ld_T0_A0(s, CODE64(s) + MO_32);
if (!s->dflag)
gen_op_andl_T0_im(0xffffff);
if (op == 2) {
@@ -7718,14 +7711,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
#else
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]));
#endif
- gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 1);
+ gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 1);
break;
case 6: /* lmsw */
if (s->cpl != 0) {
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
- gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
+ gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
gen_helper_lmsw(cpu_env, cpu_T[0]);
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
@@ -7802,7 +7795,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (CODE64(s)) {
int d_ot;
/* d_ot is the size of destination */
- d_ot = dflag + OT_WORD;
+ d_ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
@@ -7810,17 +7803,18 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
if (mod == 3) {
- gen_op_mov_TN_reg(OT_LONG, 0, rm);
+ gen_op_mov_TN_reg(MO_32, 0, rm);
/* sign extend */
- if (d_ot == OT_QUAD)
+ if (d_ot == MO_64) {
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
+ }
gen_op_mov_reg_T0(d_ot, reg);
} else {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- if (d_ot == OT_QUAD) {
- gen_op_lds_T0_A0(s, OT_LONG);
+ if (d_ot == MO_64) {
+ gen_op_lds_T0_A0(s, MO_32);
} else {
- gen_op_ld_T0_A0(s, OT_LONG);
+ gen_op_ld_T0_A0(s, MO_32);
}
gen_op_mov_reg_T0(d_ot, reg);
}
@@ -7835,7 +7829,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
t0 = tcg_temp_local_new();
t1 = tcg_temp_local_new();
t2 = tcg_temp_local_new();
- ot = OT_WORD;
+ ot = MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = (modrm >> 3) & 7;
mod = (modrm >> 6) & 3;
@@ -7880,10 +7874,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
TCGv t0;
if (!s->pe || s->vm86)
goto illegal_op;
- ot = dflag ? OT_LONG : OT_WORD;
+ ot = dflag ? MO_32 : MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
- gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
+ gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
t0 = tcg_temp_local_new();
gen_update_cc_op(s);
if (b == 0x102) {
@@ -7937,9 +7931,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
reg = ((modrm >> 3) & 7) | rex_r;
if (CODE64(s))
- ot = OT_QUAD;
+ ot = MO_64;
else
- ot = OT_LONG;
+ ot = MO_32;
if ((prefixes & PREFIX_LOCK) && (reg == 0) &&
(s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) {
reg = 8;
@@ -7982,9 +7976,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
reg = ((modrm >> 3) & 7) | rex_r;
if (CODE64(s))
- ot = OT_QUAD;
+ ot = MO_64;
else
- ot = OT_LONG;
+ ot = MO_32;
/* XXX: do it dynamically with CR4.DE bit */
if (reg == 4 || reg == 5 || reg >= 8)
goto illegal_op;
@@ -8016,7 +8010,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x1c3: /* MOVNTI reg, mem */
if (!(s->cpuid_features & CPUID_SSE2))
goto illegal_op;
- ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
+ ot = s->dflag == 2 ? MO_64 : MO_32;
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
if (mod == 3)
@@ -8068,12 +8062,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
if (op == 2) {
- gen_op_ld_T0_A0(s, OT_LONG);
+ gen_op_ld_T0_A0(s, MO_32);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_ldmxcsr(cpu_env, cpu_tmp2_i32);
} else {
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
- gen_op_st_T0_A0(s, OT_LONG);
+ gen_op_st_T0_A0(s, MO_32);
}
break;
case 5: /* lfence */
@@ -8126,11 +8120,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
reg = ((modrm >> 3) & 7) | rex_r;
if (s->prefix & PREFIX_DATA)
- ot = OT_WORD;
+ ot = MO_16;
else if (s->dflag != 2)
- ot = OT_LONG;
+ ot = MO_32;
else
- ot = OT_QUAD;
+ ot = MO_64;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
gen_helper_popcnt(cpu_T[0], cpu_env, cpu_T[0], tcg_const_i32(ot));
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 07/49] target-i386: Remove gen_op_ld_T0_A0
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (5 preceding siblings ...)
2014-01-07 20:59 ` [Qemu-devel] [PULL 06/49] target-i386: Replace OT_* constants with MO_* constants Richard Henderson
@ 2014-01-07 20:59 ` Richard Henderson
2014-01-07 20:59 ` [Qemu-devel] [PULL 08/49] target-i386: Remove gen_op_ldu_T0_A0 Richard Henderson
` (41 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Propagate its definition into all users.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 77 +++++++++++++++++++++++--------------------------
1 file changed, 36 insertions(+), 41 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index e7e18e3..6efe64f 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -586,12 +586,6 @@ static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
tcg_gen_qemu_ld_tl(t0, a0, s->mem_index, idx | MO_LE);
}
-/* XXX: always use ldu or lds */
-static inline void gen_op_ld_T0_A0(DisasContext *s, int idx)
-{
- gen_op_ld_v(s, idx, cpu_T[0], cpu_A0);
-}
-
static inline void gen_op_ldu_T0_A0(DisasContext *s, int idx)
{
gen_op_ld_v(s, idx, cpu_T[0], cpu_A0);
@@ -811,7 +805,7 @@ static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
static inline void gen_movs(DisasContext *s, int ot)
{
gen_string_movl_A0_ESI(s);
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
gen_string_movl_A0_EDI(s);
gen_op_st_T0_A0(s, ot);
gen_op_movl_T0_Dshift(ot);
@@ -1246,7 +1240,7 @@ static inline void gen_stos(DisasContext *s, int ot)
static inline void gen_lods(DisasContext *s, int ot)
{
gen_string_movl_A0_ESI(s);
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
gen_op_mov_reg_T0(ot, R_EAX);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_ESI);
@@ -1297,7 +1291,7 @@ static inline void gen_outs(DisasContext *s, int ot)
if (use_icount)
gen_io_start();
gen_string_movl_A0_ESI(s);
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
gen_op_mov_TN_reg(MO_16, 1, R_EDX);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
@@ -1417,7 +1411,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
if (d != OR_TMP0) {
gen_op_mov_TN_reg(ot, 0, d);
} else {
- gen_op_ld_T0_A0(s1, ot);
+ gen_op_ld_v(s1, ot, cpu_T[0], cpu_A0);
}
switch(op) {
case OP_ADCL:
@@ -1501,10 +1495,11 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
/* if d == OR_TMP0, it means memory operand (address in A0) */
static void gen_inc(DisasContext *s1, int ot, int d, int c)
{
- if (d != OR_TMP0)
+ if (d != OR_TMP0) {
gen_op_mov_TN_reg(ot, 0, d);
- else
- gen_op_ld_T0_A0(s1, ot);
+ } else {
+ gen_op_ld_v(s1, ot, cpu_T[0], cpu_A0);
+ }
gen_compute_eflags_c(s1, cpu_cc_src);
if (c > 0) {
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
@@ -1572,7 +1567,7 @@ static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
/* load */
if (op1 == OR_TMP0) {
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_mov_TN_reg(ot, 0, op1);
}
@@ -1612,7 +1607,7 @@ static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
/* load */
if (op1 == OR_TMP0)
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
else
gen_op_mov_TN_reg(ot, 0, op1);
@@ -1663,7 +1658,7 @@ static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, int is_right)
/* load */
if (op1 == OR_TMP0) {
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_mov_TN_reg(ot, 0, op1);
}
@@ -1753,7 +1748,7 @@ static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
/* load */
if (op1 == OR_TMP0) {
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_mov_TN_reg(ot, 0, op1);
}
@@ -1835,7 +1830,7 @@ static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
/* load */
if (op1 == OR_TMP0)
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
else
gen_op_mov_TN_reg(ot, 0, op1);
@@ -1890,7 +1885,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1,
/* load */
if (op1 == OR_TMP0) {
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_mov_TN_reg(ot, 0, op1);
}
@@ -2309,7 +2304,7 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
gen_op_mov_TN_reg(ot, 0, reg);
gen_op_st_T0_A0(s, ot);
} else {
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
if (reg != OR_TMP0)
gen_op_mov_reg_T0(ot, reg);
}
@@ -2589,7 +2584,7 @@ static void gen_pop_T0(DisasContext *s)
#ifdef TARGET_X86_64
if (CODE64(s)) {
gen_op_movq_A0_reg(R_ESP);
- gen_op_ld_T0_A0(s, s->dflag ? MO_64 : MO_16);
+ gen_op_ld_v(s, s->dflag ? MO_64 : MO_16, cpu_T[0], cpu_A0);
} else
#endif
{
@@ -2601,7 +2596,7 @@ static void gen_pop_T0(DisasContext *s)
gen_op_andl_A0_ffff();
gen_op_addl_A0_seg(s, R_SS);
}
- gen_op_ld_T0_A0(s, s->dflag + 1);
+ gen_op_ld_v(s, s->dflag + 1, cpu_T[0], cpu_A0);
}
}
@@ -2660,7 +2655,7 @@ static void gen_popa(DisasContext *s)
for(i = 0;i < 8; i++) {
/* ESP is not reloaded */
if (i != 3) {
- gen_op_ld_T0_A0(s, MO_16 + s->dflag);
+ gen_op_ld_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0);
gen_op_mov_reg_T0(MO_16 + s->dflag, 7 - i);
}
gen_op_addl_A0_im(2 << s->dflag);
@@ -3346,7 +3341,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x210: /* movss xmm, ea */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T0_A0(s, MO_32);
+ gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
gen_op_movl_T0_0();
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
@@ -3710,7 +3705,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if ((b >> 8) & 1) {
gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_t0.XMM_Q(0)));
} else {
- gen_op_ld_T0_A0(s, MO_32);
+ gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
}
op2_offset = offsetof(CPUX86State,xmm_t0);
@@ -4529,7 +4524,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
/* specific case for SSE single instructions */
if (b1 == 2) {
/* 32 bit access */
- gen_op_ld_T0_A0(s, MO_32);
+ gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
} else {
/* 64 bit access */
@@ -4933,7 +4928,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (op == 0)
s->rip_offset = insn_const_size(ot);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_mov_TN_reg(ot, 0, rm);
}
@@ -5145,7 +5140,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
if (op >= 2 && op != 3 && op != 5)
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_mov_TN_reg(ot, 0, rm);
}
@@ -5768,7 +5763,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
gen_add_A0_ds_seg(s);
if ((b & 2) == 0) {
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
gen_op_mov_reg_T0(ot, R_EAX);
} else {
gen_op_mov_TN_reg(ot, 0, R_EAX);
@@ -6011,12 +6006,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
switch(op >> 4) {
case 0:
- gen_op_ld_T0_A0(s, MO_32);
+ gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_flds_FT0(cpu_env, cpu_tmp2_i32);
break;
case 1:
- gen_op_ld_T0_A0(s, MO_32);
+ gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
break;
@@ -6050,12 +6045,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0:
switch(op >> 4) {
case 0:
- gen_op_ld_T0_A0(s, MO_32);
+ gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_flds_ST0(cpu_env, cpu_tmp2_i32);
break;
case 1:
- gen_op_ld_T0_A0(s, MO_32);
+ gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
break;
@@ -6129,7 +6124,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
break;
case 0x0d: /* fldcw mem */
- gen_op_ld_T0_A0(s, MO_16);
+ gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fldcw(cpu_env, cpu_tmp2_i32);
break;
@@ -6736,7 +6731,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_stack_A0(s);
/* pop offset */
- gen_op_ld_T0_A0(s, 1 + s->dflag);
+ gen_op_ld_v(s, 1 + s->dflag, cpu_T[0], cpu_A0);
if (s->dflag == 0)
gen_op_andl_T0_ffff();
/* NOTE: keeping EIP updated is not a problem in case of
@@ -6744,7 +6739,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_jmp_T0();
/* pop selector */
gen_op_addl_A0_im(2 << s->dflag);
- gen_op_ld_T0_A0(s, 1 + s->dflag);
+ gen_op_ld_v(s, 1 + s->dflag, cpu_T[0], cpu_A0);
gen_op_movl_seg_T0_vm(R_CS);
/* add stack offset */
gen_stack_update(s, val + (4 << s->dflag));
@@ -6991,7 +6986,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod != 3) {
s->rip_offset = 1;
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_mov_TN_reg(ot, 0, rm);
}
@@ -7027,7 +7022,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot);
tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot);
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_mov_TN_reg(ot, 0, rm);
}
@@ -7692,7 +7687,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
gen_op_ld_T1_A0(s, MO_16);
gen_add_A0_im(s, 2);
- gen_op_ld_T0_A0(s, CODE64(s) + MO_32);
+ gen_op_ld_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
if (!s->dflag)
gen_op_andl_T0_im(0xffffff);
if (op == 2) {
@@ -7814,7 +7809,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (d_ot == MO_64) {
gen_op_lds_T0_A0(s, MO_32);
} else {
- gen_op_ld_T0_A0(s, MO_32);
+ gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
}
gen_op_mov_reg_T0(d_ot, reg);
}
@@ -8062,7 +8057,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
if (op == 2) {
- gen_op_ld_T0_A0(s, MO_32);
+ gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_ldmxcsr(cpu_env, cpu_tmp2_i32);
} else {
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 08/49] target-i386: Remove gen_op_ldu_T0_A0
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (6 preceding siblings ...)
2014-01-07 20:59 ` [Qemu-devel] [PULL 07/49] target-i386: Remove gen_op_ld_T0_A0 Richard Henderson
@ 2014-01-07 20:59 ` Richard Henderson
2014-01-07 20:59 ` [Qemu-devel] [PULL 09/49] target-i386: Remove gen_op_ld_T1_A0 Richard Henderson
` (40 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Propagate its definition into all users.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 15 +++++----------
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 6efe64f..97bbc1f 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -586,11 +586,6 @@ static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
tcg_gen_qemu_ld_tl(t0, a0, s->mem_index, idx | MO_LE);
}
-static inline void gen_op_ldu_T0_A0(DisasContext *s, int idx)
-{
- gen_op_ld_v(s, idx, cpu_T[0], cpu_A0);
-}
-
static inline void gen_op_ld_T1_A0(DisasContext *s, int idx)
{
gen_op_ld_v(s, idx, cpu_T[1], cpu_A0);
@@ -5173,7 +5168,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 3: /* lcall Ev */
gen_op_ld_T1_A0(s, ot);
gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
- gen_op_ldu_T0_A0(s, MO_16);
+ gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
do_lcall:
if (s->pe && !s->vm86) {
gen_update_cc_op(s);
@@ -5199,7 +5194,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 5: /* ljmp Ev */
gen_op_ld_T1_A0(s, ot);
gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
- gen_op_ldu_T0_A0(s, MO_16);
+ gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
do_ljmp:
if (s->pe && !s->vm86) {
gen_update_cc_op(s);
@@ -5712,7 +5707,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (b & 8) {
gen_op_lds_T0_A0(s, ot);
} else {
- gen_op_ldu_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
}
gen_op_mov_reg_T0(d_ot, reg);
}
@@ -5791,7 +5786,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
}
gen_add_A0_ds_seg(s);
- gen_op_ldu_T0_A0(s, MO_8);
+ gen_op_ld_v(s, MO_8, cpu_T[0], cpu_A0);
gen_op_mov_reg_T0(MO_8, R_EAX);
break;
case 0xb0 ... 0xb7: /* mov R, Ib */
@@ -5882,7 +5877,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_ld_T1_A0(s, ot);
gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
/* load the segment first to handle exceptions properly */
- gen_op_ldu_T0_A0(s, MO_16);
+ gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
gen_movl_seg_T0(s, op, pc_start - s->cs_base);
/* then put the data */
gen_op_mov_reg_T1(ot, reg);
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 09/49] target-i386: Remove gen_op_ld_T1_A0
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (7 preceding siblings ...)
2014-01-07 20:59 ` [Qemu-devel] [PULL 08/49] target-i386: Remove gen_op_ldu_T0_A0 Richard Henderson
@ 2014-01-07 20:59 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 10/49] target-i386: Remove gen_op_lds_T0_A0 Richard Henderson
` (39 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Propagate its definition into all users.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 23 +++++++++--------------
1 file changed, 9 insertions(+), 14 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 97bbc1f..b747e99 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -586,11 +586,6 @@ static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
tcg_gen_qemu_ld_tl(t0, a0, s->mem_index, idx | MO_LE);
}
-static inline void gen_op_ld_T1_A0(DisasContext *s, int idx)
-{
- gen_op_ld_v(s, idx, cpu_T[1], cpu_A0);
-}
-
static inline void gen_op_st_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
{
tcg_gen_qemu_st_tl(t0, a0, s->mem_index, idx | MO_LE);
@@ -1244,7 +1239,7 @@ static inline void gen_lods(DisasContext *s, int ot)
static inline void gen_scas(DisasContext *s, int ot)
{
gen_string_movl_A0_EDI(s);
- gen_op_ld_T1_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
gen_op(s, OP_CMPL, ot, R_EAX);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_EDI);
@@ -1253,7 +1248,7 @@ static inline void gen_scas(DisasContext *s, int ot)
static inline void gen_cmps(DisasContext *s, int ot)
{
gen_string_movl_A0_EDI(s);
- gen_op_ld_T1_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
gen_string_movl_A0_ESI(s);
gen_op(s, OP_CMPL, ot, OR_TMP0);
gen_op_movl_T0_Dshift(ot);
@@ -4835,7 +4830,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T1_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
} else if (op == OP_XORL && rm == reg) {
goto xor_zero;
} else {
@@ -5166,7 +5161,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_eob(s);
break;
case 3: /* lcall Ev */
- gen_op_ld_T1_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
do_lcall:
@@ -5192,7 +5187,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_eob(s);
break;
case 5: /* ljmp Ev */
- gen_op_ld_T1_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
do_ljmp:
@@ -5357,7 +5352,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
gen_op_mov_TN_reg(ot, 0, reg);
- gen_op_ld_T1_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
gen_op_addl_T0_T1();
gen_op_st_T0_A0(s, ot);
gen_op_mov_reg_T1(ot, reg);
@@ -5843,7 +5838,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* for xchg, lock is implicit */
if (!(prefixes & PREFIX_LOCK))
gen_helper_lock();
- gen_op_ld_T1_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
gen_op_st_T0_A0(s, ot);
if (!(prefixes & PREFIX_LOCK))
gen_helper_unlock();
@@ -5874,7 +5869,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod == 3)
goto illegal_op;
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T1_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
/* load the segment first to handle exceptions properly */
gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
@@ -7680,7 +7675,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_svm_check_intercept(s, pc_start,
op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T1_A0(s, MO_16);
+ gen_op_ld_v(s, MO_16, cpu_T[1], cpu_A0);
gen_add_A0_im(s, 2);
gen_op_ld_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
if (!s->dflag)
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 10/49] target-i386: Remove gen_op_lds_T0_A0
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (8 preceding siblings ...)
2014-01-07 20:59 ` [Qemu-devel] [PULL 09/49] target-i386: Remove gen_op_ld_T1_A0 Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 11/49] target-i386: Introduce gen_op_st_rm_T0_A0 Richard Henderson
` (38 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Replace its users by gen_op_ld_v with the MO_SIGN bit set.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index b747e99..1e425e3 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -576,11 +576,6 @@ static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
}
#endif
-static inline void gen_op_lds_T0_A0(DisasContext *s, int idx)
-{
- tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0, s->mem_index, idx | MO_LE | MO_SIGN);
-}
-
static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
{
tcg_gen_qemu_ld_tl(t0, a0, s->mem_index, idx | MO_LE);
@@ -5700,7 +5695,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
if (b & 8) {
- gen_op_lds_T0_A0(s, ot);
+ gen_op_ld_v(s, ot | MO_SIGN, cpu_T[0], cpu_A0);
} else {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
}
@@ -6012,7 +6007,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 3:
default:
- gen_op_lds_T0_A0(s, MO_16);
+ gen_op_ld_v(s, MO_SW, cpu_T[0], cpu_A0);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
break;
@@ -6051,7 +6046,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 3:
default:
- gen_op_lds_T0_A0(s, MO_16);
+ gen_op_ld_v(s, MO_SW, cpu_T[0], cpu_A0);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
break;
@@ -7797,7 +7792,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
if (d_ot == MO_64) {
- gen_op_lds_T0_A0(s, MO_32);
+ gen_op_ld_v(s, MO_32 | MO_SIGN, cpu_T[0], cpu_A0);
} else {
gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
}
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 11/49] target-i386: Introduce gen_op_st_rm_T0_A0
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (9 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 10/49] target-i386: Remove gen_op_lds_T0_A0 Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 12/49] target-i386: Remove gen_op_st_T0_A0 Richard Henderson
` (37 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Too many places have the same test vs OR_TMP0 to indicate
a write back to memory. Hoist that to a subroutine.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 85 ++++++++++++++-----------------------------------
1 file changed, 24 insertions(+), 61 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 1e425e3..f531726 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -596,6 +596,15 @@ static inline void gen_op_st_T1_A0(DisasContext *s, int idx)
gen_op_st_v(s, idx, cpu_T[1], cpu_A0);
}
+static inline void gen_op_st_rm_T0_A0(DisasContext *s, int idx, int d)
+{
+ if (d == OR_TMP0) {
+ gen_op_st_T0_A0(s, idx);
+ } else {
+ gen_op_mov_reg_T0(idx, d);
+ }
+}
+
static inline void gen_jmp_im(target_ulong pc)
{
tcg_gen_movi_tl(cpu_tmp0, pc);
@@ -1403,10 +1412,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
gen_compute_eflags_c(s1, cpu_tmp4);
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
- if (d != OR_TMP0)
- gen_op_mov_reg_T0(ot, d);
- else
- gen_op_st_T0_A0(s1, ot);
+ gen_op_st_rm_T0_A0(s1, ot, d);
gen_op_update3_cc(cpu_tmp4);
set_cc_op(s1, CC_OP_ADCB + ot);
break;
@@ -1414,57 +1420,39 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
gen_compute_eflags_c(s1, cpu_tmp4);
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
- if (d != OR_TMP0)
- gen_op_mov_reg_T0(ot, d);
- else
- gen_op_st_T0_A0(s1, ot);
+ gen_op_st_rm_T0_A0(s1, ot, d);
gen_op_update3_cc(cpu_tmp4);
set_cc_op(s1, CC_OP_SBBB + ot);
break;
case OP_ADDL:
gen_op_addl_T0_T1();
- if (d != OR_TMP0)
- gen_op_mov_reg_T0(ot, d);
- else
- gen_op_st_T0_A0(s1, ot);
+ gen_op_st_rm_T0_A0(s1, ot, d);
gen_op_update2_cc();
set_cc_op(s1, CC_OP_ADDB + ot);
break;
case OP_SUBL:
tcg_gen_mov_tl(cpu_cc_srcT, cpu_T[0]);
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- if (d != OR_TMP0)
- gen_op_mov_reg_T0(ot, d);
- else
- gen_op_st_T0_A0(s1, ot);
+ gen_op_st_rm_T0_A0(s1, ot, d);
gen_op_update2_cc();
set_cc_op(s1, CC_OP_SUBB + ot);
break;
default:
case OP_ANDL:
tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- if (d != OR_TMP0)
- gen_op_mov_reg_T0(ot, d);
- else
- gen_op_st_T0_A0(s1, ot);
+ gen_op_st_rm_T0_A0(s1, ot, d);
gen_op_update1_cc();
set_cc_op(s1, CC_OP_LOGICB + ot);
break;
case OP_ORL:
tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- if (d != OR_TMP0)
- gen_op_mov_reg_T0(ot, d);
- else
- gen_op_st_T0_A0(s1, ot);
+ gen_op_st_rm_T0_A0(s1, ot, d);
gen_op_update1_cc();
set_cc_op(s1, CC_OP_LOGICB + ot);
break;
case OP_XORL:
tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- if (d != OR_TMP0)
- gen_op_mov_reg_T0(ot, d);
- else
- gen_op_st_T0_A0(s1, ot);
+ gen_op_st_rm_T0_A0(s1, ot, d);
gen_op_update1_cc();
set_cc_op(s1, CC_OP_LOGICB + ot);
break;
@@ -1493,10 +1481,7 @@ static void gen_inc(DisasContext *s1, int ot, int d, int c)
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1);
set_cc_op(s1, CC_OP_DECB + ot);
}
- if (d != OR_TMP0)
- gen_op_mov_reg_T0(ot, d);
- else
- gen_op_st_T0_A0(s1, ot);
+ gen_op_st_rm_T0_A0(s1, ot, d);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
}
@@ -1576,11 +1561,7 @@ static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
}
/* store */
- if (op1 == OR_TMP0) {
- gen_op_st_T0_A0(s, ot);
- } else {
- gen_op_mov_reg_T0(ot, op1);
- }
+ gen_op_st_rm_T0_A0(s, ot, op1);
gen_shift_flags(s, ot, cpu_T[0], cpu_tmp0, cpu_T[1], is_right);
}
@@ -1615,11 +1596,8 @@ static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
}
/* store */
- if (op1 == OR_TMP0)
- gen_op_st_T0_A0(s, ot);
- else
- gen_op_mov_reg_T0(ot, op1);
-
+ gen_op_st_rm_T0_A0(s, ot, op1);
+
/* update eflags if non zero shift */
if (op2 != 0) {
tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
@@ -1683,11 +1661,7 @@ static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, int is_right)
}
/* store */
- if (op1 == OR_TMP0) {
- gen_op_st_T0_A0(s, ot);
- } else {
- gen_op_mov_reg_T0(ot, op1);
- }
+ gen_op_st_rm_T0_A0(s, ot, op1);
/* We'll need the flags computed into CC_SRC. */
gen_compute_eflags(s);
@@ -1778,11 +1752,7 @@ static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
}
/* store */
- if (op1 == OR_TMP0) {
- gen_op_st_T0_A0(s, ot);
- } else {
- gen_op_mov_reg_T0(ot, op1);
- }
+ gen_op_st_rm_T0_A0(s, ot, op1);
if (op2 != 0) {
/* Compute the flags into CC_SRC. */
@@ -1855,10 +1825,7 @@ static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
}
}
/* store */
- if (op1 == OR_TMP0)
- gen_op_st_T0_A0(s, ot);
- else
- gen_op_mov_reg_T0(ot, op1);
+ gen_op_st_rm_T0_A0(s, ot, op1);
}
/* XXX: add faster immediate case */
@@ -1937,11 +1904,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1,
}
/* store */
- if (op1 == OR_TMP0) {
- gen_op_st_T0_A0(s, ot);
- } else {
- gen_op_mov_reg_T0(ot, op1);
- }
+ gen_op_st_rm_T0_A0(s, ot, op1);
gen_shift_flags(s, ot, cpu_T[0], cpu_tmp0, count, is_right);
tcg_temp_free(count);
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 12/49] target-i386: Remove gen_op_st_T0_A0
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (10 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 11/49] target-i386: Introduce gen_op_st_rm_T0_A0 Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 13/49] target-i386: Remove gen_op_st_T1_A0 Richard Henderson
` (36 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Propagate its definition into all users.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 83 ++++++++++++++++++++++++-------------------------
1 file changed, 40 insertions(+), 43 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index f531726..725d5ec 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -586,11 +586,6 @@ static inline void gen_op_st_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
tcg_gen_qemu_st_tl(t0, a0, s->mem_index, idx | MO_LE);
}
-static inline void gen_op_st_T0_A0(DisasContext *s, int idx)
-{
- gen_op_st_v(s, idx, cpu_T[0], cpu_A0);
-}
-
static inline void gen_op_st_T1_A0(DisasContext *s, int idx)
{
gen_op_st_v(s, idx, cpu_T[1], cpu_A0);
@@ -599,7 +594,7 @@ static inline void gen_op_st_T1_A0(DisasContext *s, int idx)
static inline void gen_op_st_rm_T0_A0(DisasContext *s, int idx, int d)
{
if (d == OR_TMP0) {
- gen_op_st_T0_A0(s, idx);
+ gen_op_st_v(s, idx, cpu_T[0], cpu_A0);
} else {
gen_op_mov_reg_T0(idx, d);
}
@@ -801,7 +796,7 @@ static inline void gen_movs(DisasContext *s, int ot)
gen_string_movl_A0_ESI(s);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
gen_string_movl_A0_EDI(s);
- gen_op_st_T0_A0(s, ot);
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_ESI);
gen_op_add_reg_T0(s->aflag, R_EDI);
@@ -1226,7 +1221,7 @@ static inline void gen_stos(DisasContext *s, int ot)
{
gen_op_mov_TN_reg(MO_32, 0, R_EAX);
gen_string_movl_A0_EDI(s);
- gen_op_st_T0_A0(s, ot);
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_EDI);
}
@@ -1268,12 +1263,12 @@ static inline void gen_ins(DisasContext *s, int ot)
/* Note: we must do this dummy write first to be restartable in
case of page fault. */
gen_op_movl_T0_0();
- gen_op_st_T0_A0(s, ot);
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_mov_TN_reg(MO_16, 1, R_EDX);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, ot);
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_EDI);
if (use_icount)
@@ -2250,7 +2245,7 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
if (is_store) {
if (reg != OR_TMP0)
gen_op_mov_TN_reg(ot, 0, reg);
- gen_op_st_T0_A0(s, ot);
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
if (reg != OR_TMP0)
@@ -2454,10 +2449,10 @@ static void gen_push_T0(DisasContext *s)
gen_op_movq_A0_reg(R_ESP);
if (s->dflag) {
gen_op_addq_A0_im(-8);
- gen_op_st_T0_A0(s, MO_64);
+ gen_op_st_v(s, MO_64, cpu_T[0], cpu_A0);
} else {
gen_op_addq_A0_im(-2);
- gen_op_st_T0_A0(s, MO_16);
+ gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
}
gen_op_mov_reg_A0(2, R_ESP);
} else
@@ -2478,7 +2473,7 @@ static void gen_push_T0(DisasContext *s)
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
gen_op_addl_A0_seg(s, R_SS);
}
- gen_op_st_T0_A0(s, s->dflag + 1);
+ gen_op_st_v(s, s->dflag + 1, cpu_T[0], cpu_A0);
if (s->ss32 && !s->addseg)
gen_op_mov_reg_A0(1, R_ESP);
else
@@ -2498,7 +2493,7 @@ static void gen_push_T1(DisasContext *s)
gen_op_st_T1_A0(s, MO_64);
} else {
gen_op_addq_A0_im(-2);
- gen_op_st_T0_A0(s, MO_16);
+ gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
}
gen_op_mov_reg_A0(2, R_ESP);
} else
@@ -2583,7 +2578,7 @@ static void gen_pusha(DisasContext *s)
gen_op_addl_A0_seg(s, R_SS);
for(i = 0;i < 8; i++) {
gen_op_mov_TN_reg(MO_32, 0, 7 - i);
- gen_op_st_T0_A0(s, MO_16 + s->dflag);
+ gen_op_st_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0);
gen_op_addl_A0_im(2 << s->dflag);
}
gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
@@ -2627,7 +2622,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
/* push bp */
gen_op_mov_TN_reg(MO_32, 0, R_EBP);
- gen_op_st_T0_A0(s, ot);
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
if (level) {
/* XXX: must save state */
gen_helper_enter64_level(cpu_env, tcg_const_i32(level),
@@ -2652,7 +2647,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
gen_op_addl_A0_seg(s, R_SS);
/* push bp */
gen_op_mov_TN_reg(MO_32, 0, R_EBP);
- gen_op_st_T0_A0(s, ot);
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
if (level) {
/* XXX: must save state */
gen_helper_enter_level(cpu_env, tcg_const_i32(level),
@@ -3224,7 +3219,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
} else {
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_L(0)));
- gen_op_st_T0_A0(s, MO_32);
+ gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
}
break;
case 0x6e: /* movd mm, ea */
@@ -3476,7 +3471,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
- gen_op_st_T0_A0(s, MO_32);
+ gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
} else {
rm = (modrm & 7) | REX_B(s);
gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
@@ -4891,7 +4886,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 2: /* not */
tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
if (mod != 3) {
- gen_op_st_T0_A0(s, ot);
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_mov_reg_T0(ot, rm);
}
@@ -4899,7 +4894,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 3: /* neg */
tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
if (mod != 3) {
- gen_op_st_T0_A0(s, ot);
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_mov_reg_T0(ot, rm);
}
@@ -5312,7 +5307,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_mov_TN_reg(ot, 0, reg);
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
gen_op_addl_T0_T1();
- gen_op_st_T0_A0(s, ot);
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_mov_reg_T1(ot, reg);
}
gen_op_update2_cc();
@@ -5571,10 +5566,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
val = insn_get(env, s, ot);
gen_op_movl_T0_im(val);
- if (mod != 3)
- gen_op_st_T0_A0(s, ot);
- else
+ if (mod != 3) {
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
+ } else {
gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s));
+ }
break;
case 0x8a:
case 0x8b: /* mov Ev, Gv */
@@ -5715,7 +5711,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_mov_reg_T0(ot, R_EAX);
} else {
gen_op_mov_TN_reg(ot, 0, R_EAX);
- gen_op_st_T0_A0(s, ot);
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
}
}
break;
@@ -5797,7 +5793,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (!(prefixes & PREFIX_LOCK))
gen_helper_lock();
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
- gen_op_st_T0_A0(s, ot);
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
if (!(prefixes & PREFIX_LOCK))
gen_helper_unlock();
gen_op_mov_reg_T1(ot, reg);
@@ -6021,7 +6017,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 1:
gen_helper_fisttl_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, MO_32);
+ gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
break;
case 2:
gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env);
@@ -6032,7 +6028,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
default:
gen_helper_fistt_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, MO_16);
+ gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
break;
}
gen_helper_fpop(cpu_env);
@@ -6042,12 +6038,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0:
gen_helper_fsts_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, MO_32);
+ gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
break;
case 1:
gen_helper_fistl_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, MO_32);
+ gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
break;
case 2:
gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env);
@@ -6058,7 +6054,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
default:
gen_helper_fist_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, MO_16);
+ gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
break;
}
if ((op & 7) == 3)
@@ -6084,7 +6080,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x0f: /* fnstcw mem */
gen_helper_fnstcw(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, MO_16);
+ gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
break;
case 0x1d: /* fldt mem */
gen_update_cc_op(s);
@@ -6110,7 +6106,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x2f: /* fnstsw mem */
gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, MO_16);
+ gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
break;
case 0x3c: /* fbld */
gen_update_cc_op(s);
@@ -7004,10 +7000,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
set_cc_op(s, CC_OP_SARB + ot);
if (op != 0) {
- if (mod != 3)
- gen_op_st_T0_A0(s, ot);
- else
+ if (mod != 3) {
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
+ } else {
gen_op_mov_reg_T0(ot, rm);
+ }
tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
tcg_gen_movi_tl(cpu_cc_dst, 0);
}
@@ -7470,12 +7467,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
- gen_op_st_T0_A0(s, MO_16);
+ gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
if (!s->dflag)
gen_op_andl_T0_im(0xffffff);
- gen_op_st_T0_A0(s, CODE64(s) + MO_32);
+ gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
break;
case 1:
if (mod == 3) {
@@ -7533,12 +7530,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
- gen_op_st_T0_A0(s, MO_16);
+ gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
if (!s->dflag)
gen_op_andl_T0_im(0xffffff);
- gen_op_st_T0_A0(s, CODE64(s) + MO_32);
+ gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
}
break;
case 2: /* lgdt */
@@ -8010,7 +8007,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_helper_ldmxcsr(cpu_env, cpu_tmp2_i32);
} else {
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
- gen_op_st_T0_A0(s, MO_32);
+ gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
}
break;
case 5: /* lfence */
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 13/49] target-i386: Remove gen_op_st_T1_A0
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (11 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 12/49] target-i386: Remove gen_op_st_T0_A0 Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 14/49] target-i386: Fix typo in gen_push_T1 Richard Henderson
` (35 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Propagate its definition into all users.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 9 ++-------
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 725d5ec..a1a23a6 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -586,11 +586,6 @@ static inline void gen_op_st_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
tcg_gen_qemu_st_tl(t0, a0, s->mem_index, idx | MO_LE);
}
-static inline void gen_op_st_T1_A0(DisasContext *s, int idx)
-{
- gen_op_st_v(s, idx, cpu_T[1], cpu_A0);
-}
-
static inline void gen_op_st_rm_T0_A0(DisasContext *s, int idx, int d)
{
if (d == OR_TMP0) {
@@ -2490,7 +2485,7 @@ static void gen_push_T1(DisasContext *s)
gen_op_movq_A0_reg(R_ESP);
if (s->dflag) {
gen_op_addq_A0_im(-8);
- gen_op_st_T1_A0(s, MO_64);
+ gen_op_st_v(s, MO_64, cpu_T[1], cpu_A0);
} else {
gen_op_addq_A0_im(-2);
gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
@@ -2512,7 +2507,7 @@ static void gen_push_T1(DisasContext *s)
gen_op_andl_A0_ffff();
gen_op_addl_A0_seg(s, R_SS);
}
- gen_op_st_T1_A0(s, s->dflag + 1);
+ gen_op_st_v(s, s->dflag + 1, cpu_T[1], cpu_A0);
if (s->ss32 && !s->addseg)
gen_op_mov_reg_A0(1, R_ESP);
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 14/49] target-i386: Fix typo in gen_push_T1
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (12 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 13/49] target-i386: Remove gen_op_st_T1_A0 Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 15/49] target-i386: Tidy mov[sz][bw] Richard Henderson
` (34 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
By inspection, obviously we should be storing T[1] not T[0].
This could only happen for x86_64 in 64-bit mode with 0x66
prefix to call insn -- i.e. never.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index a1a23a6..9205b72 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -2488,7 +2488,7 @@ static void gen_push_T1(DisasContext *s)
gen_op_st_v(s, MO_64, cpu_T[1], cpu_A0);
} else {
gen_op_addq_A0_im(-2);
- gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
+ gen_op_st_v(s, MO_16, cpu_T[1], cpu_A0);
}
gen_op_mov_reg_A0(2, R_ESP);
} else
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 15/49] target-i386: Tidy mov[sz][bw]
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (13 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 14/49] target-i386: Fix typo in gen_push_T1 Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 16/49] target-i386: Tidy movsl Richard Henderson
` (33 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
We can use the MO_SIGN bit to tidy the reg-reg switch statement
as well as pass it on to gen_op_ld_v, eliminating one call.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 23 ++++++++++++-----------
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 9205b72..f3baa4d 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -5618,11 +5618,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x1be: /* movsbS Gv, Eb */
case 0x1bf: /* movswS Gv, Eb */
{
- int d_ot;
+ TCGMemOp d_ot;
+ TCGMemOp s_ot;
+
/* d_ot is the size of destination */
d_ot = dflag + MO_16;
/* ot is the size of source */
ot = (b & 1) + MO_8;
+ /* s_ot is the sign+size of source */
+ s_ot = b & 8 ? MO_SIGN | ot : ot;
+
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -5630,29 +5635,25 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod == 3) {
gen_op_mov_TN_reg(ot, 0, rm);
- switch(ot | (b & 8)) {
- case MO_8:
+ switch (s_ot) {
+ case MO_UB:
tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
break;
- case MO_8 | 8:
+ case MO_SB:
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
break;
- case MO_16:
+ case MO_UW:
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
break;
default:
- case MO_16 | 8:
+ case MO_SW:
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
break;
}
gen_op_mov_reg_T0(d_ot, reg);
} else {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- if (b & 8) {
- gen_op_ld_v(s, ot | MO_SIGN, cpu_T[0], cpu_A0);
- } else {
- gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
- }
+ gen_op_ld_v(s, s_ot, cpu_T[0], cpu_A0);
gen_op_mov_reg_T0(d_ot, reg);
}
}
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 16/49] target-i386: Tidy movsl
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (14 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 15/49] target-i386: Tidy mov[sz][bw] Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 17/49] target-i386: Remove unused arguments to gen_lea_modrm Richard Henderson
` (32 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Always perform a sign-extending load. In the extremely unlikely
case that we've used an 0x66 prefix, the extension to 64-bits is
unnecessary but not wrong; the store will still examine only 16 bits.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index f3baa4d..0a414c4 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -7747,11 +7747,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_mov_reg_T0(d_ot, reg);
} else {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- if (d_ot == MO_64) {
- gen_op_ld_v(s, MO_32 | MO_SIGN, cpu_T[0], cpu_A0);
- } else {
- gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
- }
+ gen_op_ld_v(s, MO_32 | MO_SIGN, cpu_T[0], cpu_A0);
gen_op_mov_reg_T0(d_ot, reg);
}
} else
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 17/49] target-i386: Remove unused arguments to gen_lea_modrm
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (15 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 16/49] target-i386: Tidy movsl Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 18/49] target-i386: Use MO_BE for movbe Richard Henderson
` (31 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
The reg_ptr and offset_ptr outputs are universally unused.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 146 +++++++++++++++++++++++-------------------------
1 file changed, 69 insertions(+), 77 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 0a414c4..cfd75dc 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -1957,15 +1957,13 @@ static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
}
}
-static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm,
- int *reg_ptr, int *offset_ptr)
+static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm)
{
target_long disp;
int havesib;
int base;
int index;
int scale;
- int opreg;
int mod, rm, code, override, must_add_seg;
TCGv sum;
@@ -2060,7 +2058,7 @@ static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm,
tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
}
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
- goto done;
+ return;
}
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
@@ -2136,12 +2134,6 @@ static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm,
gen_op_addl_A0_seg(s, override);
}
}
-
- done:
- opreg = OR_A0;
- disp = 0;
- *reg_ptr = opreg;
- *offset_ptr = disp;
}
static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm)
@@ -2221,7 +2213,7 @@ static void gen_add_A0_ds_seg(DisasContext *s)
static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
int ot, int reg, int is_store)
{
- int mod, rm, opreg, disp;
+ int mod, rm;
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
@@ -2236,7 +2228,7 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
gen_op_mov_reg_T0(ot, reg);
}
} else {
- gen_lea_modrm(env, s, modrm, &opreg, &disp);
+ gen_lea_modrm(env, s, modrm);
if (is_store) {
if (reg != OR_TMP0)
gen_op_mov_TN_reg(ot, 0, reg);
@@ -3116,7 +3108,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
target_ulong pc_start, int rex_r)
{
int b1, op1_offset, op2_offset, is_xmm, val, ot;
- int modrm, mod, rm, reg, reg_addr, offset_addr;
+ int modrm, mod, rm, reg;
SSEFunc_0_epp sse_fn_epp;
SSEFunc_0_eppi sse_fn_eppi;
SSEFunc_0_ppi sse_fn_ppi;
@@ -3187,7 +3179,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x0e7: /* movntq */
if (mod == 3)
goto illegal_op;
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_stq_env_A0(s, offsetof(CPUX86State, fpregs[reg].mmx));
break;
case 0x1e7: /* movntdq */
@@ -3195,20 +3187,20 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x12b: /* movntps */
if (mod == 3)
goto illegal_op;
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_sto_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
break;
case 0x3f0: /* lddqu */
if (mod == 3)
goto illegal_op;
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
break;
case 0x22b: /* movntss */
case 0x32b: /* movntsd */
if (mod == 3)
goto illegal_op;
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
if (b1 & 1) {
gen_stq_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
} else {
@@ -3251,7 +3243,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x6f: /* movq mm, ea */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_ldq_env_A0(s, offsetof(CPUX86State, fpregs[reg].mmx));
} else {
rm = (modrm & 7);
@@ -3268,7 +3260,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x16f: /* movdqa xmm, ea */
case 0x26f: /* movdqu xmm, ea */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
} else {
rm = (modrm & 7) | REX_B(s);
@@ -3278,7 +3270,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x210: /* movss xmm, ea */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
gen_op_movl_T0_0();
@@ -3293,7 +3285,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x310: /* movsd xmm, ea */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_ldq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(0)));
gen_op_movl_T0_0();
@@ -3308,7 +3300,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x012: /* movlps */
case 0x112: /* movlpd */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_ldq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(0)));
} else {
@@ -3320,7 +3312,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x212: /* movsldup */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
} else {
rm = (modrm & 7) | REX_B(s);
@@ -3336,7 +3328,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x312: /* movddup */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_ldq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(0)));
} else {
@@ -3350,7 +3342,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x016: /* movhps */
case 0x116: /* movhpd */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_ldq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(1)));
} else {
@@ -3362,7 +3354,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x216: /* movshdup */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
} else {
rm = (modrm & 7) | REX_B(s);
@@ -3427,7 +3419,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x27e: /* movq xmm, ea */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_ldq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(0)));
} else {
@@ -3439,7 +3431,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x7f: /* movq ea, mm */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_stq_env_A0(s, offsetof(CPUX86State, fpregs[reg].mmx));
} else {
rm = (modrm & 7);
@@ -3454,7 +3446,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x17f: /* movdqa ea, xmm */
case 0x27f: /* movdqu ea, xmm */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_sto_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
} else {
rm = (modrm & 7) | REX_B(s);
@@ -3464,7 +3456,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x211: /* movss ea, xmm */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
} else {
@@ -3475,7 +3467,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x311: /* movsd ea, xmm */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_stq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(0)));
} else {
@@ -3487,7 +3479,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x013: /* movlps */
case 0x113: /* movlpd */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_stq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(0)));
} else {
@@ -3497,7 +3489,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x017: /* movhps */
case 0x117: /* movhpd */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_stq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(1)));
} else {
@@ -3563,7 +3555,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x12a: /* cvtpi2pd */
gen_helper_enter_mmx(cpu_env);
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
op2_offset = offsetof(CPUX86State,mmx_t0);
gen_ldq_env_A0(s, op2_offset);
} else {
@@ -3608,7 +3600,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x12d: /* cvtpd2pi */
gen_helper_enter_mmx(cpu_env);
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
op2_offset = offsetof(CPUX86State,xmm_t0);
gen_ldo_env_A0(s, op2_offset);
} else {
@@ -3639,7 +3631,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x32d: /* cvtsd2si */
ot = (s->dflag == 2) ? MO_64 : MO_32;
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
if ((b >> 8) & 1) {
gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_t0.XMM_Q(0)));
} else {
@@ -3705,7 +3697,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x1d6: /* movq ea, xmm */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_stq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(0)));
} else {
@@ -3773,7 +3765,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
} else {
op2_offset = offsetof(CPUX86State,xmm_t0);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
switch (b) {
case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
@@ -3807,7 +3799,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
} else {
op2_offset = offsetof(CPUX86State,mmx_t0);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_ldq_env_A0(s, op2_offset);
}
}
@@ -4240,7 +4232,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
ot = (s->dflag == 2) ? MO_64 : MO_32;
rm = (modrm & 7) | REX_B(s);
if (mod != 3)
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
reg = ((modrm >> 3) & 7) | rex_r;
val = cpu_ldub_code(env, s->pc++);
switch (b) {
@@ -4379,7 +4371,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
} else {
op2_offset = offsetof(CPUX86State,xmm_t0);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_ldo_env_A0(s, op2_offset);
}
} else {
@@ -4388,7 +4380,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
} else {
op2_offset = offsetof(CPUX86State,mmx_t0);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_ldq_env_A0(s, op2_offset);
}
}
@@ -4455,7 +4447,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (is_xmm) {
op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
op2_offset = offsetof(CPUX86State,xmm_t0);
if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) ||
b == 0xc2)) {
@@ -4479,7 +4471,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
} else {
op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
op2_offset = offsetof(CPUX86State,mmx_t0);
gen_ldq_env_A0(s, op2_offset);
} else {
@@ -4561,7 +4553,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
{
int b, prefixes, aflag, dflag;
int shift, ot;
- int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
+ int modrm, reg, rm, mod, op, opreg, val;
target_ulong next_eip, tval;
int rex_w, rex_r;
@@ -4756,7 +4748,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
opreg = OR_TMP0;
} else if (op == OP_XORL && rm == reg) {
xor_zero:
@@ -4777,7 +4769,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
reg = ((modrm >> 3) & 7) | rex_r;
rm = (modrm & 7) | REX_B(s);
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
} else if (op == OP_XORL && rm == reg) {
goto xor_zero;
@@ -4819,7 +4811,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
s->rip_offset = 1;
else
s->rip_offset = insn_const_size(ot);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
opreg = OR_TMP0;
} else {
opreg = rm;
@@ -4865,7 +4857,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod != 3) {
if (op == 0)
s->rip_offset = insn_const_size(ot);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_mov_TN_reg(ot, 0, rm);
@@ -5076,7 +5068,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
}
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
if (op >= 2 && op != 3 && op != 5)
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
@@ -5298,7 +5290,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_mov_reg_T1(ot, reg);
gen_op_mov_reg_T0(ot, rm);
} else {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_op_mov_TN_reg(ot, 0, reg);
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
gen_op_addl_T0_T1();
@@ -5330,7 +5322,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
gen_op_mov_v_reg(ot, t0, rm);
} else {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
tcg_gen_mov_tl(a0, cpu_A0);
gen_op_ld_v(s, ot, t0, a0);
rm = 0; /* avoid warning */
@@ -5378,7 +5370,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_jmp_im(pc_start - s->cs_base);
gen_update_cc_op(s);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_helper_cmpxchg16b(cpu_env, cpu_A0);
} else
#endif
@@ -5387,7 +5379,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_jmp_im(pc_start - s->cs_base);
gen_update_cc_op(s);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_helper_cmpxchg8b(cpu_env, cpu_A0);
}
set_cc_op(s, CC_OP_EFLAGS);
@@ -5557,7 +5549,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
mod = (modrm >> 6) & 3;
if (mod != 3) {
s->rip_offset = insn_const_size(ot);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
}
val = insn_get(env, s, ot);
gen_op_movl_T0_im(val);
@@ -5652,7 +5644,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
gen_op_mov_reg_T0(d_ot, reg);
} else {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, s_ot, cpu_T[0], cpu_A0);
gen_op_mov_reg_T0(d_ot, reg);
}
@@ -5670,7 +5662,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
s->override = -1;
val = s->addseg;
s->addseg = 0;
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
s->addseg = val;
gen_op_mov_reg_A0(ot - MO_16, reg);
break;
@@ -5783,7 +5775,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_mov_reg_T0(ot, rm);
gen_op_mov_reg_T1(ot, reg);
} else {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_op_mov_TN_reg(ot, 0, reg);
/* for xchg, lock is implicit */
if (!(prefixes & PREFIX_LOCK))
@@ -5818,7 +5810,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
mod = (modrm >> 6) & 3;
if (mod == 3)
goto illegal_op;
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
/* load the segment first to handle exceptions properly */
@@ -5853,7 +5845,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (shift == 2) {
s->rip_offset = 1;
}
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
opreg = OR_TMP0;
} else {
opreg = (modrm & 7) | REX_B(s);
@@ -5903,7 +5895,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
reg = ((modrm >> 3) & 7) | rex_r;
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
opreg = OR_TMP0;
} else {
opreg = rm;
@@ -5934,7 +5926,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
op = ((b & 7) << 3) | ((modrm >> 3) & 7);
if (mod != 3) {
/* memory op */
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
switch(op) {
case 0x00 ... 0x07: /* fxxxs */
case 0x10 ... 0x17: /* fixxxl */
@@ -6925,7 +6917,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
if (mod != 3) {
s->rip_offset = 1;
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_mov_TN_reg(ot, 0, rm);
@@ -6956,7 +6948,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
gen_op_mov_TN_reg(MO_32, 1, reg);
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
/* specific case: we need to add a displacement */
gen_exts(ot, cpu_T[1]);
tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot);
@@ -7213,7 +7205,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod == 3)
goto illegal_op;
gen_op_mov_TN_reg(ot, 0, reg);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_jmp_im(pc_start - s->cs_base);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
if (ot == MO_16) {
@@ -7461,7 +7453,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod == 3)
goto illegal_op;
gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
gen_add_A0_im(s, 2);
@@ -7524,7 +7516,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
} else { /* sidt */
gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
gen_add_A0_im(s, 2);
@@ -7625,7 +7617,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_svm_check_intercept(s, pc_start,
op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, MO_16, cpu_T[1], cpu_A0);
gen_add_A0_im(s, 2);
gen_op_ld_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
@@ -7667,7 +7659,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_helper_invlpg(cpu_env, cpu_A0);
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
@@ -7746,7 +7738,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
gen_op_mov_reg_T0(d_ot, reg);
} else {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, MO_32 | MO_SIGN, cpu_T[0], cpu_A0);
gen_op_mov_reg_T0(d_ot, reg);
}
@@ -7767,7 +7759,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
mod = (modrm >> 6) & 3;
rm = modrm & 7;
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, t0, cpu_A0);
a0 = tcg_temp_local_new();
tcg_gen_mov_tl(a0, cpu_A0);
@@ -7837,7 +7829,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 3: /* prefetchnt0 */
if (mod == 3)
goto illegal_op;
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
/* nothing more to do */
break;
default: /* nop (multi byte) */
@@ -7964,7 +7956,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
break;
}
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
gen_helper_fxsave(cpu_env, cpu_A0, tcg_const_i32((s->dflag == 2)));
@@ -7977,7 +7969,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
break;
}
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
gen_helper_fxrstor(cpu_env, cpu_A0,
@@ -7992,7 +7984,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) ||
mod == 3)
goto illegal_op;
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
if (op == 2) {
gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
@@ -8017,7 +8009,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* clflush */
if (!(s->cpuid_features & CPUID_CLFLUSH))
goto illegal_op;
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
}
break;
default:
@@ -8029,7 +8021,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
mod = (modrm >> 6) & 3;
if (mod == 3)
goto illegal_op;
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
/* ignore for now */
break;
case 0x1aa: /* rsm */
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 18/49] target-i386: Use MO_BE for movbe
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (16 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 17/49] target-i386: Remove unused arguments to gen_lea_modrm Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 19/49] target-i386: Tidy gen_op_mov_TN_reg+tcg_gen_trunc_tl_i32 Richard Henderson
` (30 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Fold the bswap into the memory operation.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 40 +++++-----------------------------------
1 file changed, 5 insertions(+), 35 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index cfd75dc..c07062c 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -3869,44 +3869,14 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
ot = MO_64;
}
- /* Load the data incoming to the bswap. Note that the TCG
- implementation of bswap requires the input be zero
- extended. In the case of the loads, we simply know that
- gen_op_ld_v via gen_ldst_modrm does that already. */
- if ((b & 1) == 0) {
- gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- } else {
- switch (ot) {
- case MO_16:
- tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[reg]);
- break;
- default:
- tcg_gen_ext32u_tl(cpu_T[0], cpu_regs[reg]);
- break;
- case MO_64:
- tcg_gen_mov_tl(cpu_T[0], cpu_regs[reg]);
- break;
- }
- }
-
- switch (ot) {
- case MO_16:
- tcg_gen_bswap16_tl(cpu_T[0], cpu_T[0]);
- break;
- default:
- tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]);
- break;
-#ifdef TARGET_X86_64
- case MO_64:
- tcg_gen_bswap64_tl(cpu_T[0], cpu_T[0]);
- break;
-#endif
- }
-
+ gen_lea_modrm(env, s, modrm);
if ((b & 1) == 0) {
+ tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0,
+ s->mem_index, ot | MO_BE);
gen_op_mov_reg_T0(ot, reg);
} else {
- gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
+ tcg_gen_qemu_st_tl(cpu_regs[reg], cpu_A0,
+ s->mem_index, ot | MO_BE);
}
break;
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 19/49] target-i386: Tidy gen_op_mov_TN_reg+tcg_gen_trunc_tl_i32
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (17 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 18/49] target-i386: Use MO_BE for movbe Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 20/49] target-i386: Tidy load + truncate Richard Henderson
` (29 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
For the 16 and 32-bit cases, we don't need to truncate via
a temporary register.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index c07062c..3d03d47 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -1259,8 +1259,7 @@ static inline void gen_ins(DisasContext *s, int ot)
case of page fault. */
gen_op_movl_T0_0();
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
- gen_op_mov_TN_reg(MO_16, 1, R_EDX);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[R_EDX]);
tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
@@ -1277,8 +1276,7 @@ static inline void gen_outs(DisasContext *s, int ot)
gen_string_movl_A0_ESI(s);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
- gen_op_mov_TN_reg(MO_16, 1, R_EDX);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[R_EDX]);
tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
@@ -3839,8 +3837,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
ot = MO_64;
}
- gen_op_mov_TN_reg(MO_32, 0, reg);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[reg]);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
gen_helper_crc32(cpu_T[0], cpu_tmp2_i32,
cpu_T[0], tcg_const_i32(8 << ot));
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 20/49] target-i386: Tidy load + truncate
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (18 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 19/49] target-i386: Tidy gen_op_mov_TN_reg+tcg_gen_trunc_tl_i32 Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 21/49] target-i386: Tidy extend + store Richard Henderson
` (28 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
We can now use tcg_gen_qemu_ld_i32 directly to avoid the truncation.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 39 +++++++++++++++++++--------------------
1 file changed, 19 insertions(+), 20 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 3d03d47..58be71f 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -4303,12 +4303,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x22:
if (ot == MO_32) { /* pinsrd */
if (mod == 3) {
- gen_op_mov_v_reg(ot, cpu_tmp0, rm);
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[rm]);
} else {
- tcg_gen_qemu_ld_tl(cpu_tmp0, cpu_A0,
- s->mem_index, MO_LEUL);
+ tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUL);
}
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
offsetof(CPUX86State,
xmm_regs[reg].XMM_L(val & 3)));
@@ -5905,13 +5904,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
switch(op >> 4) {
case 0:
- gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUL);
gen_helper_flds_FT0(cpu_env, cpu_tmp2_i32);
break;
case 1:
- gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUL);
gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
break;
case 2:
@@ -5921,8 +5920,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 3:
default:
- gen_op_ld_v(s, MO_SW, cpu_T[0], cpu_A0);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LESW);
gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
break;
}
@@ -5944,13 +5943,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0:
switch(op >> 4) {
case 0:
- gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUL);
gen_helper_flds_ST0(cpu_env, cpu_tmp2_i32);
break;
case 1:
- gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUL);
gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
break;
case 2:
@@ -5960,8 +5959,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 3:
default:
- gen_op_ld_v(s, MO_SW, cpu_T[0], cpu_A0);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LESW);
gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
break;
}
@@ -6023,8 +6022,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
break;
case 0x0d: /* fldcw mem */
- gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUW);
gen_helper_fldcw(cpu_env, cpu_tmp2_i32);
break;
case 0x0e: /* fnstenv mem */
@@ -7953,8 +7952,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_lea_modrm(env, s, modrm);
if (op == 2) {
- gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUL);
gen_helper_ldmxcsr(cpu_env, cpu_tmp2_i32);
} else {
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 21/49] target-i386: Tidy extend + store
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (19 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 20/49] target-i386: Tidy load + truncate Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 22/49] target-i386: Tidy extend + move Richard Henderson
` (27 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
We can now use tcg_gen_qemu_st_i32 directly to avoid the extension.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 34 +++++++++++++++++-----------------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 58be71f..ad6ecd3 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -4228,12 +4228,12 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
offsetof(CPUX86State,
xmm_regs[reg].XMM_L(val & 3)));
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
if (mod == 3) {
+ tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
- tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
- s->mem_index, MO_LEUL);
+ tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUL);
}
} else { /* pextrq */
#ifdef TARGET_X86_64
@@ -5970,8 +5970,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
switch(op >> 4) {
case 1:
gen_helper_fisttl_ST0(cpu_tmp2_i32, cpu_env);
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
+ tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUL);
break;
case 2:
gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env);
@@ -5981,8 +5981,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 3:
default:
gen_helper_fistt_ST0(cpu_tmp2_i32, cpu_env);
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
+ tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUW);
break;
}
gen_helper_fpop(cpu_env);
@@ -5991,13 +5991,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
switch(op >> 4) {
case 0:
gen_helper_fsts_ST0(cpu_tmp2_i32, cpu_env);
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
+ tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUL);
break;
case 1:
gen_helper_fistl_ST0(cpu_tmp2_i32, cpu_env);
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
+ tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUL);
break;
case 2:
gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env);
@@ -6007,8 +6007,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 3:
default:
gen_helper_fist_ST0(cpu_tmp2_i32, cpu_env);
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
+ tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUW);
break;
}
if ((op & 7) == 3)
@@ -6033,8 +6033,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x0f: /* fnstcw mem */
gen_helper_fnstcw(cpu_tmp2_i32, cpu_env);
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
+ tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUW);
break;
case 0x1d: /* fldt mem */
gen_update_cc_op(s);
@@ -6059,8 +6059,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x2f: /* fnstsw mem */
gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
+ tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUW);
break;
case 0x3c: /* fbld */
gen_update_cc_op(s);
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 22/49] target-i386: Tidy extend + move
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (20 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 21/49] target-i386: Tidy extend + store Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 23/49] target-i386: Remove gen_op_movl_T0_0 Richard Henderson
` (26 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
For the known MO_32/MO_64 cases, we don't need to extend a 32-bit temp
into a 64-bit temp before storing into the hardware register.
We do need the extension for the MO_8/MO_16 cases, in order for the
deposit_tl operation to work, so leave those alone.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 14 +++++---------
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index ad6ecd3..2d404d7 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -3538,16 +3538,14 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
offsetof(CPUX86State,xmm_regs[rm]));
gen_helper_movmskps(cpu_tmp2_i32, cpu_env, cpu_ptr0);
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_mov_reg_T0(MO_32, reg);
+ tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp2_i32);
break;
case 0x150: /* movmskpd */
rm = (modrm & 7) | REX_B(s);
tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
offsetof(CPUX86State,xmm_regs[rm]));
gen_helper_movmskpd(cpu_tmp2_i32, cpu_env, cpu_ptr0);
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_mov_reg_T0(MO_32, reg);
+ tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp2_i32);
break;
case 0x02a: /* cvtpi2ps */
case 0x12a: /* cvtpi2pd */
@@ -3731,9 +3729,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx));
gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_env, cpu_ptr0);
}
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
reg = ((modrm >> 3) & 7) | rex_r;
- gen_op_mov_reg_T0(MO_32, reg);
+ tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp2_i32);
break;
case 0x138:
@@ -4229,8 +4226,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
offsetof(CPUX86State,
xmm_regs[reg].XMM_L(val & 3)));
if (mod == 3) {
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_mov_reg_v(ot, rm, cpu_T[0]);
+ tcg_gen_extu_i32_tl(cpu_regs[rm], cpu_tmp2_i32);
} else {
tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0,
s->mem_index, MO_LEUL);
@@ -4241,7 +4237,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(val & 1)));
if (mod == 3) {
- gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64);
+ tcg_gen_mov_i64(cpu_regs[rm], cpu_tmp1_i64);
} else {
tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0,
s->mem_index, MO_LEQ);
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 23/49] target-i386: Remove gen_op_movl_T0_0
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (21 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 22/49] target-i386: Tidy extend + move Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 24/49] target-i386: Remove gen_op_movl_T0_im* Richard Henderson
` (25 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Propagate its definition into all users.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 17 ++++++-----------
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 2d404d7..0671371 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -252,11 +252,6 @@ static void gen_update_cc_op(DisasContext *s)
}
}
-static inline void gen_op_movl_T0_0(void)
-{
- tcg_gen_movi_tl(cpu_T[0], 0);
-}
-
static inline void gen_op_movl_T0_im(int32_t val)
{
tcg_gen_movi_tl(cpu_T[0], val);
@@ -1257,7 +1252,7 @@ static inline void gen_ins(DisasContext *s, int ot)
gen_string_movl_A0_EDI(s);
/* Note: we must do this dummy write first to be restartable in
case of page fault. */
- gen_op_movl_T0_0();
+ tcg_gen_movi_tl(cpu_T[0], 0);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[R_EDX]);
tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
@@ -3271,7 +3266,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
- gen_op_movl_T0_0();
+ tcg_gen_movi_tl(cpu_T[0], 0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
@@ -3286,7 +3281,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_lea_modrm(env, s, modrm);
gen_ldq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(0)));
- gen_op_movl_T0_0();
+ tcg_gen_movi_tl(cpu_T[0], 0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
} else {
@@ -3507,13 +3502,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (is_xmm) {
gen_op_movl_T0_im(val);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
- gen_op_movl_T0_0();
+ tcg_gen_movi_tl(cpu_T[0], 0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
op1_offset = offsetof(CPUX86State,xmm_t0);
} else {
gen_op_movl_T0_im(val);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0)));
- gen_op_movl_T0_0();
+ tcg_gen_movi_tl(cpu_T[0], 0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1)));
op1_offset = offsetof(CPUX86State,mmx_t0);
}
@@ -4716,7 +4711,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
xor_zero:
/* xor reg, reg optimisation */
set_cc_op(s, CC_OP_CLR);
- gen_op_movl_T0_0();
+ tcg_gen_movi_tl(cpu_T[0], 0);
gen_op_mov_reg_T0(ot, reg);
break;
} else {
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 24/49] target-i386: Remove gen_op_movl_T0_im*
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (22 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 23/49] target-i386: Remove gen_op_movl_T0_0 Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-23 15:24 ` Kevin Wolf
2014-01-07 21:00 ` [Qemu-devel] [PULL 25/49] " Richard Henderson
` (24 subsequent siblings)
48 siblings, 1 reply; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Propagate the definition of gen_op_movl_T0_im to all users.
The function gen_op_movl_T0_imu was unused.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 32 ++++++++++----------------------
1 file changed, 10 insertions(+), 22 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 0671371..46eabe4 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -252,16 +252,6 @@ static void gen_update_cc_op(DisasContext *s)
}
}
-static inline void gen_op_movl_T0_im(int32_t val)
-{
- tcg_gen_movi_tl(cpu_T[0], val);
-}
-
-static inline void gen_op_movl_T0_imu(uint32_t val)
-{
- tcg_gen_movi_tl(cpu_T[0], val);
-}
-
static inline void gen_op_movl_T1_im(int32_t val)
{
tcg_gen_movi_tl(cpu_T[1], val);
@@ -3500,13 +3490,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
}
val = cpu_ldub_code(env, s->pc++);
if (is_xmm) {
- gen_op_movl_T0_im(val);
+ tcg_gen_movi_tl(cpu_T[0], val);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
tcg_gen_movi_tl(cpu_T[0], 0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
op1_offset = offsetof(CPUX86State,xmm_t0);
} else {
- gen_op_movl_T0_im(val);
+ tcg_gen_movi_tl(cpu_T[0], val);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0)));
tcg_gen_movi_tl(cpu_T[0], 0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1)));
@@ -5380,7 +5370,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
val = insn_get(env, s, ot);
else
val = (int8_t)insn_get(env, s, MO_8);
- gen_op_movl_T0_im(val);
+ tcg_gen_movi_tl(cpu_T[0], val);
gen_push_T0(s);
break;
case 0x8f: /* pop Ev */
@@ -5509,7 +5499,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_lea_modrm(env, s, modrm);
}
val = insn_get(env, s, ot);
- gen_op_movl_T0_im(val);
+ tcg_gen_movi_tl(cpu_T[0], val);
if (mod != 3) {
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
@@ -5685,7 +5675,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0xb0 ... 0xb7: /* mov R, Ib */
val = insn_get(env, s, MO_8);
- gen_op_movl_T0_im(val);
+ tcg_gen_movi_tl(cpu_T[0], val);
gen_op_mov_reg_T0(MO_8, (b & 7) | REX_B(s));
break;
case 0xb8 ... 0xbf: /* mov R, Iv */
@@ -5704,7 +5694,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
ot = dflag ? MO_32 : MO_16;
val = insn_get(env, s, ot);
reg = (b & 7) | REX_B(s);
- gen_op_movl_T0_im(val);
+ tcg_gen_movi_tl(cpu_T[0], val);
gen_op_mov_reg_T0(ot, reg);
}
break;
@@ -6508,12 +6498,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
else
ot = dflag ? MO_32 : MO_16;
val = cpu_ldub_code(env, s->pc++);
- gen_op_movl_T0_im(val);
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
if (use_icount)
gen_io_start();
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_movi_i32(cpu_tmp2_i32, val);
gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
gen_op_mov_reg_T1(ot, R_EAX);
if (use_icount) {
@@ -6528,14 +6517,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
else
ot = dflag ? MO_32 : MO_16;
val = cpu_ldub_code(env, s->pc++);
- gen_op_movl_T0_im(val);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes));
gen_op_mov_TN_reg(ot, 1, R_EAX);
if (use_icount)
gen_io_start();
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_movi_i32(cpu_tmp2_i32, val);
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
if (use_icount) {
@@ -6687,7 +6675,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
offset = insn_get(env, s, ot);
selector = insn_get(env, s, MO_16);
- gen_op_movl_T0_im(selector);
+ tcg_gen_movi_tl(cpu_T[0], selector);
gen_op_movl_T1_imu(offset);
}
goto do_lcall;
@@ -6713,7 +6701,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
offset = insn_get(env, s, ot);
selector = insn_get(env, s, MO_16);
- gen_op_movl_T0_im(selector);
+ tcg_gen_movi_tl(cpu_T[0], selector);
gen_op_movl_T1_imu(offset);
}
goto do_ljmp;
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [Qemu-devel] [PULL 24/49] target-i386: Remove gen_op_movl_T0_im*
2014-01-07 21:00 ` [Qemu-devel] [PULL 24/49] target-i386: Remove gen_op_movl_T0_im* Richard Henderson
@ 2014-01-23 15:24 ` Kevin Wolf
2014-01-23 17:03 ` Richard Henderson
0 siblings, 1 reply; 52+ messages in thread
From: Kevin Wolf @ 2014-01-23 15:24 UTC (permalink / raw)
To: Richard Henderson; +Cc: peter.maydell, qemu-devel, aliguori
Am 07.01.2014 um 22:00 hat Richard Henderson geschrieben:
> Propagate the definition of gen_op_movl_T0_im to all users.
> The function gen_op_movl_T0_imu was unused.
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-i386/translate.c | 32 ++++++++++----------------------
> 1 file changed, 10 insertions(+), 22 deletions(-)
>
> diff --git a/target-i386/translate.c b/target-i386/translate.c
> index 0671371..46eabe4 100644
> --- a/target-i386/translate.c
> +++ b/target-i386/translate.c
> @@ -252,16 +252,6 @@ static void gen_update_cc_op(DisasContext *s)
> }
> }
>
> -static inline void gen_op_movl_T0_im(int32_t val)
> -{
> - tcg_gen_movi_tl(cpu_T[0], val);
> -}
> -
> -static inline void gen_op_movl_T0_imu(uint32_t val)
> -{
> - tcg_gen_movi_tl(cpu_T[0], val);
> -}
> -
> static inline void gen_op_movl_T1_im(int32_t val)
> {
> tcg_gen_movi_tl(cpu_T[1], val);
> @@ -3500,13 +3490,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
> }
> val = cpu_ldub_code(env, s->pc++);
> if (is_xmm) {
> - gen_op_movl_T0_im(val);
> + tcg_gen_movi_tl(cpu_T[0], val);
> tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
> tcg_gen_movi_tl(cpu_T[0], 0);
> tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
> op1_offset = offsetof(CPUX86State,xmm_t0);
> } else {
> - gen_op_movl_T0_im(val);
> + tcg_gen_movi_tl(cpu_T[0], val);
> tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0)));
> tcg_gen_movi_tl(cpu_T[0], 0);
> tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1)));
> @@ -5380,7 +5370,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
> val = insn_get(env, s, ot);
> else
> val = (int8_t)insn_get(env, s, MO_8);
> - gen_op_movl_T0_im(val);
> + tcg_gen_movi_tl(cpu_T[0], val);
> gen_push_T0(s);
> break;
> case 0x8f: /* pop Ev */
> @@ -5509,7 +5499,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
> gen_lea_modrm(env, s, modrm);
> }
> val = insn_get(env, s, ot);
> - gen_op_movl_T0_im(val);
> + tcg_gen_movi_tl(cpu_T[0], val);
> if (mod != 3) {
> gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
> } else {
> @@ -5685,7 +5675,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
> break;
> case 0xb0 ... 0xb7: /* mov R, Ib */
> val = insn_get(env, s, MO_8);
> - gen_op_movl_T0_im(val);
> + tcg_gen_movi_tl(cpu_T[0], val);
> gen_op_mov_reg_T0(MO_8, (b & 7) | REX_B(s));
> break;
> case 0xb8 ... 0xbf: /* mov R, Iv */
> @@ -5704,7 +5694,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
> ot = dflag ? MO_32 : MO_16;
> val = insn_get(env, s, ot);
> reg = (b & 7) | REX_B(s);
> - gen_op_movl_T0_im(val);
> + tcg_gen_movi_tl(cpu_T[0], val);
> gen_op_mov_reg_T0(ot, reg);
> }
> break;
> @@ -6508,12 +6498,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
> else
> ot = dflag ? MO_32 : MO_16;
> val = cpu_ldub_code(env, s->pc++);
> - gen_op_movl_T0_im(val);
> gen_check_io(s, ot, pc_start - s->cs_base,
> SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
This removal is wrong. gen_check_io() uses cpu_T[0] internally in order
to check the I/O bitmap. Now I get a #GP even for legitimate cases.
The following patch (which is essentially a partial revert) makes it
work for me again. Should I send it as a proper patch or would you
prefer to clean up gen_check_io()? I guess some more explicit passing of
the port number couldn't hurt there, but I'm not familiar with TCG and
who knows what I would break while doing this...
Kevin
diff --git a/target-i386/translate.c b/target-i386/translate.c
index b0f2279..5dd2450 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -6284,6 +6284,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xe5:
ot = mo_b_d32(b, dflag);
val = cpu_ldub_code(env, s->pc++);
+ tcg_gen_movi_tl(cpu_T[0], val);
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
if (use_icount)
@@ -6300,6 +6301,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xe7:
ot = mo_b_d32(b, dflag);
val = cpu_ldub_code(env, s->pc++);
+ tcg_gen_movi_tl(cpu_T[0], val);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes));
gen_op_mov_v_reg(ot, cpu_T[1], R_EAX);
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [Qemu-devel] [PULL 24/49] target-i386: Remove gen_op_movl_T0_im*
2014-01-23 15:24 ` Kevin Wolf
@ 2014-01-23 17:03 ` Richard Henderson
0 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-23 17:03 UTC (permalink / raw)
To: Kevin Wolf; +Cc: peter.maydell, qemu-devel, aliguori
On 01/23/2014 07:24 AM, Kevin Wolf wrote:
>> > @@ -6508,12 +6498,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
>> > else
>> > ot = dflag ? MO_32 : MO_16;
>> > val = cpu_ldub_code(env, s->pc++);
>> > - gen_op_movl_T0_im(val);
>> > gen_check_io(s, ot, pc_start - s->cs_base,
>> > SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
> This removal is wrong. gen_check_io() uses cpu_T[0] internally in order
> to check the I/O bitmap. Now I get a #GP even for legitimate cases.
>
> The following patch (which is essentially a partial revert) makes it
> work for me again. Should I send it as a proper patch or would you
> prefer to clean up gen_check_io()? I guess some more explicit passing of
> the port number couldn't hurt there, but I'm not familiar with TCG and
> who knows what I would break while doing this...
Oops. How did that happen?
Please just send this as a proper patch and we'll worry about cleanup of
gen_check_io later. You can add my
Reviewed-by: Richard Henderson <rth@twiddle.net>
when you send it. Via qemu-trivial?
r~
^ permalink raw reply [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 25/49] target-i386: Remove gen_op_movl_T0_im*
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (23 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 24/49] target-i386: Remove gen_op_movl_T0_im* Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 26/49] target-i386: Remove gen_op_mov*_A0_im Richard Henderson
` (23 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Propagate the definitions into all users. The only time that
gen_op_movl_T1_imu was used, the input was type 'unsigned',
so the replacement works identically.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 30 ++++++++++--------------------
1 file changed, 10 insertions(+), 20 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 46eabe4..59554aa 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -252,16 +252,6 @@ static void gen_update_cc_op(DisasContext *s)
}
}
-static inline void gen_op_movl_T1_im(int32_t val)
-{
- tcg_gen_movi_tl(cpu_T[1], val);
-}
-
-static inline void gen_op_movl_T1_imu(uint32_t val)
-{
- tcg_gen_movi_tl(cpu_T[1], val);
-}
-
static inline void gen_op_movl_A0_im(uint32_t val)
{
tcg_gen_movi_tl(cpu_A0, val);
@@ -1934,7 +1924,7 @@ static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
break;
default:
/* currently not optimized */
- gen_op_movl_T1_im(c);
+ tcg_gen_movi_tl(cpu_T[1], c);
gen_shift(s1, op, ot, d, OR_TMP1);
break;
}
@@ -4727,7 +4717,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 2: /* OP A, Iv */
val = insn_get(env, s, ot);
- gen_op_movl_T1_im(val);
+ tcg_gen_movi_tl(cpu_T[1], val);
gen_op(s, op, ot, OR_EAX);
break;
}
@@ -4775,7 +4765,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
val = (int8_t)insn_get(env, s, MO_8);
break;
}
- gen_op_movl_T1_im(val);
+ tcg_gen_movi_tl(cpu_T[1], val);
gen_op(s, op, ot, opreg);
}
break;
@@ -4813,7 +4803,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
switch(op) {
case 0: /* test */
val = insn_get(env, s, ot);
- gen_op_movl_T1_im(val);
+ tcg_gen_movi_tl(cpu_T[1], val);
gen_op_testl_T0_T1_cc();
set_cc_op(s, CC_OP_LOGICB + ot);
break;
@@ -5124,7 +5114,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
val = insn_get(env, s, ot);
gen_op_mov_TN_reg(ot, 0, OR_EAX);
- gen_op_movl_T1_im(val);
+ tcg_gen_movi_tl(cpu_T[1], val);
gen_op_testl_T0_T1_cc();
set_cc_op(s, CC_OP_LOGICB + ot);
break;
@@ -5180,10 +5170,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
if (b == 0x69) {
val = insn_get(env, s, ot);
- gen_op_movl_T1_im(val);
+ tcg_gen_movi_tl(cpu_T[1], val);
} else if (b == 0x6b) {
val = (int8_t)insn_get(env, s, MO_8);
- gen_op_movl_T1_im(val);
+ tcg_gen_movi_tl(cpu_T[1], val);
} else {
gen_op_mov_TN_reg(ot, 1, reg);
}
@@ -6676,7 +6666,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
selector = insn_get(env, s, MO_16);
tcg_gen_movi_tl(cpu_T[0], selector);
- gen_op_movl_T1_imu(offset);
+ tcg_gen_movi_tl(cpu_T[1], offset);
}
goto do_lcall;
case 0xe9: /* jmp im */
@@ -6702,7 +6692,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
selector = insn_get(env, s, MO_16);
tcg_gen_movi_tl(cpu_T[0], selector);
- gen_op_movl_T1_imu(offset);
+ tcg_gen_movi_tl(cpu_T[1], offset);
}
goto do_ljmp;
case 0xeb: /* jmp Jb */
@@ -6869,7 +6859,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
/* load shift */
val = cpu_ldub_code(env, s->pc++);
- gen_op_movl_T1_im(val);
+ tcg_gen_movi_tl(cpu_T[1], val);
if (op < 4)
goto illegal_op;
op -= 4;
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 26/49] target-i386: Remove gen_op_mov*_A0_im
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (24 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 25/49] " Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 27/49] target-i386: Remove gen_movtl_T*_im Richard Henderson
` (22 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Propagate the definitions into all users. In two cases, this allows
us to share code between the 32-bit and 64-bit immediate moves.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 17 ++---------------
1 file changed, 2 insertions(+), 15 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 59554aa..ade8606 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -252,18 +252,6 @@ static void gen_update_cc_op(DisasContext *s)
}
}
-static inline void gen_op_movl_A0_im(uint32_t val)
-{
- tcg_gen_movi_tl(cpu_A0, val);
-}
-
-#ifdef TARGET_X86_64
-static inline void gen_op_movq_A0_im(int64_t val)
-{
- tcg_gen_movi_tl(cpu_A0, val);
-}
-#endif
-
static inline void gen_movtl_T0_im(target_ulong val)
{
tcg_gen_movi_tl(cpu_T[0], val);
@@ -2046,7 +2034,7 @@ static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm)
if (rm == 6) {
disp = cpu_lduw_code(env, s->pc);
s->pc += 2;
- gen_op_movl_A0_im(disp);
+ tcg_gen_movi_tl(cpu_A0, disp);
rm = 0; /* avoid SS override */
goto no_rm;
} else {
@@ -5619,7 +5607,6 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (s->aflag == 2) {
offset_addr = cpu_ldq_code(env, s->pc);
s->pc += 8;
- gen_op_movq_A0_im(offset_addr);
} else
#endif
{
@@ -5628,8 +5615,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
offset_addr = insn_get(env, s, MO_16);
}
- gen_op_movl_A0_im(offset_addr);
}
+ tcg_gen_movi_tl(cpu_A0, offset_addr);
gen_add_A0_ds_seg(s);
if ((b & 2) == 0) {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 27/49] target-i386: Remove gen_movtl_T*_im
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (25 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 26/49] target-i386: Remove gen_op_mov*_A0_im Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 28/49] target-i386: Remove gen_op_andl_T0_ffff Richard Henderson
` (21 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Propagate the definitions into all users.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 16 +++-------------
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index ade8606..a0fba1b 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -252,16 +252,6 @@ static void gen_update_cc_op(DisasContext *s)
}
}
-static inline void gen_movtl_T0_im(target_ulong val)
-{
- tcg_gen_movi_tl(cpu_T[0], val);
-}
-
-static inline void gen_movtl_T1_im(target_ulong val)
-{
- tcg_gen_movi_tl(cpu_T[1], val);
-}
-
static inline void gen_op_andl_T0_ffff(void)
{
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
@@ -5020,7 +5010,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (s->dflag == 0)
gen_op_andl_T0_ffff();
next_eip = s->pc - s->cs_base;
- gen_movtl_T1_im(next_eip);
+ tcg_gen_movi_tl(cpu_T[1], next_eip);
gen_push_T1(s);
gen_op_jmp_T0();
gen_eob(s);
@@ -5663,7 +5653,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tmp = cpu_ldq_code(env, s->pc);
s->pc += 8;
reg = (b & 7) | REX_B(s);
- gen_movtl_T0_im(tmp);
+ tcg_gen_movi_tl(cpu_T[0], tmp);
gen_op_mov_reg_T0(MO_64, reg);
} else
#endif
@@ -6637,7 +6627,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tval &= 0xffff;
else if(!CODE64(s))
tval &= 0xffffffff;
- gen_movtl_T0_im(next_eip);
+ tcg_gen_movi_tl(cpu_T[0], next_eip);
gen_push_T0(s);
gen_jmp(s, tval);
}
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 28/49] target-i386: Remove gen_op_andl_T0_ffff
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (26 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 27/49] target-i386: Remove gen_movtl_T*_im Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 29/49] target-i386: Remove gen_op_andl_T0_im Richard Henderson
` (20 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Replace it with tcg_gen_ext16u_tl. In four places we can combine that
with a previous move into cpu_T[0], and in one place we can infer that
the zero-extension has already happened via the previous load.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 43 ++++++++++++++++++-------------------------
1 file changed, 18 insertions(+), 25 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index a0fba1b..502d129 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -252,11 +252,6 @@ static void gen_update_cc_op(DisasContext *s)
}
}
-static inline void gen_op_andl_T0_ffff(void)
-{
- tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
-}
-
static inline void gen_op_andl_T0_im(uint32_t val)
{
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val);
@@ -5007,8 +5002,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 2: /* call Ev */
/* XXX: optimize if memory (no 'and' is necessary) */
- if (s->dflag == 0)
- gen_op_andl_T0_ffff();
+ if (s->dflag == 0) {
+ tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
+ }
next_eip = s->pc - s->cs_base;
tcg_gen_movi_tl(cpu_T[1], next_eip);
gen_push_T1(s);
@@ -5036,8 +5032,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_eob(s);
break;
case 4: /* jmp Ev */
- if (s->dflag == 0)
- gen_op_andl_T0_ffff();
+ if (s->dflag == 0) {
+ tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
+ }
gen_op_jmp_T0();
gen_eob(s);
break;
@@ -6422,8 +6419,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
ot = MO_8;
else
ot = dflag ? MO_32 : MO_16;
- gen_op_mov_TN_reg(MO_16, 0, R_EDX);
- gen_op_andl_T0_ffff();
+ tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
@@ -6441,8 +6437,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
ot = MO_8;
else
ot = dflag ? MO_32 : MO_16;
- gen_op_mov_TN_reg(MO_16, 0, R_EDX);
- gen_op_andl_T0_ffff();
+ tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes) | 4);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
@@ -6504,8 +6499,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
ot = MO_8;
else
ot = dflag ? MO_32 : MO_16;
- gen_op_mov_TN_reg(MO_16, 0, R_EDX);
- gen_op_andl_T0_ffff();
+ tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
if (use_icount)
@@ -6524,8 +6518,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
ot = MO_8;
else
ot = dflag ? MO_32 : MO_16;
- gen_op_mov_TN_reg(MO_16, 0, R_EDX);
- gen_op_andl_T0_ffff();
+ tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes));
gen_op_mov_TN_reg(ot, 1, R_EAX);
@@ -6550,16 +6543,18 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (CODE64(s) && s->dflag)
s->dflag = 2;
gen_stack_update(s, val + (2 << s->dflag));
- if (s->dflag == 0)
- gen_op_andl_T0_ffff();
+ if (s->dflag == 0) {
+ tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
+ }
gen_op_jmp_T0();
gen_eob(s);
break;
case 0xc3: /* ret */
gen_pop_T0(s);
gen_pop_update(s);
- if (s->dflag == 0)
- gen_op_andl_T0_ffff();
+ if (s->dflag == 0) {
+ tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
+ }
gen_op_jmp_T0();
gen_eob(s);
break;
@@ -6575,15 +6570,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_stack_A0(s);
/* pop offset */
- gen_op_ld_v(s, 1 + s->dflag, cpu_T[0], cpu_A0);
- if (s->dflag == 0)
- gen_op_andl_T0_ffff();
+ gen_op_ld_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0);
/* NOTE: keeping EIP updated is not a problem in case of
exception */
gen_op_jmp_T0();
/* pop selector */
gen_op_addl_A0_im(2 << s->dflag);
- gen_op_ld_v(s, 1 + s->dflag, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0);
gen_op_movl_seg_T0_vm(R_CS);
/* add stack offset */
gen_stack_update(s, val + (4 << s->dflag));
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 29/49] target-i386: Remove gen_op_andl_T0_im
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (27 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 28/49] target-i386: Remove gen_op_andl_T0_ffff Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 30/49] target-i386: Remove gen_op_movl_T0_T1 Richard Henderson
` (19 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Replace it with its definition.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 20 +++++++++-----------
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 502d129..6051c2c 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -252,11 +252,6 @@ static void gen_update_cc_op(DisasContext *s)
}
}
-static inline void gen_op_andl_T0_im(uint32_t val)
-{
- tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val);
-}
-
static inline void gen_op_movl_T0_T1(void)
{
tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
@@ -7363,8 +7358,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
- if (!s->dflag)
- gen_op_andl_T0_im(0xffffff);
+ if (s->dflag == 0) {
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff);
+ }
gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
break;
case 1:
@@ -7426,8 +7422,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
- if (!s->dflag)
- gen_op_andl_T0_im(0xffffff);
+ if (s->dflag == 0) {
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff);
+ }
gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
}
break;
@@ -7526,8 +7523,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_ld_v(s, MO_16, cpu_T[1], cpu_A0);
gen_add_A0_im(s, 2);
gen_op_ld_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
- if (!s->dflag)
- gen_op_andl_T0_im(0xffffff);
+ if (s->dflag == 0) {
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff);
+ }
if (op == 2) {
tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base));
tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit));
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 30/49] target-i386: Remove gen_op_movl_T0_T1
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (28 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 29/49] target-i386: Remove gen_op_andl_T0_im Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 31/49] target-i386: Remove gen_op_andl_A0_ffff Richard Henderson
` (18 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Replace it with its definition.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 6051c2c..4da5b8e 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -252,11 +252,6 @@ static void gen_update_cc_op(DisasContext *s)
}
}
-static inline void gen_op_movl_T0_T1(void)
-{
- tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
-}
-
static inline void gen_op_andl_A0_ffff(void)
{
tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);
@@ -5046,7 +5041,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_const_i32(s->pc - pc_start));
} else {
gen_op_movl_seg_T0_vm(R_CS);
- gen_op_movl_T0_T1();
+ tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
gen_op_jmp_T0();
}
gen_eob(s);
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 31/49] target-i386: Remove gen_op_andl_A0_ffff
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (29 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 30/49] target-i386: Remove gen_op_movl_T0_T1 Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 32/49] target-i386: Use TCGMemOp for 'ot' variables Richard Henderson
` (17 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Replace it with tcg_gen_ext16u_tl, and in two cases merge with a
previous move from cpu_regs.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 33 +++++++++++++--------------------
1 file changed, 13 insertions(+), 20 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 4da5b8e..c3c51a6 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -252,11 +252,6 @@ static void gen_update_cc_op(DisasContext *s)
}
}
-static inline void gen_op_andl_A0_ffff(void)
-{
- tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);
-}
-
#ifdef TARGET_X86_64
#define NB_OP_SIZES 4
@@ -568,8 +563,7 @@ static inline void gen_string_movl_A0_ESI(DisasContext *s)
/* 16 address, always override */
if (override < 0)
override = R_DS;
- gen_op_movl_A0_reg(R_ESI);
- gen_op_andl_A0_ffff();
+ tcg_gen_ext16u_tl(cpu_A0, cpu_regs[R_ESI]);
gen_op_addl_A0_seg(s, override);
}
}
@@ -589,8 +583,7 @@ static inline void gen_string_movl_A0_EDI(DisasContext *s)
gen_op_movl_A0_reg(R_EDI);
}
} else {
- gen_op_movl_A0_reg(R_EDI);
- gen_op_andl_A0_ffff();
+ tcg_gen_ext16u_tl(cpu_A0, cpu_regs[R_EDI]);
gen_op_addl_A0_seg(s, R_ES);
}
}
@@ -2058,7 +2051,7 @@ static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm)
}
if (disp != 0)
gen_op_addl_A0_im(disp);
- gen_op_andl_A0_ffff();
+ tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
no_rm:
if (must_add_seg) {
if (override < 0) {
@@ -2392,7 +2385,7 @@ static void gen_push_T0(DisasContext *s)
gen_op_addl_A0_seg(s, R_SS);
}
} else {
- gen_op_andl_A0_ffff();
+ tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
gen_op_addl_A0_seg(s, R_SS);
}
@@ -2432,7 +2425,7 @@ static void gen_push_T1(DisasContext *s)
gen_op_addl_A0_seg(s, R_SS);
}
} else {
- gen_op_andl_A0_ffff();
+ tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
gen_op_addl_A0_seg(s, R_SS);
}
gen_op_st_v(s, s->dflag + 1, cpu_T[1], cpu_A0);
@@ -2459,7 +2452,7 @@ static void gen_pop_T0(DisasContext *s)
if (s->addseg)
gen_op_addl_A0_seg(s, R_SS);
} else {
- gen_op_andl_A0_ffff();
+ tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
gen_op_addl_A0_seg(s, R_SS);
}
gen_op_ld_v(s, s->dflag + 1, cpu_T[0], cpu_A0);
@@ -2482,7 +2475,7 @@ static void gen_stack_A0(DisasContext *s)
{
gen_op_movl_A0_reg(R_ESP);
if (!s->ss32)
- gen_op_andl_A0_ffff();
+ tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
if (s->addseg)
gen_op_addl_A0_seg(s, R_SS);
@@ -2495,7 +2488,7 @@ static void gen_pusha(DisasContext *s)
gen_op_movl_A0_reg(R_ESP);
gen_op_addl_A0_im(-16 << s->dflag);
if (!s->ss32)
- gen_op_andl_A0_ffff();
+ tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
if (s->addseg)
gen_op_addl_A0_seg(s, R_SS);
@@ -2513,7 +2506,7 @@ static void gen_popa(DisasContext *s)
int i;
gen_op_movl_A0_reg(R_ESP);
if (!s->ss32)
- gen_op_andl_A0_ffff();
+ tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag);
if (s->addseg)
@@ -2564,7 +2557,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
gen_op_movl_A0_reg(R_ESP);
gen_op_addl_A0_im(-opsize);
if (!s->ss32)
- gen_op_andl_A0_ffff();
+ tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
if (s->addseg)
gen_op_addl_A0_seg(s, R_SS);
@@ -4424,7 +4417,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
{
gen_op_movl_A0_reg(R_EDI);
if (s->aflag == 0)
- gen_op_andl_A0_ffff();
+ tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
}
gen_add_A0_ds_seg(s);
@@ -5619,7 +5612,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
if (s->aflag == 0)
- gen_op_andl_A0_ffff();
+ tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
else
tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
}
@@ -7375,7 +7368,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
{
gen_op_movl_A0_reg(R_EAX);
if (s->aflag == 0)
- gen_op_andl_A0_ffff();
+ tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
}
gen_add_A0_ds_seg(s);
gen_helper_monitor(cpu_env, cpu_A0);
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 32/49] target-i386: Use TCGMemOp for 'ot' variables
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (30 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 31/49] target-i386: Remove gen_op_andl_A0_ffff Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 33/49] target-i386: Change gen_op_add_reg_* size parameter to TCGMemOp Richard Henderson
` (16 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
The 'ot' variables (operand type?) hold the log2(byte size) of
the operand being manipulated. This is the same as the MO_SIZE
subset of the TCGMemOp. Indeed, we often pass 'ot' to the
tcg_gen_qemu_ld/st functions.
Changing the type from 'int' makes it easier to see what domain
the variable should be.
This does require adding some default cases to some switch statements,
to avoid the 'unhandled enumeration value' warning that would result
from the change of type.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 120 ++++++++++++++++++++++++++++--------------------
1 file changed, 70 insertions(+), 50 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index c3c51a6..10d1501 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -126,7 +126,7 @@ typedef struct DisasContext {
static void gen_eob(DisasContext *s);
static void gen_jmp(DisasContext *s, target_ulong eip);
static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
-static void gen_op(DisasContext *s1, int op, int ot, int d);
+static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d);
/* i386 arith/logic operations */
enum {
@@ -295,7 +295,7 @@ static inline bool byte_reg_is_xH(int reg)
return true;
}
-static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)
+static void gen_op_mov_reg_v(TCGMemOp ot, int reg, TCGv t0)
{
switch(ot) {
case MO_8:
@@ -308,7 +308,6 @@ static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)
case MO_16:
tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 16);
break;
- default: /* XXX this shouldn't be reached; abort? */
case MO_32:
/* For x86_64, this sets the higher half of register to zero.
For i386, this is equivalent to a mov. */
@@ -319,26 +318,27 @@ static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)
tcg_gen_mov_tl(cpu_regs[reg], t0);
break;
#endif
+ default:
+ tcg_abort();
}
}
-static inline void gen_op_mov_reg_T0(int ot, int reg)
+static inline void gen_op_mov_reg_T0(TCGMemOp ot, int reg)
{
gen_op_mov_reg_v(ot, reg, cpu_T[0]);
}
-static inline void gen_op_mov_reg_T1(int ot, int reg)
+static inline void gen_op_mov_reg_T1(TCGMemOp ot, int reg)
{
gen_op_mov_reg_v(ot, reg, cpu_T[1]);
}
-static inline void gen_op_mov_reg_A0(int size, int reg)
+static void gen_op_mov_reg_A0(TCGMemOp size, int reg)
{
- switch(size) {
+ switch (size) {
case MO_8:
tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_A0, 0, 16);
break;
- default: /* XXX this shouldn't be reached; abort? */
case MO_16:
/* For x86_64, this sets the higher half of register to zero.
For i386, this is equivalent to a mov. */
@@ -349,10 +349,12 @@ static inline void gen_op_mov_reg_A0(int size, int reg)
tcg_gen_mov_tl(cpu_regs[reg], cpu_A0);
break;
#endif
+ default:
+ tcg_abort();
}
}
-static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg)
+static inline void gen_op_mov_v_reg(TCGMemOp ot, TCGv t0, int reg)
{
if (ot == MO_8 && byte_reg_is_xH(reg)) {
tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8);
@@ -362,7 +364,7 @@ static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg)
}
}
-static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg)
+static inline void gen_op_mov_TN_reg(TCGMemOp ot, int t_index, int reg)
{
gen_op_mov_v_reg(ot, cpu_T[t_index], reg);
}
@@ -588,13 +590,13 @@ static inline void gen_string_movl_A0_EDI(DisasContext *s)
}
}
-static inline void gen_op_movl_T0_Dshift(int ot)
+static inline void gen_op_movl_T0_Dshift(TCGMemOp ot)
{
tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, df));
tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot);
};
-static TCGv gen_ext_tl(TCGv dst, TCGv src, int size, bool sign)
+static TCGv gen_ext_tl(TCGv dst, TCGv src, TCGMemOp size, bool sign)
{
switch (size) {
case MO_8:
@@ -625,12 +627,12 @@ static TCGv gen_ext_tl(TCGv dst, TCGv src, int size, bool sign)
}
}
-static void gen_extu(int ot, TCGv reg)
+static void gen_extu(TCGMemOp ot, TCGv reg)
{
gen_ext_tl(reg, reg, ot, false);
}
-static void gen_exts(int ot, TCGv reg)
+static void gen_exts(TCGMemOp ot, TCGv reg)
{
gen_ext_tl(reg, reg, ot, true);
}
@@ -649,7 +651,7 @@ static inline void gen_op_jz_ecx(int size, int label1)
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
}
-static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n)
+static void gen_helper_in_func(TCGMemOp ot, TCGv v, TCGv_i32 n)
{
switch (ot) {
case MO_8:
@@ -661,10 +663,12 @@ static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n)
case MO_32:
gen_helper_inl(v, n);
break;
+ default:
+ tcg_abort();
}
}
-static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n)
+static void gen_helper_out_func(TCGMemOp ot, TCGv_i32 v, TCGv_i32 n)
{
switch (ot) {
case MO_8:
@@ -676,10 +680,12 @@ static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n)
case MO_32:
gen_helper_outl(v, n);
break;
+ default:
+ tcg_abort();
}
}
-static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
+static void gen_check_io(DisasContext *s, TCGMemOp ot, target_ulong cur_eip,
uint32_t svm_flags)
{
int state_saved;
@@ -701,6 +707,8 @@ static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
case MO_32:
gen_helper_check_iol(cpu_env, cpu_tmp2_i32);
break;
+ default:
+ tcg_abort();
}
}
if(s->flags & HF_SVMI_MASK) {
@@ -717,7 +725,7 @@ static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
}
}
-static inline void gen_movs(DisasContext *s, int ot)
+static inline void gen_movs(DisasContext *s, TCGMemOp ot)
{
gen_string_movl_A0_ESI(s);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
@@ -911,7 +919,7 @@ static CCPrepare gen_prepare_eflags_s(DisasContext *s, TCGv reg)
return (CCPrepare) { .cond = TCG_COND_NEVER, .mask = -1 };
default:
{
- int size = (s->cc_op - CC_OP_ADDB) & 3;
+ TCGMemOp size = (s->cc_op - CC_OP_ADDB) & 3;
TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, true);
return (CCPrepare) { .cond = TCG_COND_LT, .reg = t0, .mask = -1 };
}
@@ -952,7 +960,7 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg)
return (CCPrepare) { .cond = TCG_COND_ALWAYS, .mask = -1 };
default:
{
- int size = (s->cc_op - CC_OP_ADDB) & 3;
+ TCGMemOp size = (s->cc_op - CC_OP_ADDB) & 3;
TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, false);
return (CCPrepare) { .cond = TCG_COND_EQ, .reg = t0, .mask = -1 };
}
@@ -963,7 +971,8 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg)
value 'b'. In the fast case, T0 is guaranted not to be used. */
static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
{
- int inv, jcc_op, size, cond;
+ int inv, jcc_op, cond;
+ TCGMemOp size;
CCPrepare cc;
TCGv t0;
@@ -1143,7 +1152,7 @@ static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
return l2;
}
-static inline void gen_stos(DisasContext *s, int ot)
+static inline void gen_stos(DisasContext *s, TCGMemOp ot)
{
gen_op_mov_TN_reg(MO_32, 0, R_EAX);
gen_string_movl_A0_EDI(s);
@@ -1152,7 +1161,7 @@ static inline void gen_stos(DisasContext *s, int ot)
gen_op_add_reg_T0(s->aflag, R_EDI);
}
-static inline void gen_lods(DisasContext *s, int ot)
+static inline void gen_lods(DisasContext *s, TCGMemOp ot)
{
gen_string_movl_A0_ESI(s);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
@@ -1161,7 +1170,7 @@ static inline void gen_lods(DisasContext *s, int ot)
gen_op_add_reg_T0(s->aflag, R_ESI);
}
-static inline void gen_scas(DisasContext *s, int ot)
+static inline void gen_scas(DisasContext *s, TCGMemOp ot)
{
gen_string_movl_A0_EDI(s);
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
@@ -1170,7 +1179,7 @@ static inline void gen_scas(DisasContext *s, int ot)
gen_op_add_reg_T0(s->aflag, R_EDI);
}
-static inline void gen_cmps(DisasContext *s, int ot)
+static inline void gen_cmps(DisasContext *s, TCGMemOp ot)
{
gen_string_movl_A0_EDI(s);
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
@@ -1181,7 +1190,7 @@ static inline void gen_cmps(DisasContext *s, int ot)
gen_op_add_reg_T0(s->aflag, R_EDI);
}
-static inline void gen_ins(DisasContext *s, int ot)
+static inline void gen_ins(DisasContext *s, TCGMemOp ot)
{
if (use_icount)
gen_io_start();
@@ -1200,7 +1209,7 @@ static inline void gen_ins(DisasContext *s, int ot)
gen_io_end();
}
-static inline void gen_outs(DisasContext *s, int ot)
+static inline void gen_outs(DisasContext *s, TCGMemOp ot)
{
if (use_icount)
gen_io_start();
@@ -1221,7 +1230,7 @@ static inline void gen_outs(DisasContext *s, int ot)
/* same method as Valgrind : we generate jumps to current or next
instruction */
#define GEN_REPZ(op) \
-static inline void gen_repz_ ## op(DisasContext *s, int ot, \
+static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
target_ulong cur_eip, target_ulong next_eip) \
{ \
int l2;\
@@ -1237,7 +1246,7 @@ static inline void gen_repz_ ## op(DisasContext *s, int ot, \
}
#define GEN_REPZ2(op) \
-static inline void gen_repz_ ## op(DisasContext *s, int ot, \
+static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
target_ulong cur_eip, \
target_ulong next_eip, \
int nz) \
@@ -1319,7 +1328,7 @@ static void gen_helper_fp_arith_STN_ST0(int op, int opreg)
}
/* if d == OR_TMP0, it means memory operand (address in A0) */
-static void gen_op(DisasContext *s1, int op, int ot, int d)
+static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d)
{
if (d != OR_TMP0) {
gen_op_mov_TN_reg(ot, 0, d);
@@ -1385,7 +1394,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
}
/* if d == OR_TMP0, it means memory operand (address in A0) */
-static void gen_inc(DisasContext *s1, int ot, int d, int c)
+static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c)
{
if (d != OR_TMP0) {
gen_op_mov_TN_reg(ot, 0, d);
@@ -1404,8 +1413,8 @@ static void gen_inc(DisasContext *s1, int ot, int d, int c)
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
}
-static void gen_shift_flags(DisasContext *s, int ot, TCGv result, TCGv shm1,
- TCGv count, bool is_right)
+static void gen_shift_flags(DisasContext *s, TCGMemOp ot, TCGv result,
+ TCGv shm1, TCGv count, bool is_right)
{
TCGv_i32 z32, s32, oldop;
TCGv z_tl;
@@ -1449,7 +1458,7 @@ static void gen_shift_flags(DisasContext *s, int ot, TCGv result, TCGv shm1,
set_cc_op(s, CC_OP_DYNAMIC);
}
-static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
+static void gen_shift_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
int is_right, int is_arith)
{
target_ulong mask = (ot == MO_64 ? 0x3f : 0x1f);
@@ -1485,7 +1494,7 @@ static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
gen_shift_flags(s, ot, cpu_T[0], cpu_tmp0, cpu_T[1], is_right);
}
-static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
+static void gen_shift_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,
int is_right, int is_arith)
{
int mask = (ot == MO_64 ? 0x3f : 0x1f);
@@ -1533,7 +1542,7 @@ static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2)
tcg_gen_shri_tl(ret, arg1, -arg2);
}
-static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, int is_right)
+static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right)
{
target_ulong mask = (ot == MO_64 ? 0x3f : 0x1f);
TCGv_i32 t0, t1;
@@ -1618,7 +1627,7 @@ static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, int is_right)
set_cc_op(s, CC_OP_DYNAMIC);
}
-static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
+static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,
int is_right)
{
int mask = (ot == MO_64 ? 0x3f : 0x1f);
@@ -1696,7 +1705,7 @@ static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
}
/* XXX: add faster immediate = 1 case */
-static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
+static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
int is_right)
{
gen_compute_eflags(s);
@@ -1724,6 +1733,8 @@ static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
gen_helper_rcrq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
#endif
+ default:
+ tcg_abort();
}
} else {
switch (ot) {
@@ -1741,6 +1752,8 @@ static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
gen_helper_rclq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
#endif
+ default:
+ tcg_abort();
}
}
/* store */
@@ -1748,7 +1761,7 @@ static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
}
/* XXX: add faster immediate case */
-static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1,
+static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
bool is_right, TCGv count_in)
{
target_ulong mask = (ot == MO_64 ? 63 : 31);
@@ -1829,7 +1842,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1,
tcg_temp_free(count);
}
-static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
+static void gen_shift(DisasContext *s1, int op, TCGMemOp ot, int d, int s)
{
if (s != OR_TMP1)
gen_op_mov_TN_reg(ot, 1, s);
@@ -1859,7 +1872,7 @@ static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
}
}
-static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
+static void gen_shifti(DisasContext *s1, int op, TCGMemOp ot, int d, int c)
{
switch(op) {
case OP_ROL:
@@ -2140,7 +2153,7 @@ static void gen_add_A0_ds_seg(DisasContext *s)
/* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
OR_TMP0 */
static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
- int ot, int reg, int is_store)
+ TCGMemOp ot, int reg, int is_store)
{
int mod, rm;
@@ -2170,11 +2183,11 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
}
}
-static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, int ot)
+static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, TCGMemOp ot)
{
uint32_t ret;
- switch(ot) {
+ switch (ot) {
case MO_8:
ret = cpu_ldub_code(env, s->pc);
s->pc++;
@@ -2183,16 +2196,20 @@ static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, int ot)
ret = cpu_lduw_code(env, s->pc);
s->pc += 2;
break;
- default:
case MO_32:
+#ifdef TARGET_X86_64
+ case MO_64:
+#endif
ret = cpu_ldl_code(env, s->pc);
s->pc += 4;
break;
+ default:
+ tcg_abort();
}
return ret;
}
-static inline int insn_const_size(unsigned int ot)
+static inline int insn_const_size(TCGMemOp ot)
{
if (ot <= MO_32) {
return 1 << ot;
@@ -2251,7 +2268,7 @@ static inline void gen_jcc(DisasContext *s, int b,
}
}
-static void gen_cmovcc1(CPUX86State *env, DisasContext *s, int ot, int b,
+static void gen_cmovcc1(CPUX86State *env, DisasContext *s, TCGMemOp ot, int b,
int modrm, int reg)
{
CCPrepare cc;
@@ -2524,7 +2541,8 @@ static void gen_popa(DisasContext *s)
static void gen_enter(DisasContext *s, int esp_addend, int level)
{
- int ot, opsize;
+ TCGMemOp ot;
+ int opsize;
level &= 0x1f;
#ifdef TARGET_X86_64
@@ -3036,12 +3054,13 @@ static const struct SSEOpHelper_eppi sse_op_table7[256] = {
static void gen_sse(CPUX86State *env, DisasContext *s, int b,
target_ulong pc_start, int rex_r)
{
- int b1, op1_offset, op2_offset, is_xmm, val, ot;
+ int b1, op1_offset, op2_offset, is_xmm, val;
int modrm, mod, rm, reg;
SSEFunc_0_epp sse_fn_epp;
SSEFunc_0_eppi sse_fn_eppi;
SSEFunc_0_ppi sse_fn_ppi;
SSEFunc_0_eppt sse_fn_eppt;
+ TCGMemOp ot;
b &= 0xff;
if (s->prefix & PREFIX_DATA)
@@ -4445,7 +4464,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
target_ulong pc_start)
{
int b, prefixes, aflag, dflag;
- int shift, ot;
+ int shift;
+ TCGMemOp ot;
int modrm, reg, rm, mod, op, opreg, val;
target_ulong next_eip, tval;
int rex_w, rex_r;
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 33/49] target-i386: Change gen_op_add_reg_* size parameter to TCGMemOp
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (31 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 32/49] target-i386: Use TCGMemOp for 'ot' variables Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 34/49] target-i386: Change gen_op_j*z_ecx " Richard Henderson
` (15 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
These functions used the aflags/dflags domain, which is log2-1
of the byte size. Confusingly, they used enumeration values
from the log2 domain.
Change the domain of the parameter and update all callers.
Since we're now in a common domain, defer the deposit/extend/mov
decision to gen_op_mov_reg_v.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 76 ++++++++++++++-----------------------------------
1 file changed, 22 insertions(+), 54 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 10d1501..47897b4 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -409,48 +409,16 @@ static inline void gen_op_jmp_T0(void)
tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, eip));
}
-static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
+static inline void gen_op_add_reg_im(TCGMemOp size, int reg, int32_t val)
{
- switch(size) {
- case MO_8:
- tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
- tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16);
- break;
- case MO_16:
- tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
- /* For x86_64, this sets the higher half of register to zero.
- For i386, this is equivalent to a nop. */
- tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
- tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
- break;
-#ifdef TARGET_X86_64
- case MO_32:
- tcg_gen_addi_tl(cpu_regs[reg], cpu_regs[reg], val);
- break;
-#endif
- }
+ tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
+ gen_op_mov_reg_v(size, reg, cpu_tmp0);
}
-static inline void gen_op_add_reg_T0(int size, int reg)
+static inline void gen_op_add_reg_T0(TCGMemOp size, int reg)
{
- switch(size) {
- case MO_8:
- tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
- tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16);
- break;
- case MO_16:
- tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
- /* For x86_64, this sets the higher half of register to zero.
- For i386, this is equivalent to a nop. */
- tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
- tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
- break;
-#ifdef TARGET_X86_64
- case MO_32:
- tcg_gen_add_tl(cpu_regs[reg], cpu_regs[reg], cpu_T[0]);
- break;
-#endif
- }
+ tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
+ gen_op_mov_reg_v(size, reg, cpu_tmp0);
}
static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
@@ -732,8 +700,8 @@ static inline void gen_movs(DisasContext *s, TCGMemOp ot)
gen_string_movl_A0_EDI(s);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag, R_ESI);
- gen_op_add_reg_T0(s->aflag, R_EDI);
+ gen_op_add_reg_T0(s->aflag + 1, R_ESI);
+ gen_op_add_reg_T0(s->aflag + 1, R_EDI);
}
static void gen_op_update1_cc(void)
@@ -1158,7 +1126,7 @@ static inline void gen_stos(DisasContext *s, TCGMemOp ot)
gen_string_movl_A0_EDI(s);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag, R_EDI);
+ gen_op_add_reg_T0(s->aflag + 1, R_EDI);
}
static inline void gen_lods(DisasContext *s, TCGMemOp ot)
@@ -1167,7 +1135,7 @@ static inline void gen_lods(DisasContext *s, TCGMemOp ot)
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
gen_op_mov_reg_T0(ot, R_EAX);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag, R_ESI);
+ gen_op_add_reg_T0(s->aflag + 1, R_ESI);
}
static inline void gen_scas(DisasContext *s, TCGMemOp ot)
@@ -1176,7 +1144,7 @@ static inline void gen_scas(DisasContext *s, TCGMemOp ot)
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
gen_op(s, OP_CMPL, ot, R_EAX);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag, R_EDI);
+ gen_op_add_reg_T0(s->aflag + 1, R_EDI);
}
static inline void gen_cmps(DisasContext *s, TCGMemOp ot)
@@ -1186,8 +1154,8 @@ static inline void gen_cmps(DisasContext *s, TCGMemOp ot)
gen_string_movl_A0_ESI(s);
gen_op(s, OP_CMPL, ot, OR_TMP0);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag, R_ESI);
- gen_op_add_reg_T0(s->aflag, R_EDI);
+ gen_op_add_reg_T0(s->aflag + 1, R_ESI);
+ gen_op_add_reg_T0(s->aflag + 1, R_EDI);
}
static inline void gen_ins(DisasContext *s, TCGMemOp ot)
@@ -1204,7 +1172,7 @@ static inline void gen_ins(DisasContext *s, TCGMemOp ot)
gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag, R_EDI);
+ gen_op_add_reg_T0(s->aflag + 1, R_EDI);
if (use_icount)
gen_io_end();
}
@@ -1222,7 +1190,7 @@ static inline void gen_outs(DisasContext *s, TCGMemOp ot)
gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag, R_ESI);
+ gen_op_add_reg_T0(s->aflag + 1, R_ESI);
if (use_icount)
gen_io_end();
}
@@ -1237,7 +1205,7 @@ static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
gen_update_cc_op(s); \
l2 = gen_jz_ecx_string(s, next_eip); \
gen_ ## op(s, ot); \
- gen_op_add_reg_im(s->aflag, R_ECX, -1); \
+ gen_op_add_reg_im(s->aflag + 1, R_ECX, -1); \
/* a loop would cause two single step exceptions if ECX = 1 \
before rep string_insn */ \
if (!s->jmp_opt) \
@@ -1255,7 +1223,7 @@ static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
gen_update_cc_op(s); \
l2 = gen_jz_ecx_string(s, next_eip); \
gen_ ## op(s, ot); \
- gen_op_add_reg_im(s->aflag, R_ECX, -1); \
+ gen_op_add_reg_im(s->aflag + 1, R_ECX, -1); \
gen_update_cc_op(s); \
gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); \
if (!s->jmp_opt) \
@@ -2364,13 +2332,13 @@ static inline void gen_stack_update(DisasContext *s, int addend)
{
#ifdef TARGET_X86_64
if (CODE64(s)) {
- gen_op_add_reg_im(2, R_ESP, addend);
+ gen_op_add_reg_im(MO_64, R_ESP, addend);
} else
#endif
if (s->ss32) {
- gen_op_add_reg_im(1, R_ESP, addend);
+ gen_op_add_reg_im(MO_32, R_ESP, addend);
} else {
- gen_op_add_reg_im(0, R_ESP, addend);
+ gen_op_add_reg_im(MO_16, R_ESP, addend);
}
}
@@ -7165,12 +7133,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
switch(b) {
case 0: /* loopnz */
case 1: /* loopz */
- gen_op_add_reg_im(s->aflag, R_ECX, -1);
+ gen_op_add_reg_im(s->aflag + 1, R_ECX, -1);
gen_op_jz_ecx(s->aflag, l3);
gen_jcc1(s, (JCC_Z << 1) | (b ^ 1), l1);
break;
case 2: /* loop */
- gen_op_add_reg_im(s->aflag, R_ECX, -1);
+ gen_op_add_reg_im(s->aflag + 1, R_ECX, -1);
gen_op_jnz_ecx(s->aflag, l1);
break;
default:
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 34/49] target-i386: Change gen_op_j*z_ecx size parameter to TCGMemOp
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (32 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 33/49] target-i386: Change gen_op_add_reg_* size parameter to TCGMemOp Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 35/49] target-i386: Change aflag " Richard Henderson
` (14 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Change the domain of the parameter and update all callers.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 47897b4..f1b4932 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -605,17 +605,17 @@ static void gen_exts(TCGMemOp ot, TCGv reg)
gen_ext_tl(reg, reg, ot, true);
}
-static inline void gen_op_jnz_ecx(int size, int label1)
+static inline void gen_op_jnz_ecx(TCGMemOp size, int label1)
{
tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
- gen_extu(size + 1, cpu_tmp0);
+ gen_extu(size, cpu_tmp0);
tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1);
}
-static inline void gen_op_jz_ecx(int size, int label1)
+static inline void gen_op_jz_ecx(TCGMemOp size, int label1)
{
tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
- gen_extu(size + 1, cpu_tmp0);
+ gen_extu(size, cpu_tmp0);
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
}
@@ -1113,7 +1113,7 @@ static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
l1 = gen_new_label();
l2 = gen_new_label();
- gen_op_jnz_ecx(s->aflag, l1);
+ gen_op_jnz_ecx(s->aflag + 1, l1);
gen_set_label(l2);
gen_jmp_tb(s, next_eip, 1);
gen_set_label(l1);
@@ -1209,7 +1209,7 @@ static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
/* a loop would cause two single step exceptions if ECX = 1 \
before rep string_insn */ \
if (!s->jmp_opt) \
- gen_op_jz_ecx(s->aflag, l2); \
+ gen_op_jz_ecx(s->aflag + 1, l2); \
gen_jmp(s, cur_eip); \
}
@@ -1227,7 +1227,7 @@ static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
gen_update_cc_op(s); \
gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); \
if (!s->jmp_opt) \
- gen_op_jz_ecx(s->aflag, l2); \
+ gen_op_jz_ecx(s->aflag + 1, l2); \
gen_jmp(s, cur_eip); \
}
@@ -7134,16 +7134,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0: /* loopnz */
case 1: /* loopz */
gen_op_add_reg_im(s->aflag + 1, R_ECX, -1);
- gen_op_jz_ecx(s->aflag, l3);
+ gen_op_jz_ecx(s->aflag + 1, l3);
gen_jcc1(s, (JCC_Z << 1) | (b ^ 1), l1);
break;
case 2: /* loop */
gen_op_add_reg_im(s->aflag + 1, R_ECX, -1);
- gen_op_jnz_ecx(s->aflag, l1);
+ gen_op_jnz_ecx(s->aflag + 1, l1);
break;
default:
case 3: /* jcxz */
- gen_op_jz_ecx(s->aflag, l1);
+ gen_op_jz_ecx(s->aflag + 1, l1);
break;
}
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 35/49] target-i386: Change aflag to TCGMemOp
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (33 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 34/49] target-i386: Change gen_op_j*z_ecx " Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 36/49] target-i386: Change gen_op_mov_reg_A0 size parameter " Richard Henderson
` (13 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Changing the domain to TCGMemOp makes it easier to interoperate
with other portions of the rest of the translator.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 178 +++++++++++++++++++++++-------------------------
1 file changed, 87 insertions(+), 91 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index f1b4932..8861973 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -85,7 +85,8 @@ typedef struct DisasContext {
/* current insn context */
int override; /* -1 if no override */
int prefix;
- int aflag, dflag;
+ TCGMemOp aflag;
+ int dflag;
target_ulong pc; /* pc = eip + cs_base */
int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
static state change (stop translation) */
@@ -509,17 +510,18 @@ static inline void gen_string_movl_A0_ESI(DisasContext *s)
int override;
override = s->override;
+ switch (s->aflag) {
#ifdef TARGET_X86_64
- if (s->aflag == 2) {
+ case MO_64:
if (override >= 0) {
gen_op_movq_A0_seg(override);
gen_op_addq_A0_reg_sN(0, R_ESI);
} else {
gen_op_movq_A0_reg(R_ESI);
}
- } else
+ break;
#endif
- if (s->aflag) {
+ case MO_32:
/* 32 bit address */
if (s->addseg && override < 0)
override = R_DS;
@@ -529,32 +531,41 @@ static inline void gen_string_movl_A0_ESI(DisasContext *s)
} else {
gen_op_movl_A0_reg(R_ESI);
}
- } else {
+ break;
+ case MO_16:
/* 16 address, always override */
if (override < 0)
override = R_DS;
tcg_gen_ext16u_tl(cpu_A0, cpu_regs[R_ESI]);
gen_op_addl_A0_seg(s, override);
+ break;
+ default:
+ tcg_abort();
}
}
static inline void gen_string_movl_A0_EDI(DisasContext *s)
{
+ switch (s->aflag) {
#ifdef TARGET_X86_64
- if (s->aflag == 2) {
+ case MO_64:
gen_op_movq_A0_reg(R_EDI);
- } else
+ break;
#endif
- if (s->aflag) {
+ case MO_32:
if (s->addseg) {
gen_op_movl_A0_seg(R_ES);
gen_op_addl_A0_reg_sN(0, R_EDI);
} else {
gen_op_movl_A0_reg(R_EDI);
}
- } else {
+ break;
+ case MO_16:
tcg_gen_ext16u_tl(cpu_A0, cpu_regs[R_EDI]);
gen_op_addl_A0_seg(s, R_ES);
+ break;
+ default:
+ tcg_abort();
}
}
@@ -700,8 +711,8 @@ static inline void gen_movs(DisasContext *s, TCGMemOp ot)
gen_string_movl_A0_EDI(s);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag + 1, R_ESI);
- gen_op_add_reg_T0(s->aflag + 1, R_EDI);
+ gen_op_add_reg_T0(s->aflag, R_ESI);
+ gen_op_add_reg_T0(s->aflag, R_EDI);
}
static void gen_op_update1_cc(void)
@@ -1113,7 +1124,7 @@ static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
l1 = gen_new_label();
l2 = gen_new_label();
- gen_op_jnz_ecx(s->aflag + 1, l1);
+ gen_op_jnz_ecx(s->aflag, l1);
gen_set_label(l2);
gen_jmp_tb(s, next_eip, 1);
gen_set_label(l1);
@@ -1126,7 +1137,7 @@ static inline void gen_stos(DisasContext *s, TCGMemOp ot)
gen_string_movl_A0_EDI(s);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag + 1, R_EDI);
+ gen_op_add_reg_T0(s->aflag, R_EDI);
}
static inline void gen_lods(DisasContext *s, TCGMemOp ot)
@@ -1135,7 +1146,7 @@ static inline void gen_lods(DisasContext *s, TCGMemOp ot)
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
gen_op_mov_reg_T0(ot, R_EAX);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag + 1, R_ESI);
+ gen_op_add_reg_T0(s->aflag, R_ESI);
}
static inline void gen_scas(DisasContext *s, TCGMemOp ot)
@@ -1144,7 +1155,7 @@ static inline void gen_scas(DisasContext *s, TCGMemOp ot)
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
gen_op(s, OP_CMPL, ot, R_EAX);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag + 1, R_EDI);
+ gen_op_add_reg_T0(s->aflag, R_EDI);
}
static inline void gen_cmps(DisasContext *s, TCGMemOp ot)
@@ -1154,8 +1165,8 @@ static inline void gen_cmps(DisasContext *s, TCGMemOp ot)
gen_string_movl_A0_ESI(s);
gen_op(s, OP_CMPL, ot, OR_TMP0);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag + 1, R_ESI);
- gen_op_add_reg_T0(s->aflag + 1, R_EDI);
+ gen_op_add_reg_T0(s->aflag, R_ESI);
+ gen_op_add_reg_T0(s->aflag, R_EDI);
}
static inline void gen_ins(DisasContext *s, TCGMemOp ot)
@@ -1172,7 +1183,7 @@ static inline void gen_ins(DisasContext *s, TCGMemOp ot)
gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag + 1, R_EDI);
+ gen_op_add_reg_T0(s->aflag, R_EDI);
if (use_icount)
gen_io_end();
}
@@ -1190,7 +1201,7 @@ static inline void gen_outs(DisasContext *s, TCGMemOp ot)
gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag + 1, R_ESI);
+ gen_op_add_reg_T0(s->aflag, R_ESI);
if (use_icount)
gen_io_end();
}
@@ -1205,11 +1216,11 @@ static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
gen_update_cc_op(s); \
l2 = gen_jz_ecx_string(s, next_eip); \
gen_ ## op(s, ot); \
- gen_op_add_reg_im(s->aflag + 1, R_ECX, -1); \
+ gen_op_add_reg_im(s->aflag, R_ECX, -1); \
/* a loop would cause two single step exceptions if ECX = 1 \
before rep string_insn */ \
if (!s->jmp_opt) \
- gen_op_jz_ecx(s->aflag + 1, l2); \
+ gen_op_jz_ecx(s->aflag, l2); \
gen_jmp(s, cur_eip); \
}
@@ -1223,11 +1234,11 @@ static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
gen_update_cc_op(s); \
l2 = gen_jz_ecx_string(s, next_eip); \
gen_ ## op(s, ot); \
- gen_op_add_reg_im(s->aflag + 1, R_ECX, -1); \
+ gen_op_add_reg_im(s->aflag, R_ECX, -1); \
gen_update_cc_op(s); \
gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); \
if (!s->jmp_opt) \
- gen_op_jz_ecx(s->aflag + 1, l2); \
+ gen_op_jz_ecx(s->aflag, l2); \
gen_jmp(s, cur_eip); \
}
@@ -1884,7 +1895,9 @@ static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm)
mod = (modrm >> 6) & 3;
rm = modrm & 7;
- if (s->aflag) {
+ switch (s->aflag) {
+ case MO_64:
+ case MO_32:
havesib = 0;
base = rm;
index = -1;
@@ -1964,7 +1977,7 @@ static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm)
tcg_gen_ld_tl(cpu_tmp0, cpu_env,
offsetof(CPUX86State, segs[override].base));
if (CODE64(s)) {
- if (s->aflag != 2) {
+ if (s->aflag == MO_32) {
tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
}
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
@@ -1974,10 +1987,12 @@ static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm)
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
}
- if (s->aflag != 2) {
+ if (s->aflag == MO_32) {
tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
}
- } else {
+ break;
+
+ case MO_16:
switch (mod) {
case 0:
if (rm == 6) {
@@ -2043,6 +2058,10 @@ static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm)
}
gen_op_addl_A0_seg(s, override);
}
+ break;
+
+ default:
+ tcg_abort();
}
}
@@ -2055,8 +2074,9 @@ static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm)
return;
rm = modrm & 7;
- if (s->aflag) {
-
+ switch (s->aflag) {
+ case MO_64:
+ case MO_32:
base = rm;
if (base == 4) {
@@ -2078,7 +2098,9 @@ static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm)
s->pc += 4;
break;
}
- } else {
+ break;
+
+ case MO_16:
switch (mod) {
case 0:
if (rm == 6) {
@@ -2093,6 +2115,10 @@ static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm)
s->pc += 2;
break;
}
+ break;
+
+ default:
+ tcg_abort();
}
}
@@ -4396,16 +4422,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
/* maskmov : we must prepare A0 */
if (mod != 3)
goto illegal_op;
-#ifdef TARGET_X86_64
- if (s->aflag == 2) {
- gen_op_movq_A0_reg(R_EDI);
- } else
-#endif
- {
- gen_op_movl_A0_reg(R_EDI);
- if (s->aflag == 0)
- tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
- }
+ tcg_gen_mov_tl(cpu_A0, cpu_regs[R_EDI]);
+ gen_extu(s->aflag, cpu_A0);
gen_add_A0_ds_seg(s);
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
@@ -4431,9 +4449,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
target_ulong pc_start)
{
- int b, prefixes, aflag, dflag;
+ int b, prefixes, dflag;
int shift;
- TCGMemOp ot;
+ TCGMemOp ot, aflag;
int modrm, reg, rm, mod, op, opreg, val;
target_ulong next_eip, tval;
int rex_w, rex_r;
@@ -4571,7 +4589,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
over 0x66 if both are present. */
dflag = (rex_w > 0 ? 2 : prefixes & PREFIX_DATA ? 0 : 1);
/* In 64-bit mode, 0x67 selects 32-bit addressing. */
- aflag = (prefixes & PREFIX_ADR ? 1 : 2);
+ aflag = (prefixes & PREFIX_ADR ? MO_32 : MO_64);
} else {
/* In 16/32-bit mode, 0x66 selects the opposite data size. */
dflag = s->code32;
@@ -4579,9 +4597,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
dflag ^= 1;
}
/* In 16/32-bit mode, 0x67 selects the opposite addressing. */
- aflag = s->code32;
- if (prefixes & PREFIX_ADR) {
- aflag ^= 1;
+ if (s->code32 ^ ((prefixes & PREFIX_ADR) != 0)) {
+ aflag = MO_32;
+ } else {
+ aflag = MO_16;
}
}
@@ -5561,18 +5580,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
ot = MO_8;
else
ot = dflag + MO_16;
+ switch (s->aflag) {
#ifdef TARGET_X86_64
- if (s->aflag == 2) {
+ case MO_64:
offset_addr = cpu_ldq_code(env, s->pc);
s->pc += 8;
- } else
+ break;
#endif
- {
- if (s->aflag) {
- offset_addr = insn_get(env, s, MO_32);
- } else {
- offset_addr = insn_get(env, s, MO_16);
- }
+ default:
+ offset_addr = insn_get(env, s, s->aflag);
+ break;
}
tcg_gen_movi_tl(cpu_A0, offset_addr);
gen_add_A0_ds_seg(s);
@@ -5586,24 +5603,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
break;
case 0xd7: /* xlat */
-#ifdef TARGET_X86_64
- if (s->aflag == 2) {
- gen_op_movq_A0_reg(R_EBX);
- gen_op_mov_TN_reg(MO_64, 0, R_EAX);
- tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
- tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
- } else
-#endif
- {
- gen_op_movl_A0_reg(R_EBX);
- gen_op_mov_TN_reg(MO_32, 0, R_EAX);
- tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
- tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
- if (s->aflag == 0)
- tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
- else
- tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
- }
+ tcg_gen_mov_tl(cpu_A0, cpu_regs[R_EBX]);
+ tcg_gen_ext8u_tl(cpu_T[0], cpu_regs[R_EAX]);
+ tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
+ gen_extu(s->aflag, cpu_A0);
gen_add_A0_ds_seg(s);
gen_op_ld_v(s, MO_8, cpu_T[0], cpu_A0);
gen_op_mov_reg_T0(MO_8, R_EAX);
@@ -7133,17 +7136,17 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
switch(b) {
case 0: /* loopnz */
case 1: /* loopz */
- gen_op_add_reg_im(s->aflag + 1, R_ECX, -1);
- gen_op_jz_ecx(s->aflag + 1, l3);
+ gen_op_add_reg_im(s->aflag, R_ECX, -1);
+ gen_op_jz_ecx(s->aflag, l3);
gen_jcc1(s, (JCC_Z << 1) | (b ^ 1), l1);
break;
case 2: /* loop */
- gen_op_add_reg_im(s->aflag + 1, R_ECX, -1);
- gen_op_jnz_ecx(s->aflag + 1, l1);
+ gen_op_add_reg_im(s->aflag, R_ECX, -1);
+ gen_op_jnz_ecx(s->aflag, l1);
break;
default:
case 3: /* jcxz */
- gen_op_jz_ecx(s->aflag + 1, l1);
+ gen_op_jz_ecx(s->aflag, l1);
break;
}
@@ -7348,16 +7351,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
-#ifdef TARGET_X86_64
- if (s->aflag == 2) {
- gen_op_movq_A0_reg(R_EAX);
- } else
-#endif
- {
- gen_op_movl_A0_reg(R_EAX);
- if (s->aflag == 0)
- tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
- }
+ tcg_gen_mov_tl(cpu_A0, cpu_regs[R_EAX]);
+ gen_extu(s->aflag, cpu_A0);
gen_add_A0_ds_seg(s);
gen_helper_monitor(cpu_env, cpu_A0);
break;
@@ -7417,7 +7412,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
break;
} else {
- gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag),
+ gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag - 1),
tcg_const_i32(s->pc - pc_start));
tcg_gen_exit_tb(0);
s->is_jmp = DISAS_TB_JUMP;
@@ -7435,7 +7430,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
break;
} else {
- gen_helper_vmload(cpu_env, tcg_const_i32(s->aflag));
+ gen_helper_vmload(cpu_env, tcg_const_i32(s->aflag - 1));
}
break;
case 3: /* VMSAVE */
@@ -7445,7 +7440,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
break;
} else {
- gen_helper_vmsave(cpu_env, tcg_const_i32(s->aflag));
+ gen_helper_vmsave(cpu_env, tcg_const_i32(s->aflag - 1));
}
break;
case 4: /* STGI */
@@ -7484,7 +7479,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
break;
} else {
- gen_helper_invlpga(cpu_env, tcg_const_i32(s->aflag));
+ gen_helper_invlpga(cpu_env,
+ tcg_const_i32(s->aflag - 1));
}
break;
default:
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 36/49] target-i386: Change gen_op_mov_reg_A0 size parameter to TCGMemOp
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (34 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 35/49] target-i386: Change aflag " Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 37/49] target-i386: Change dflag " Richard Henderson
` (12 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Change the domain of the parameter and update all callers.
Which lets us defer completely to gen_op_mov_reg_v.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 32 ++++++++------------------------
1 file changed, 8 insertions(+), 24 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 8861973..9b191ad 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -334,25 +334,9 @@ static inline void gen_op_mov_reg_T1(TCGMemOp ot, int reg)
gen_op_mov_reg_v(ot, reg, cpu_T[1]);
}
-static void gen_op_mov_reg_A0(TCGMemOp size, int reg)
+static inline void gen_op_mov_reg_A0(TCGMemOp size, int reg)
{
- switch (size) {
- case MO_8:
- tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_A0, 0, 16);
- break;
- case MO_16:
- /* For x86_64, this sets the higher half of register to zero.
- For i386, this is equivalent to a mov. */
- tcg_gen_ext32u_tl(cpu_regs[reg], cpu_A0);
- break;
-#ifdef TARGET_X86_64
- case MO_32:
- tcg_gen_mov_tl(cpu_regs[reg], cpu_A0);
- break;
-#endif
- default:
- tcg_abort();
- }
+ gen_op_mov_reg_v(size, reg, cpu_A0);
}
static inline void gen_op_mov_v_reg(TCGMemOp ot, TCGv t0, int reg)
@@ -2381,7 +2365,7 @@ static void gen_push_T0(DisasContext *s)
gen_op_addq_A0_im(-2);
gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
}
- gen_op_mov_reg_A0(2, R_ESP);
+ gen_op_mov_reg_A0(MO_64, R_ESP);
} else
#endif
{
@@ -2402,9 +2386,9 @@ static void gen_push_T0(DisasContext *s)
}
gen_op_st_v(s, s->dflag + 1, cpu_T[0], cpu_A0);
if (s->ss32 && !s->addseg)
- gen_op_mov_reg_A0(1, R_ESP);
+ gen_op_mov_reg_A0(MO_32, R_ESP);
else
- gen_op_mov_reg_T1(s->ss32 + 1, R_ESP);
+ gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
}
}
@@ -2422,7 +2406,7 @@ static void gen_push_T1(DisasContext *s)
gen_op_addq_A0_im(-2);
gen_op_st_v(s, MO_16, cpu_T[1], cpu_A0);
}
- gen_op_mov_reg_A0(2, R_ESP);
+ gen_op_mov_reg_A0(MO_64, R_ESP);
} else
#endif
{
@@ -2442,7 +2426,7 @@ static void gen_push_T1(DisasContext *s)
gen_op_st_v(s, s->dflag + 1, cpu_T[1], cpu_A0);
if (s->ss32 && !s->addseg)
- gen_op_mov_reg_A0(1, R_ESP);
+ gen_op_mov_reg_A0(MO_32, R_ESP);
else
gen_stack_update(s, (-2) << s->dflag);
}
@@ -5566,7 +5550,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
s->addseg = 0;
gen_lea_modrm(env, s, modrm);
s->addseg = val;
- gen_op_mov_reg_A0(ot - MO_16, reg);
+ gen_op_mov_reg_A0(ot, reg);
break;
case 0xa0: /* mov EAX, Ov */
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 37/49] target-i386: Change dflag to TCGMemOp
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (35 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 36/49] target-i386: Change gen_op_mov_reg_A0 size parameter " Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 38/49] target-i386: Tidy addr16 code in gen_lea_modrm Richard Henderson
` (11 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Changing the domain to TCGMemOp makes it easier to interoperate
with other portions of the rest of the translator.
We now only have one domain for size operands inside the translator,
which makes things less confusing all the way around. There are
still a number of helpers that continue to use the log2-1 domain.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 500 +++++++++++++++++++++---------------------------
1 file changed, 216 insertions(+), 284 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 9b191ad..9f38adf 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -86,7 +86,7 @@ typedef struct DisasContext {
int override; /* -1 if no override */
int prefix;
TCGMemOp aflag;
- int dflag;
+ TCGMemOp dflag;
target_ulong pc; /* pc = eip + cs_base */
int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
static state change (stop translation) */
@@ -296,6 +296,40 @@ static inline bool byte_reg_is_xH(int reg)
return true;
}
+/* Select the size of a push/pop operation. */
+static inline TCGMemOp mo_pushpop(DisasContext *s, TCGMemOp ot)
+{
+ if (CODE64(s)) {
+ return ot == MO_16 ? MO_16 : MO_64;
+ } else {
+ return ot;
+ }
+}
+
+/* Select only size 64 else 32. Used for SSE operand sizes. */
+static inline TCGMemOp mo_64_32(TCGMemOp ot)
+{
+#ifdef TARGET_X86_64
+ return ot == MO_64 ? MO_64 : MO_32;
+#else
+ return MO_32;
+#endif
+}
+
+/* Select size 8 if lsb of B is clear, else OT. Used for decoding
+ byte vs word opcodes. */
+static inline TCGMemOp mo_b_d(int b, TCGMemOp ot)
+{
+ return b & 1 ? ot : MO_8;
+}
+
+/* Select size 8 if lsb of B is clear, else OT capped at 32.
+ Used for decoding operand size of port opcodes. */
+static inline TCGMemOp mo_b_d32(int b, TCGMemOp ot)
+{
+ return b & 1 ? (ot == MO_16 ? MO_16 : MO_32) : MO_8;
+}
+
static void gen_op_mov_reg_v(TCGMemOp ot, int reg, TCGv t0)
{
switch(ot) {
@@ -2358,7 +2392,7 @@ static void gen_push_T0(DisasContext *s)
#ifdef TARGET_X86_64
if (CODE64(s)) {
gen_op_movq_A0_reg(R_ESP);
- if (s->dflag) {
+ if (s->dflag != MO_16) {
gen_op_addq_A0_im(-8);
gen_op_st_v(s, MO_64, cpu_T[0], cpu_A0);
} else {
@@ -2370,10 +2404,7 @@ static void gen_push_T0(DisasContext *s)
#endif
{
gen_op_movl_A0_reg(R_ESP);
- if (!s->dflag)
- gen_op_addl_A0_im(-2);
- else
- gen_op_addl_A0_im(-4);
+ gen_op_addl_A0_im(-1 << s->dflag);
if (s->ss32) {
if (s->addseg) {
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
@@ -2384,7 +2415,7 @@ static void gen_push_T0(DisasContext *s)
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
gen_op_addl_A0_seg(s, R_SS);
}
- gen_op_st_v(s, s->dflag + 1, cpu_T[0], cpu_A0);
+ gen_op_st_v(s, s->dflag, cpu_T[0], cpu_A0);
if (s->ss32 && !s->addseg)
gen_op_mov_reg_A0(MO_32, R_ESP);
else
@@ -2399,7 +2430,7 @@ static void gen_push_T1(DisasContext *s)
#ifdef TARGET_X86_64
if (CODE64(s)) {
gen_op_movq_A0_reg(R_ESP);
- if (s->dflag) {
+ if (s->dflag != MO_16) {
gen_op_addq_A0_im(-8);
gen_op_st_v(s, MO_64, cpu_T[1], cpu_A0);
} else {
@@ -2411,10 +2442,7 @@ static void gen_push_T1(DisasContext *s)
#endif
{
gen_op_movl_A0_reg(R_ESP);
- if (!s->dflag)
- gen_op_addl_A0_im(-2);
- else
- gen_op_addl_A0_im(-4);
+ gen_op_addl_A0_im(-1 << s->dflag);
if (s->ss32) {
if (s->addseg) {
gen_op_addl_A0_seg(s, R_SS);
@@ -2423,12 +2451,12 @@ static void gen_push_T1(DisasContext *s)
tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
gen_op_addl_A0_seg(s, R_SS);
}
- gen_op_st_v(s, s->dflag + 1, cpu_T[1], cpu_A0);
+ gen_op_st_v(s, s->dflag, cpu_T[1], cpu_A0);
if (s->ss32 && !s->addseg)
gen_op_mov_reg_A0(MO_32, R_ESP);
else
- gen_stack_update(s, (-2) << s->dflag);
+ gen_stack_update(s, -1 << s->dflag);
}
}
@@ -2438,7 +2466,7 @@ static void gen_pop_T0(DisasContext *s)
#ifdef TARGET_X86_64
if (CODE64(s)) {
gen_op_movq_A0_reg(R_ESP);
- gen_op_ld_v(s, s->dflag ? MO_64 : MO_16, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, mo_pushpop(s, s->dflag), cpu_T[0], cpu_A0);
} else
#endif
{
@@ -2450,20 +2478,13 @@ static void gen_pop_T0(DisasContext *s)
tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
gen_op_addl_A0_seg(s, R_SS);
}
- gen_op_ld_v(s, s->dflag + 1, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, s->dflag, cpu_T[0], cpu_A0);
}
}
static void gen_pop_update(DisasContext *s)
{
-#ifdef TARGET_X86_64
- if (CODE64(s) && s->dflag) {
- gen_stack_update(s, 8);
- } else
-#endif
- {
- gen_stack_update(s, 2 << s->dflag);
- }
+ gen_stack_update(s, 1 << mo_pushpop(s, s->dflag));
}
static void gen_stack_A0(DisasContext *s)
@@ -2481,7 +2502,7 @@ static void gen_pusha(DisasContext *s)
{
int i;
gen_op_movl_A0_reg(R_ESP);
- gen_op_addl_A0_im(-16 << s->dflag);
+ gen_op_addl_A0_im(-8 << s->dflag);
if (!s->ss32)
tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
@@ -2489,8 +2510,8 @@ static void gen_pusha(DisasContext *s)
gen_op_addl_A0_seg(s, R_SS);
for(i = 0;i < 8; i++) {
gen_op_mov_TN_reg(MO_32, 0, 7 - i);
- gen_op_st_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0);
- gen_op_addl_A0_im(2 << s->dflag);
+ gen_op_st_v(s, s->dflag, cpu_T[0], cpu_A0);
+ gen_op_addl_A0_im(1 << s->dflag);
}
gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
}
@@ -2503,31 +2524,28 @@ static void gen_popa(DisasContext *s)
if (!s->ss32)
tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
- tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag);
+ tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 8 << s->dflag);
if (s->addseg)
gen_op_addl_A0_seg(s, R_SS);
for(i = 0;i < 8; i++) {
/* ESP is not reloaded */
if (i != 3) {
- gen_op_ld_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(MO_16 + s->dflag, 7 - i);
+ gen_op_ld_v(s, s->dflag, cpu_T[0], cpu_A0);
+ gen_op_mov_reg_T0(s->dflag, 7 - i);
}
- gen_op_addl_A0_im(2 << s->dflag);
+ gen_op_addl_A0_im(1 << s->dflag);
}
gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
}
static void gen_enter(DisasContext *s, int esp_addend, int level)
{
- TCGMemOp ot;
- int opsize;
+ TCGMemOp ot = mo_pushpop(s, s->dflag);
+ int opsize = 1 << ot;
level &= 0x1f;
#ifdef TARGET_X86_64
if (CODE64(s)) {
- ot = s->dflag ? MO_64 : MO_16;
- opsize = 1 << ot;
-
gen_op_movl_A0_reg(R_ESP);
gen_op_addq_A0_im(-opsize);
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
@@ -2547,9 +2565,6 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
} else
#endif
{
- ot = s->dflag + MO_16;
- opsize = 2 << s->dflag;
-
gen_op_movl_A0_reg(R_ESP);
gen_op_addl_A0_im(-opsize);
if (!s->ss32)
@@ -2563,7 +2578,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
if (level) {
/* XXX: must save state */
gen_helper_enter_level(cpu_env, tcg_const_i32(level),
- tcg_const_i32(s->dflag),
+ tcg_const_i32(s->dflag - 1),
cpu_T[1]);
}
gen_op_mov_reg_T1(ot, R_EBP);
@@ -3137,7 +3152,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x6e: /* movd mm, ea */
#ifdef TARGET_X86_64
- if (s->dflag == 2) {
+ if (s->dflag == MO_64) {
gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0);
tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
} else
@@ -3152,7 +3167,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x16e: /* movd xmm, ea */
#ifdef TARGET_X86_64
- if (s->dflag == 2) {
+ if (s->dflag == MO_64) {
gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0);
tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
offsetof(CPUX86State,xmm_regs[reg]));
@@ -3317,7 +3332,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x7e: /* movd ea, mm */
#ifdef TARGET_X86_64
- if (s->dflag == 2) {
+ if (s->dflag == MO_64) {
tcg_gen_ld_i64(cpu_T[0], cpu_env,
offsetof(CPUX86State,fpregs[reg].mmx));
gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1);
@@ -3331,7 +3346,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x17e: /* movd ea, xmm */
#ifdef TARGET_X86_64
- if (s->dflag == 2) {
+ if (s->dflag == MO_64) {
tcg_gen_ld_i64(cpu_T[0], cpu_env,
offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1);
@@ -3501,7 +3516,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x22a: /* cvtsi2ss */
case 0x32a: /* cvtsi2sd */
- ot = (s->dflag == 2) ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
@@ -3553,7 +3568,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x32c: /* cvttsd2si */
case 0x22d: /* cvtss2si */
case 0x32d: /* cvtsd2si */
- ot = (s->dflag == 2) ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
if ((b >> 8) & 1) {
@@ -3603,7 +3618,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x1c5:
if (mod != 3)
goto illegal_op;
- ot = (s->dflag == 2) ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
val = cpu_ldub_code(env, s->pc++);
if (b1) {
val &= 7;
@@ -3756,7 +3771,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
}
if ((b & 0xff) == 0xf0) {
ot = MO_8;
- } else if (s->dflag != 2) {
+ } else if (s->dflag != MO_64) {
ot = (s->prefix & PREFIX_DATA ? MO_16 : MO_32);
} else {
ot = MO_64;
@@ -3767,7 +3782,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_helper_crc32(cpu_T[0], cpu_tmp2_i32,
cpu_T[0], tcg_const_i32(8 << ot));
- ot = (s->dflag == 2) ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_op_mov_reg_T0(ot, reg);
break;
@@ -3785,7 +3800,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (!(s->cpuid_ext_features & CPUID_EXT_MOVBE)) {
goto illegal_op;
}
- if (s->dflag != 2) {
+ if (s->dflag != MO_64) {
ot = (s->prefix & PREFIX_DATA ? MO_16 : MO_32);
} else {
ot = MO_64;
@@ -3808,7 +3823,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
tcg_gen_andc_tl(cpu_T[0], cpu_regs[s->vex_v], cpu_T[0]);
gen_op_mov_reg_T0(ot, reg);
@@ -3822,7 +3837,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
{
TCGv bound, zero;
@@ -3862,7 +3877,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
tcg_gen_ext8u_tl(cpu_T[1], cpu_regs[s->vex_v]);
{
@@ -3889,7 +3904,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
switch (ot) {
default:
@@ -3915,11 +3930,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
/* Note that by zero-extending the mask operand, we
automatically handle zero-extending the result. */
- if (s->dflag == 2) {
+ if (ot == MO_64) {
tcg_gen_mov_tl(cpu_T[1], cpu_regs[s->vex_v]);
} else {
tcg_gen_ext32u_tl(cpu_T[1], cpu_regs[s->vex_v]);
@@ -3933,11 +3948,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
/* Note that by zero-extending the mask operand, we
automatically handle zero-extending the result. */
- if (s->dflag == 2) {
+ if (ot == MO_64) {
tcg_gen_mov_tl(cpu_T[1], cpu_regs[s->vex_v]);
} else {
tcg_gen_ext32u_tl(cpu_T[1], cpu_regs[s->vex_v]);
@@ -3953,7 +3968,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
TCGv carry_in, carry_out, zero;
int end_op;
- ot = (s->dflag == 2 ? MO_64 : MO_32);
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
/* Re-use the carry-out from a previous round. */
@@ -4032,7 +4047,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = (s->dflag == 2 ? MO_64 : MO_32);
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
if (ot == MO_64) {
tcg_gen_andi_tl(cpu_T[1], cpu_regs[s->vex_v], 63);
@@ -4064,7 +4079,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
switch (reg & 7) {
@@ -4121,7 +4136,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
goto illegal_op;
if (sse_fn_eppi == SSE_SPECIAL) {
- ot = (s->dflag == 2) ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
rm = (modrm & 7) | REX_B(s);
if (mod != 3)
gen_lea_modrm(env, s, modrm);
@@ -4279,9 +4294,10 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if ((b & 0xfc) == 0x60) { /* pcmpXstrX */
set_cc_op(s, CC_OP_EFLAGS);
- if (s->dflag == 2)
+ if (s->dflag == MO_64) {
/* The helper must use entire 64-bit gp registers */
val |= 1 << 8;
+ }
}
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
@@ -4302,7 +4318,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
b = cpu_ldub_code(env, s->pc++);
if (ot == MO_64) {
@@ -4433,9 +4449,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
target_ulong pc_start)
{
- int b, prefixes, dflag;
+ int b, prefixes;
int shift;
- TCGMemOp ot, aflag;
+ TCGMemOp ot, aflag, dflag;
int modrm, reg, rm, mod, op, opreg, val;
target_ulong next_eip, tval;
int rex_w, rex_r;
@@ -4571,14 +4587,15 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* In 64-bit mode, the default data size is 32-bit. Select 64-bit
data with rex_w, and 16-bit data with 0x66; rex_w takes precedence
over 0x66 if both are present. */
- dflag = (rex_w > 0 ? 2 : prefixes & PREFIX_DATA ? 0 : 1);
+ dflag = (rex_w > 0 ? MO_64 : prefixes & PREFIX_DATA ? MO_16 : MO_32);
/* In 64-bit mode, 0x67 selects 32-bit addressing. */
aflag = (prefixes & PREFIX_ADR ? MO_32 : MO_64);
} else {
/* In 16/32-bit mode, 0x66 selects the opposite data size. */
- dflag = s->code32;
- if (prefixes & PREFIX_DATA) {
- dflag ^= 1;
+ if (s->code32 ^ ((prefixes & PREFIX_DATA) != 0)) {
+ dflag = MO_32;
+ } else {
+ dflag = MO_16;
}
/* In 16/32-bit mode, 0x67 selects the opposite addressing. */
if (s->code32 ^ ((prefixes & PREFIX_ADR) != 0)) {
@@ -4620,10 +4637,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
op = (b >> 3) & 7;
f = (b >> 1) & 3;
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
switch(f) {
case 0: /* OP Ev, Gv */
@@ -4680,10 +4694,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
{
int val;
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
@@ -4720,19 +4731,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/**************************/
/* inc, dec, and other misc arith */
case 0x40 ... 0x47: /* inc Gv */
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag;
gen_inc(s, ot, OR_EAX + (b & 7), 1);
break;
case 0x48 ... 0x4f: /* dec Gv */
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag;
gen_inc(s, ot, OR_EAX + (b & 7), -1);
break;
case 0xf6: /* GRP3 */
case 0xf7:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
@@ -4928,10 +4936,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xfe: /* GRP4 */
case 0xff: /* GRP5 */
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
@@ -4945,10 +4950,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* operand size for jumps is 64 bit */
ot = MO_64;
} else if (op == 3 || op == 5) {
- ot = dflag ? MO_32 + (rex_w == 1) : MO_16;
+ ot = dflag != MO_16 ? MO_32 + (rex_w == 1) : MO_16;
} else if (op == 6) {
/* default push size is 64 bit */
- ot = dflag ? MO_64 : MO_16;
+ ot = mo_pushpop(s, dflag);
}
}
if (mod != 3) {
@@ -4976,7 +4981,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 2: /* call Ev */
/* XXX: optimize if memory (no 'and' is necessary) */
- if (s->dflag == 0) {
+ if (dflag == MO_16) {
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
}
next_eip = s->pc - s->cs_base;
@@ -4995,18 +5000,18 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_jmp_im(pc_start - s->cs_base);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_lcall_protected(cpu_env, cpu_tmp2_i32, cpu_T[1],
- tcg_const_i32(dflag),
+ tcg_const_i32(dflag - 1),
tcg_const_i32(s->pc - pc_start));
} else {
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_lcall_real(cpu_env, cpu_tmp2_i32, cpu_T[1],
- tcg_const_i32(dflag),
+ tcg_const_i32(dflag - 1),
tcg_const_i32(s->pc - s->cs_base));
}
gen_eob(s);
break;
case 4: /* jmp Ev */
- if (s->dflag == 0) {
+ if (dflag == MO_16) {
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
}
gen_op_jmp_T0();
@@ -5040,10 +5045,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x84: /* test Ev, Gv */
case 0x85:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
@@ -5056,10 +5058,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xa8: /* test eAX, Iv */
case 0xa9:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
val = insn_get(env, s, ot);
gen_op_mov_TN_reg(ot, 0, OR_EAX);
@@ -5069,47 +5068,57 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x98: /* CWDE/CBW */
+ switch (dflag) {
#ifdef TARGET_X86_64
- if (dflag == 2) {
+ case MO_64:
gen_op_mov_TN_reg(MO_32, 0, R_EAX);
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_T0(MO_64, R_EAX);
- } else
+ break;
#endif
- if (dflag == 1) {
+ case MO_32:
gen_op_mov_TN_reg(MO_16, 0, R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_T0(MO_32, R_EAX);
- } else {
+ break;
+ case MO_16:
gen_op_mov_TN_reg(MO_8, 0, R_EAX);
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_T0(MO_16, R_EAX);
+ break;
+ default:
+ tcg_abort();
}
break;
case 0x99: /* CDQ/CWD */
+ switch (dflag) {
#ifdef TARGET_X86_64
- if (dflag == 2) {
+ case MO_64:
gen_op_mov_TN_reg(MO_64, 0, R_EAX);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
gen_op_mov_reg_T0(MO_64, R_EDX);
- } else
+ break;
#endif
- if (dflag == 1) {
+ case MO_32:
gen_op_mov_TN_reg(MO_32, 0, R_EAX);
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
gen_op_mov_reg_T0(MO_32, R_EDX);
- } else {
+ break;
+ case MO_16:
gen_op_mov_TN_reg(MO_16, 0, R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
gen_op_mov_reg_T0(MO_16, R_EDX);
+ break;
+ default:
+ tcg_abort();
}
break;
case 0x1af: /* imul Gv, Ev */
case 0x69: /* imul Gv, Ev, I */
case 0x6b:
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
if (b == 0x69)
@@ -5161,10 +5170,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x1c0:
case 0x1c1: /* xadd Ev, Gv */
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -5192,10 +5198,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
int label1, label2;
TCGv t0, t1, t2, a0;
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -5251,7 +5254,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if ((mod == 3) || ((modrm & 0x38) != 0x8))
goto illegal_op;
#ifdef TARGET_X86_64
- if (dflag == 2) {
+ if (dflag == MO_64) {
if (!(s->cpuid_ext_features & CPUID_EXT_CX16))
goto illegal_op;
gen_jmp_im(pc_start - s->cs_base);
@@ -5278,11 +5281,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_push_T0(s);
break;
case 0x58 ... 0x5f: /* pop */
- if (CODE64(s)) {
- ot = dflag ? MO_64 : MO_16;
- } else {
- ot = dflag + MO_16;
- }
+ ot = mo_pushpop(s, dflag);
gen_pop_T0(s);
/* NOTE: order is important for pop %sp */
gen_pop_update(s);
@@ -5300,11 +5299,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x68: /* push Iv */
case 0x6a:
- if (CODE64(s)) {
- ot = dflag ? MO_64 : MO_16;
- } else {
- ot = dflag + MO_16;
- }
+ ot = mo_pushpop(s, dflag);
if (b == 0x68)
val = insn_get(env, s, ot);
else
@@ -5313,11 +5308,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_push_T0(s);
break;
case 0x8f: /* pop Ev */
- if (CODE64(s)) {
- ot = dflag ? MO_64 : MO_16;
- } else {
- ot = dflag + MO_16;
- }
+ ot = mo_pushpop(s, dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
gen_pop_T0(s);
@@ -5356,11 +5347,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_mov_reg_T0(MO_16, R_ESP);
}
gen_pop_T0(s);
- if (CODE64(s)) {
- ot = dflag ? MO_64 : MO_16;
- } else {
- ot = dflag + MO_16;
- }
+ ot = mo_pushpop(s, dflag);
gen_op_mov_reg_T0(ot, R_EBP);
gen_pop_update(s);
break;
@@ -5415,10 +5402,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* mov */
case 0x88:
case 0x89: /* mov Gv, Ev */
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
@@ -5427,10 +5411,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0xc6:
case 0xc7: /* mov Ev, Iv */
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
if (mod != 3) {
@@ -5447,10 +5428,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x8a:
case 0x8b: /* mov Ev, Gv */
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = MO_16 + dflag;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
@@ -5484,10 +5462,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (reg >= 6)
goto illegal_op;
gen_op_movl_T0_seg(reg);
- if (mod == 3)
- ot = MO_16 + dflag;
- else
- ot = MO_16;
+ ot = mod == 3 ? dflag : MO_16;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
break;
@@ -5500,7 +5475,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
TCGMemOp s_ot;
/* d_ot is the size of destination */
- d_ot = dflag + MO_16;
+ d_ot = dflag;
/* ot is the size of source */
ot = (b & 1) + MO_8;
/* s_ot is the sign+size of source */
@@ -5538,7 +5513,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x8d: /* lea */
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
if (mod == 3)
@@ -5560,10 +5535,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
{
target_ulong offset_addr;
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
switch (s->aflag) {
#ifdef TARGET_X86_64
case MO_64:
@@ -5602,7 +5574,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0xb8 ... 0xbf: /* mov R, Iv */
#ifdef TARGET_X86_64
- if (dflag == 2) {
+ if (dflag == MO_64) {
uint64_t tmp;
/* 64 bit case */
tmp = cpu_ldq_code(env, s->pc);
@@ -5613,7 +5585,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else
#endif
{
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag;
val = insn_get(env, s, ot);
reg = (b & 7) | REX_B(s);
tcg_gen_movi_tl(cpu_T[0], val);
@@ -5623,16 +5595,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x91 ... 0x97: /* xchg R, EAX */
do_xchg_reg_eax:
- ot = dflag + MO_16;
+ ot = dflag;
reg = (b & 7) | REX_B(s);
rm = R_EAX;
goto do_xchg_reg;
case 0x86:
case 0x87: /* xchg Ev, Gv */
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -5673,7 +5642,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x1b5: /* lgs Gv */
op = R_GS;
do_lxx:
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag != MO_16 ? MO_32 : MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -5701,11 +5670,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
shift = 2;
grp2:
{
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
-
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
op = (modrm >> 3) & 7;
@@ -5758,7 +5723,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
op = 1;
shift = 0;
do_shiftd:
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
@@ -5922,7 +5887,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x0c: /* fldenv mem */
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
+ gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(dflag - 1));
break;
case 0x0d: /* fldcw mem */
tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
@@ -5932,7 +5897,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x0e: /* fnstenv mem */
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_fstenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
+ gen_helper_fstenv(cpu_env, cpu_A0, tcg_const_i32(dflag - 1));
break;
case 0x0f: /* fnstcw mem */
gen_helper_fnstcw(cpu_tmp2_i32, cpu_env);
@@ -5953,12 +5918,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x2c: /* frstor mem */
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_frstor(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
+ gen_helper_frstor(cpu_env, cpu_A0, tcg_const_i32(dflag - 1));
break;
case 0x2e: /* fnsave mem */
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_fsave(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
+ gen_helper_fsave(cpu_env, cpu_A0, tcg_const_i32(dflag - 1));
break;
case 0x2f: /* fnstsw mem */
gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
@@ -6305,11 +6270,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xa4: /* movsS */
case 0xa5:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
-
+ ot = mo_b_d(b, dflag);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
} else {
@@ -6319,11 +6280,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xaa: /* stosS */
case 0xab:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
-
+ ot = mo_b_d(b, dflag);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
} else {
@@ -6332,10 +6289,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0xac: /* lodsS */
case 0xad:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
} else {
@@ -6344,10 +6298,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0xae: /* scasS */
case 0xaf:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
if (prefixes & PREFIX_REPNZ) {
gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
} else if (prefixes & PREFIX_REPZ) {
@@ -6359,10 +6310,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xa6: /* cmpsS */
case 0xa7:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
if (prefixes & PREFIX_REPNZ) {
gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
} else if (prefixes & PREFIX_REPZ) {
@@ -6373,10 +6321,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x6c: /* insS */
case 0x6d:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag ? MO_32 : MO_16;
+ ot = mo_b_d32(b, dflag);
tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
@@ -6391,10 +6336,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x6e: /* outsS */
case 0x6f:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag ? MO_32 : MO_16;
+ ot = mo_b_d32(b, dflag);
tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes) | 4);
@@ -6413,10 +6355,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xe4:
case 0xe5:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag ? MO_32 : MO_16;
+ ot = mo_b_d32(b, dflag);
val = cpu_ldub_code(env, s->pc++);
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
@@ -6432,10 +6371,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0xe6:
case 0xe7:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag ? MO_32 : MO_16;
+ ot = mo_b_d32(b, dflag);
val = cpu_ldub_code(env, s->pc++);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes));
@@ -6453,10 +6389,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0xec:
case 0xed:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag ? MO_32 : MO_16;
+ ot = mo_b_d32(b, dflag);
tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
@@ -6472,10 +6405,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0xee:
case 0xef:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag ? MO_32 : MO_16;
+ ot = mo_b_d32(b, dflag);
tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes));
@@ -6498,10 +6428,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
val = cpu_ldsw_code(env, s->pc);
s->pc += 2;
gen_pop_T0(s);
- if (CODE64(s) && s->dflag)
- s->dflag = 2;
- gen_stack_update(s, val + (2 << s->dflag));
- if (s->dflag == 0) {
+ if (CODE64(s) && dflag != MO_16) {
+ dflag = MO_64;
+ }
+ gen_stack_update(s, val + (1 << dflag));
+ if (dflag == MO_16) {
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
}
gen_op_jmp_T0();
@@ -6510,7 +6441,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xc3: /* ret */
gen_pop_T0(s);
gen_pop_update(s);
- if (s->dflag == 0) {
+ if (dflag == MO_16) {
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
}
gen_op_jmp_T0();
@@ -6523,21 +6454,21 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (s->pe && !s->vm86) {
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_lret_protected(cpu_env, tcg_const_i32(s->dflag),
+ gen_helper_lret_protected(cpu_env, tcg_const_i32(dflag - 1),
tcg_const_i32(val));
} else {
gen_stack_A0(s);
/* pop offset */
- gen_op_ld_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, dflag, cpu_T[0], cpu_A0);
/* NOTE: keeping EIP updated is not a problem in case of
exception */
gen_op_jmp_T0();
/* pop selector */
- gen_op_addl_A0_im(2 << s->dflag);
- gen_op_ld_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0);
+ gen_op_addl_A0_im(1 << dflag);
+ gen_op_ld_v(s, dflag, cpu_T[0], cpu_A0);
gen_op_movl_seg_T0_vm(R_CS);
/* add stack offset */
- gen_stack_update(s, val + (4 << s->dflag));
+ gen_stack_update(s, val + (2 << dflag));
}
gen_eob(s);
break;
@@ -6548,19 +6479,19 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET);
if (!s->pe) {
/* real mode */
- gen_helper_iret_real(cpu_env, tcg_const_i32(s->dflag));
+ gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1));
set_cc_op(s, CC_OP_EFLAGS);
} else if (s->vm86) {
if (s->iopl != 3) {
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
- gen_helper_iret_real(cpu_env, tcg_const_i32(s->dflag));
+ gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1));
set_cc_op(s, CC_OP_EFLAGS);
}
} else {
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_iret_protected(cpu_env, tcg_const_i32(s->dflag),
+ gen_helper_iret_protected(cpu_env, tcg_const_i32(dflag - 1),
tcg_const_i32(s->pc - s->cs_base));
set_cc_op(s, CC_OP_EFLAGS);
}
@@ -6568,16 +6499,18 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0xe8: /* call im */
{
- if (dflag)
+ if (dflag != MO_16) {
tval = (int32_t)insn_get(env, s, MO_32);
- else
+ } else {
tval = (int16_t)insn_get(env, s, MO_16);
+ }
next_eip = s->pc - s->cs_base;
tval += next_eip;
- if (s->dflag == 0)
+ if (dflag == MO_16) {
tval &= 0xffff;
- else if(!CODE64(s))
+ } else if (!CODE64(s)) {
tval &= 0xffffffff;
+ }
tcg_gen_movi_tl(cpu_T[0], next_eip);
gen_push_T0(s);
gen_jmp(s, tval);
@@ -6589,7 +6522,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (CODE64(s))
goto illegal_op;
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag;
offset = insn_get(env, s, ot);
selector = insn_get(env, s, MO_16);
@@ -6598,15 +6531,17 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
goto do_lcall;
case 0xe9: /* jmp im */
- if (dflag)
+ if (dflag != MO_16) {
tval = (int32_t)insn_get(env, s, MO_32);
- else
+ } else {
tval = (int16_t)insn_get(env, s, MO_16);
+ }
tval += s->pc - s->cs_base;
- if (s->dflag == 0)
+ if (dflag == MO_16) {
tval &= 0xffff;
- else if(!CODE64(s))
+ } else if (!CODE64(s)) {
tval &= 0xffffffff;
+ }
gen_jmp(s, tval);
break;
case 0xea: /* ljmp im */
@@ -6615,7 +6550,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (CODE64(s))
goto illegal_op;
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag;
offset = insn_get(env, s, ot);
selector = insn_get(env, s, MO_16);
@@ -6626,15 +6561,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xeb: /* jmp Jb */
tval = (int8_t)insn_get(env, s, MO_8);
tval += s->pc - s->cs_base;
- if (s->dflag == 0)
+ if (dflag == MO_16) {
tval &= 0xffff;
+ }
gen_jmp(s, tval);
break;
case 0x70 ... 0x7f: /* jcc Jb */
tval = (int8_t)insn_get(env, s, MO_8);
goto do_jcc;
case 0x180 ... 0x18f: /* jcc Jv */
- if (dflag) {
+ if (dflag != MO_16) {
tval = (int32_t)insn_get(env, s, MO_32);
} else {
tval = (int16_t)insn_get(env, s, MO_16);
@@ -6642,8 +6578,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
do_jcc:
next_eip = s->pc - s->cs_base;
tval += next_eip;
- if (s->dflag == 0)
+ if (dflag == MO_16) {
tval &= 0xffff;
+ }
gen_jcc(s, b, tval, next_eip);
break;
@@ -6656,7 +6593,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (!(s->cpuid_features & CPUID_CMOV)) {
goto illegal_op;
}
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
gen_cmovcc1(env, s, ot, b, modrm, reg);
@@ -6681,7 +6618,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_pop_T0(s);
if (s->cpl == 0) {
- if (s->dflag) {
+ if (dflag != MO_16) {
gen_helper_write_eflags(cpu_env, cpu_T[0],
tcg_const_i32((TF_MASK | AC_MASK |
ID_MASK | NT_MASK |
@@ -6696,7 +6633,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
} else {
if (s->cpl <= s->iopl) {
- if (s->dflag) {
+ if (dflag != MO_16) {
gen_helper_write_eflags(cpu_env, cpu_T[0],
tcg_const_i32((TF_MASK |
AC_MASK |
@@ -6713,7 +6650,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
& 0xffff));
}
} else {
- if (s->dflag) {
+ if (dflag != MO_16) {
gen_helper_write_eflags(cpu_env, cpu_T[0],
tcg_const_i32((TF_MASK | AC_MASK |
ID_MASK | NT_MASK)));
@@ -6773,7 +6710,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/************************/
/* bit operations */
case 0x1ba: /* bt/bts/btr/btc Gv, im */
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
op = (modrm >> 3) & 7;
mod = (modrm >> 6) & 3;
@@ -6804,7 +6741,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x1bb: /* btc */
op = 3;
do_btx:
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -6862,7 +6799,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x1bc: /* bsf / tzcnt */
case 0x1bd: /* bsr / lzcnt */
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
@@ -7061,7 +6998,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x62: /* bound */
if (CODE64(s))
goto illegal_op;
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
reg = (modrm >> 3) & 7;
mod = (modrm >> 6) & 3;
@@ -7080,7 +7017,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x1c8 ... 0x1cf: /* bswap reg */
reg = (b & 7) | REX_B(s);
#ifdef TARGET_X86_64
- if (dflag == 2) {
+ if (dflag == MO_64) {
gen_op_mov_TN_reg(MO_64, 0, reg);
tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_T0(MO_64, reg);
@@ -7110,8 +7047,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tval = (int8_t)insn_get(env, s, MO_8);
next_eip = s->pc - s->cs_base;
tval += next_eip;
- if (s->dflag == 0)
+ if (dflag == MO_16) {
tval &= 0xffff;
+ }
l1 = gen_new_label();
l2 = gen_new_label();
@@ -7196,7 +7134,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_sysexit(cpu_env, tcg_const_i32(dflag));
+ gen_helper_sysexit(cpu_env, tcg_const_i32(dflag - 1));
gen_eob(s);
}
break;
@@ -7214,7 +7152,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_sysret(cpu_env, tcg_const_i32(s->dflag));
+ gen_helper_sysret(cpu_env, tcg_const_i32(dflag - 1));
/* condition codes are modified only in long mode */
if (s->lma) {
set_cc_op(s, CC_OP_EFLAGS);
@@ -7248,9 +7186,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector));
- ot = MO_16;
- if (mod == 3)
- ot += s->dflag;
+ ot = mod == 3 ? dflag : MO_16;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
break;
case 2: /* lldt */
@@ -7271,9 +7207,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector));
- ot = MO_16;
- if (mod == 3)
- ot += s->dflag;
+ ot = mod == 3 ? dflag : MO_16;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
break;
case 3: /* ltr */
@@ -7321,7 +7255,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
- if (s->dflag == 0) {
+ if (dflag == MO_16) {
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff);
}
gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
@@ -7377,7 +7311,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
- if (s->dflag == 0) {
+ if (dflag == MO_16) {
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff);
}
gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
@@ -7479,7 +7413,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_ld_v(s, MO_16, cpu_T[1], cpu_A0);
gen_add_A0_im(s, 2);
gen_op_ld_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
- if (s->dflag == 0) {
+ if (dflag == MO_16) {
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff);
}
if (op == 2) {
@@ -7582,7 +7516,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (CODE64(s)) {
int d_ot;
/* d_ot is the size of destination */
- d_ot = dflag + MO_16;
+ d_ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
@@ -7657,7 +7591,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
TCGv t0;
if (!s->pe || s->vm86)
goto illegal_op;
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag != MO_16 ? MO_32 : MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
@@ -7793,7 +7727,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x1c3: /* MOVNTI reg, mem */
if (!(s->cpuid_features & CPUID_SSE2))
goto illegal_op;
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
if (mod == 3)
@@ -7818,7 +7752,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_lea_modrm(env, s, modrm);
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_fxsave(cpu_env, cpu_A0, tcg_const_i32((s->dflag == 2)));
+ gen_helper_fxsave(cpu_env, cpu_A0, tcg_const_i32(dflag == MO_64));
break;
case 1: /* fxrstor */
if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
@@ -7831,8 +7765,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_lea_modrm(env, s, modrm);
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_fxrstor(cpu_env, cpu_A0,
- tcg_const_i32((s->dflag == 2)));
+ gen_helper_fxrstor(cpu_env, cpu_A0, tcg_const_i32(dflag == MO_64));
break;
case 2: /* ldmxcsr */
case 3: /* stmxcsr */
@@ -7902,12 +7835,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
- if (s->prefix & PREFIX_DATA)
+ if (s->prefix & PREFIX_DATA) {
ot = MO_16;
- else if (s->dflag != 2)
- ot = MO_32;
- else
- ot = MO_64;
+ } else {
+ ot = mo_64_32(dflag);
+ }
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
gen_helper_popcnt(cpu_T[0], cpu_env, cpu_T[0], tcg_const_i32(ot));
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 38/49] target-i386: Tidy addr16 code in gen_lea_modrm
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (36 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 37/49] target-i386: Change dflag " Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 39/49] target-i386: Combine gen_push_T* into gen_push_v Richard Henderson
` (10 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Unlike the addr32, there was no bug. But we can use the same
technique to reduce the number of TCG ops.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 34 ++++++++++++++++------------------
1 file changed, 16 insertions(+), 18 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 9f38adf..8673f95 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -2028,51 +2028,49 @@ static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm)
break;
default:
case 2:
- disp = cpu_lduw_code(env, s->pc);
+ disp = (int16_t)cpu_lduw_code(env, s->pc);
s->pc += 2;
break;
}
- switch(rm) {
+
+ sum = cpu_A0;
+ switch (rm) {
case 0:
- gen_op_movl_A0_reg(R_EBX);
- gen_op_addl_A0_reg_sN(0, R_ESI);
+ tcg_gen_add_tl(cpu_A0, cpu_regs[R_EBX], cpu_regs[R_ESI]);
break;
case 1:
- gen_op_movl_A0_reg(R_EBX);
- gen_op_addl_A0_reg_sN(0, R_EDI);
+ tcg_gen_add_tl(cpu_A0, cpu_regs[R_EBX], cpu_regs[R_EDI]);
break;
case 2:
- gen_op_movl_A0_reg(R_EBP);
- gen_op_addl_A0_reg_sN(0, R_ESI);
+ tcg_gen_add_tl(cpu_A0, cpu_regs[R_EBP], cpu_regs[R_ESI]);
break;
case 3:
- gen_op_movl_A0_reg(R_EBP);
- gen_op_addl_A0_reg_sN(0, R_EDI);
+ tcg_gen_add_tl(cpu_A0, cpu_regs[R_EBP], cpu_regs[R_EDI]);
break;
case 4:
- gen_op_movl_A0_reg(R_ESI);
+ sum = cpu_regs[R_ESI];
break;
case 5:
- gen_op_movl_A0_reg(R_EDI);
+ sum = cpu_regs[R_EDI];
break;
case 6:
- gen_op_movl_A0_reg(R_EBP);
+ sum = cpu_regs[R_EBP];
break;
default:
case 7:
- gen_op_movl_A0_reg(R_EBX);
+ sum = cpu_regs[R_EBX];
break;
}
- if (disp != 0)
- gen_op_addl_A0_im(disp);
+ tcg_gen_addi_tl(cpu_A0, sum, disp);
tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
no_rm:
if (must_add_seg) {
if (override < 0) {
- if (rm == 2 || rm == 3 || rm == 6)
+ if (rm == 2 || rm == 3 || rm == 6) {
override = R_SS;
- else
+ } else {
override = R_DS;
+ }
}
gen_op_addl_A0_seg(s, override);
}
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 39/49] target-i386: Combine gen_push_T* into gen_push_v
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (37 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 38/49] target-i386: Tidy addr16 code in gen_lea_modrm Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 40/49] target_i386: Clean up gen_pop_T0 Richard Henderson
` (9 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Reduce ifdefs, share more code between paths, reduce the number of TCG
ops generated.
Add forgotten zero-extension in the TARGET_X86_64, !CODE64, ss32 case.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 106 +++++++++++++++---------------------------------
1 file changed, 32 insertions(+), 74 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 8673f95..589c90c 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -2384,78 +2384,36 @@ static inline void gen_stack_update(DisasContext *s, int addend)
}
}
-/* generate a push. It depends on ss32, addseg and dflag */
-static void gen_push_T0(DisasContext *s)
+/* Generate a push. It depends on ss32, addseg and dflag. */
+static void gen_push_v(DisasContext *s, TCGv val)
{
-#ifdef TARGET_X86_64
- if (CODE64(s)) {
- gen_op_movq_A0_reg(R_ESP);
- if (s->dflag != MO_16) {
- gen_op_addq_A0_im(-8);
- gen_op_st_v(s, MO_64, cpu_T[0], cpu_A0);
- } else {
- gen_op_addq_A0_im(-2);
- gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
- }
- gen_op_mov_reg_A0(MO_64, R_ESP);
- } else
-#endif
- {
- gen_op_movl_A0_reg(R_ESP);
- gen_op_addl_A0_im(-1 << s->dflag);
- if (s->ss32) {
- if (s->addseg) {
- tcg_gen_mov_tl(cpu_T[1], cpu_A0);
- gen_op_addl_A0_seg(s, R_SS);
- }
- } else {
- tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
- tcg_gen_mov_tl(cpu_T[1], cpu_A0);
- gen_op_addl_A0_seg(s, R_SS);
- }
- gen_op_st_v(s, s->dflag, cpu_T[0], cpu_A0);
- if (s->ss32 && !s->addseg)
- gen_op_mov_reg_A0(MO_32, R_ESP);
- else
- gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
- }
-}
+ TCGMemOp a_ot, d_ot = mo_pushpop(s, s->dflag);
+ int size = 1 << d_ot;
+ TCGv new_esp = cpu_A0;
+
+ tcg_gen_subi_tl(cpu_A0, cpu_regs[R_ESP], size);
-/* generate a push. It depends on ss32, addseg and dflag */
-/* slower version for T1, only used for call Ev */
-static void gen_push_T1(DisasContext *s)
-{
-#ifdef TARGET_X86_64
if (CODE64(s)) {
- gen_op_movq_A0_reg(R_ESP);
- if (s->dflag != MO_16) {
- gen_op_addq_A0_im(-8);
- gen_op_st_v(s, MO_64, cpu_T[1], cpu_A0);
- } else {
- gen_op_addq_A0_im(-2);
- gen_op_st_v(s, MO_16, cpu_T[1], cpu_A0);
- }
- gen_op_mov_reg_A0(MO_64, R_ESP);
- } else
-#endif
- {
- gen_op_movl_A0_reg(R_ESP);
- gen_op_addl_A0_im(-1 << s->dflag);
- if (s->ss32) {
- if (s->addseg) {
- gen_op_addl_A0_seg(s, R_SS);
- }
- } else {
- tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
+ a_ot = MO_64;
+ } else if (s->ss32) {
+ a_ot = MO_32;
+ if (s->addseg) {
+ new_esp = cpu_tmp4;
+ tcg_gen_mov_tl(new_esp, cpu_A0);
gen_op_addl_A0_seg(s, R_SS);
+ } else {
+ tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
}
- gen_op_st_v(s, s->dflag, cpu_T[1], cpu_A0);
-
- if (s->ss32 && !s->addseg)
- gen_op_mov_reg_A0(MO_32, R_ESP);
- else
- gen_stack_update(s, -1 << s->dflag);
+ } else {
+ a_ot = MO_16;
+ new_esp = cpu_tmp4;
+ tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
+ tcg_gen_mov_tl(new_esp, cpu_A0);
+ gen_op_addl_A0_seg(s, R_SS);
}
+
+ gen_op_st_v(s, d_ot, val, cpu_A0);
+ gen_op_mov_reg_v(a_ot, R_ESP, new_esp);
}
/* two step pop is necessary for precise exceptions */
@@ -4984,7 +4942,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
next_eip = s->pc - s->cs_base;
tcg_gen_movi_tl(cpu_T[1], next_eip);
- gen_push_T1(s);
+ gen_push_v(s, cpu_T[1]);
gen_op_jmp_T0();
gen_eob(s);
break;
@@ -5034,7 +4992,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_eob(s);
break;
case 6: /* push Ev */
- gen_push_T0(s);
+ gen_push_v(s, cpu_T[0]);
break;
default:
goto illegal_op;
@@ -5276,7 +5234,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* push/pop */
case 0x50 ... 0x57: /* push */
gen_op_mov_TN_reg(MO_32, 0, (b & 7) | REX_B(s));
- gen_push_T0(s);
+ gen_push_v(s, cpu_T[0]);
break;
case 0x58 ... 0x5f: /* pop */
ot = mo_pushpop(s, dflag);
@@ -5303,7 +5261,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
else
val = (int8_t)insn_get(env, s, MO_8);
tcg_gen_movi_tl(cpu_T[0], val);
- gen_push_T0(s);
+ gen_push_v(s, cpu_T[0]);
break;
case 0x8f: /* pop Ev */
ot = mo_pushpop(s, dflag);
@@ -5356,12 +5314,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (CODE64(s))
goto illegal_op;
gen_op_movl_T0_seg(b >> 3);
- gen_push_T0(s);
+ gen_push_v(s, cpu_T[0]);
break;
case 0x1a0: /* push fs */
case 0x1a8: /* push gs */
gen_op_movl_T0_seg((b >> 3) & 7);
- gen_push_T0(s);
+ gen_push_v(s, cpu_T[0]);
break;
case 0x07: /* pop es */
case 0x17: /* pop ss */
@@ -6510,7 +6468,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tval &= 0xffffffff;
}
tcg_gen_movi_tl(cpu_T[0], next_eip);
- gen_push_T0(s);
+ gen_push_v(s, cpu_T[0]);
gen_jmp(s, tval);
}
break;
@@ -6606,7 +6564,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_update_cc_op(s);
gen_helper_read_eflags(cpu_T[0], cpu_env);
- gen_push_T0(s);
+ gen_push_v(s, cpu_T[0]);
}
break;
case 0x9d: /* popf */
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 40/49] target_i386: Clean up gen_pop_T0
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (38 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 39/49] target-i386: Combine gen_push_T* into gen_push_v Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 41/49] target-i386: Tidy cpu_regs initialization Richard Henderson
` (8 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Reduce ifdefs, share more code between paths, reduce the number of TCG
ops generated. Avoid re-computing the size of the operation across
gen_pop_T0 and gen_pop_update.
Add forgotten zero-extension in the TARGET_X86_64, !CODE64, ss32 case.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 84 ++++++++++++++++++++++---------------------------
1 file changed, 37 insertions(+), 47 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 589c90c..9baeffa 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -2417,30 +2417,30 @@ static void gen_push_v(DisasContext *s, TCGv val)
}
/* two step pop is necessary for precise exceptions */
-static void gen_pop_T0(DisasContext *s)
+static TCGMemOp gen_pop_T0(DisasContext *s)
{
-#ifdef TARGET_X86_64
+ TCGMemOp d_ot = mo_pushpop(s, s->dflag);
+ TCGv addr = cpu_A0;
+
if (CODE64(s)) {
- gen_op_movq_A0_reg(R_ESP);
- gen_op_ld_v(s, mo_pushpop(s, s->dflag), cpu_T[0], cpu_A0);
- } else
-#endif
- {
- gen_op_movl_A0_reg(R_ESP);
- if (s->ss32) {
- if (s->addseg)
- gen_op_addl_A0_seg(s, R_SS);
- } else {
- tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
- gen_op_addl_A0_seg(s, R_SS);
- }
- gen_op_ld_v(s, s->dflag, cpu_T[0], cpu_A0);
+ addr = cpu_regs[R_ESP];
+ } else if (!s->ss32) {
+ tcg_gen_ext16u_tl(cpu_A0, cpu_regs[R_ESP]);
+ gen_op_addl_A0_seg(s, R_SS);
+ } else if (s->addseg) {
+ tcg_gen_mov_tl(cpu_A0, cpu_regs[R_ESP]);
+ gen_op_addl_A0_seg(s, R_SS);
+ } else {
+ tcg_gen_ext32u_tl(cpu_A0, cpu_regs[R_ESP]);
}
+
+ gen_op_ld_v(s, d_ot, cpu_T[0], addr);
+ return d_ot;
}
-static void gen_pop_update(DisasContext *s)
+static void gen_pop_update(DisasContext *s, TCGMemOp ot)
{
- gen_stack_update(s, 1 << mo_pushpop(s, s->dflag));
+ gen_stack_update(s, 1 << ot);
}
static void gen_stack_A0(DisasContext *s)
@@ -5237,10 +5237,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_push_v(s, cpu_T[0]);
break;
case 0x58 ... 0x5f: /* pop */
- ot = mo_pushpop(s, dflag);
- gen_pop_T0(s);
+ ot = gen_pop_T0(s);
/* NOTE: order is important for pop %sp */
- gen_pop_update(s);
+ gen_pop_update(s, ot);
gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s));
break;
case 0x60: /* pusha */
@@ -5264,13 +5263,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_push_v(s, cpu_T[0]);
break;
case 0x8f: /* pop Ev */
- ot = mo_pushpop(s, dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
- gen_pop_T0(s);
+ ot = gen_pop_T0(s);
if (mod == 3) {
/* NOTE: order is important for pop %sp */
- gen_pop_update(s);
+ gen_pop_update(s, ot);
rm = (modrm & 7) | REX_B(s);
gen_op_mov_reg_T0(ot, rm);
} else {
@@ -5278,7 +5276,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
s->popl_esp_hack = 1 << ot;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
s->popl_esp_hack = 0;
- gen_pop_update(s);
+ gen_pop_update(s, ot);
}
break;
case 0xc8: /* enter */
@@ -5302,10 +5300,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_mov_TN_reg(MO_16, 0, R_EBP);
gen_op_mov_reg_T0(MO_16, R_ESP);
}
- gen_pop_T0(s);
- ot = mo_pushpop(s, dflag);
+ ot = gen_pop_T0(s);
gen_op_mov_reg_T0(ot, R_EBP);
- gen_pop_update(s);
+ gen_pop_update(s, ot);
break;
case 0x06: /* push es */
case 0x0e: /* push cs */
@@ -5327,9 +5324,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (CODE64(s))
goto illegal_op;
reg = b >> 3;
- gen_pop_T0(s);
+ ot = gen_pop_T0(s);
gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
- gen_pop_update(s);
+ gen_pop_update(s, ot);
if (reg == R_SS) {
/* if reg == SS, inhibit interrupts/trace. */
/* If several instructions disable interrupts, only the
@@ -5345,9 +5342,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x1a1: /* pop fs */
case 0x1a9: /* pop gs */
- gen_pop_T0(s);
+ ot = gen_pop_T0(s);
gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
- gen_pop_update(s);
+ gen_pop_update(s, ot);
if (s->is_jmp) {
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
@@ -6383,23 +6380,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xc2: /* ret im */
val = cpu_ldsw_code(env, s->pc);
s->pc += 2;
- gen_pop_T0(s);
- if (CODE64(s) && dflag != MO_16) {
- dflag = MO_64;
- }
- gen_stack_update(s, val + (1 << dflag));
- if (dflag == MO_16) {
- tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
- }
+ ot = gen_pop_T0(s);
+ gen_stack_update(s, val + (1 << ot));
+ /* Note that gen_pop_T0 uses a zero-extending load. */
gen_op_jmp_T0();
gen_eob(s);
break;
case 0xc3: /* ret */
- gen_pop_T0(s);
- gen_pop_update(s);
- if (dflag == MO_16) {
- tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
- }
+ ot = gen_pop_T0(s);
+ gen_pop_update(s, ot);
+ /* Note that gen_pop_T0 uses a zero-extending load. */
gen_op_jmp_T0();
gen_eob(s);
break;
@@ -6572,7 +6562,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (s->vm86 && s->iopl != 3) {
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
- gen_pop_T0(s);
+ ot = gen_pop_T0(s);
if (s->cpl == 0) {
if (dflag != MO_16) {
gen_helper_write_eflags(cpu_env, cpu_T[0],
@@ -6618,7 +6608,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
}
}
- gen_pop_update(s);
+ gen_pop_update(s, ot);
set_cc_op(s, CC_OP_EFLAGS);
/* abort translation because TF/AC flag may change */
gen_jmp_im(s->pc - s->cs_base);
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 41/49] target-i386: Tidy cpu_regs initialization
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (39 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 40/49] target_i386: Clean up gen_pop_T0 Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 42/49] target-i386: Remove gen_op_mov_reg_T0 Richard Henderson
` (7 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 87 ++++++++++++++++++++-----------------------------
1 file changed, 36 insertions(+), 51 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 9baeffa..5a594b9 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -7823,6 +7823,37 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
void optimize_flags_init(void)
{
+ static const char reg_names[CPU_NB_REGS][4] = {
+#ifdef TARGET_X86_64
+ [R_EAX] = "rax",
+ [R_EBX] = "rbx",
+ [R_ECX] = "rcx",
+ [R_EDX] = "rdx",
+ [R_ESI] = "rsi",
+ [R_EDI] = "rdi",
+ [R_EBP] = "rbp",
+ [R_ESP] = "rsp",
+ [8] = "r8",
+ [9] = "r9",
+ [10] = "r10",
+ [11] = "r11",
+ [12] = "r12",
+ [13] = "r13",
+ [14] = "r14",
+ [15] = "r15",
+#else
+ [R_EAX] = "eax",
+ [R_EBX] = "ebx",
+ [R_ECX] = "ecx",
+ [R_EDX] = "edx",
+ [R_ESI] = "esi",
+ [R_EDI] = "edi",
+ [R_EBP] = "ebp",
+ [R_ESP] = "esp",
+#endif
+ };
+ int i;
+
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUX86State, cc_op), "cc_op");
@@ -7833,57 +7864,11 @@ void optimize_flags_init(void)
cpu_cc_src2 = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_src2),
"cc_src2");
-#ifdef TARGET_X86_64
- cpu_regs[R_EAX] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EAX]), "rax");
- cpu_regs[R_ECX] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[R_ECX]), "rcx");
- cpu_regs[R_EDX] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EDX]), "rdx");
- cpu_regs[R_EBX] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EBX]), "rbx");
- cpu_regs[R_ESP] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[R_ESP]), "rsp");
- cpu_regs[R_EBP] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EBP]), "rbp");
- cpu_regs[R_ESI] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[R_ESI]), "rsi");
- cpu_regs[R_EDI] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EDI]), "rdi");
- cpu_regs[8] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[8]), "r8");
- cpu_regs[9] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[9]), "r9");
- cpu_regs[10] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[10]), "r10");
- cpu_regs[11] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[11]), "r11");
- cpu_regs[12] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[12]), "r12");
- cpu_regs[13] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[13]), "r13");
- cpu_regs[14] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[14]), "r14");
- cpu_regs[15] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[15]), "r15");
-#else
- cpu_regs[R_EAX] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EAX]), "eax");
- cpu_regs[R_ECX] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUX86State, regs[R_ECX]), "ecx");
- cpu_regs[R_EDX] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EDX]), "edx");
- cpu_regs[R_EBX] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EBX]), "ebx");
- cpu_regs[R_ESP] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUX86State, regs[R_ESP]), "esp");
- cpu_regs[R_EBP] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EBP]), "ebp");
- cpu_regs[R_ESI] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUX86State, regs[R_ESI]), "esi");
- cpu_regs[R_EDI] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EDI]), "edi");
-#endif
+ for (i = 0; i < CPU_NB_REGS; ++i) {
+ cpu_regs[i] = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUX86State, regs[i]),
+ reg_names[i]);
+ }
}
/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 42/49] target-i386: Remove gen_op_mov_reg_T0
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (40 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 41/49] target-i386: Tidy cpu_regs initialization Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 43/49] target-i386: Remove gen_op_mov_reg_T1 Richard Henderson
` (6 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Replace with its definition.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 135 +++++++++++++++++++++++-------------------------
1 file changed, 65 insertions(+), 70 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 5a594b9..8553b71 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -358,11 +358,6 @@ static void gen_op_mov_reg_v(TCGMemOp ot, int reg, TCGv t0)
}
}
-static inline void gen_op_mov_reg_T0(TCGMemOp ot, int reg)
-{
- gen_op_mov_reg_v(ot, reg, cpu_T[0]);
-}
-
static inline void gen_op_mov_reg_T1(TCGMemOp ot, int reg)
{
gen_op_mov_reg_v(ot, reg, cpu_T[1]);
@@ -513,7 +508,7 @@ static inline void gen_op_st_rm_T0_A0(DisasContext *s, int idx, int d)
if (d == OR_TMP0) {
gen_op_st_v(s, idx, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_reg_T0(idx, d);
+ gen_op_mov_reg_v(idx, d, cpu_T[0]);
}
}
@@ -1162,7 +1157,7 @@ static inline void gen_lods(DisasContext *s, TCGMemOp ot)
{
gen_string_movl_A0_ESI(s);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(ot, R_EAX);
+ gen_op_mov_reg_v(ot, R_EAX, cpu_T[0]);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_ESI);
}
@@ -2173,11 +2168,11 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
if (is_store) {
if (reg != OR_TMP0)
gen_op_mov_TN_reg(ot, 0, reg);
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
gen_op_mov_TN_reg(ot, 0, rm);
if (reg != OR_TMP0)
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
}
} else {
gen_lea_modrm(env, s, modrm);
@@ -2188,7 +2183,7 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
} else {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
if (reg != OR_TMP0)
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
}
}
}
@@ -2297,7 +2292,7 @@ static void gen_cmovcc1(CPUX86State *env, DisasContext *s, TCGMemOp ot, int b,
tcg_gen_movcond_tl(cc.cond, cpu_T[0], cc.reg, cc.reg2,
cpu_T[0], cpu_regs[reg]);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
if (cc.mask != -1) {
tcg_temp_free(cc.reg);
@@ -2487,7 +2482,7 @@ static void gen_popa(DisasContext *s)
/* ESP is not reloaded */
if (i != 3) {
gen_op_ld_v(s, s->dflag, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(s->dflag, 7 - i);
+ gen_op_mov_reg_v(s->dflag, 7 - i, cpu_T[0]);
}
gen_op_addl_A0_im(1 << s->dflag);
}
@@ -3553,7 +3548,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
goto illegal_op;
#endif
}
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
case 0xc4: /* pinsrw */
case 0x1c4:
@@ -3588,7 +3583,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val)));
}
reg = ((modrm >> 3) & 7) | rex_r;
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
case 0x1d6: /* movq ea, xmm */
if (mod != 3) {
@@ -3739,7 +3734,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
cpu_T[0], tcg_const_i32(8 << ot));
ot = mo_64_32(s->dflag);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
case 0x1f0: /* crc32 or movbe */
@@ -3766,7 +3761,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if ((b & 1) == 0) {
tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0,
s->mem_index, ot | MO_BE);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
} else {
tcg_gen_qemu_st_tl(cpu_regs[reg], cpu_A0,
s->mem_index, ot | MO_BE);
@@ -3782,7 +3777,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
tcg_gen_andc_tl(cpu_T[0], cpu_regs[s->vex_v], cpu_T[0]);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
gen_op_update1_cc();
set_cc_op(s, CC_OP_LOGICB + ot);
break;
@@ -3821,7 +3816,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_subi_tl(cpu_T[1], cpu_T[1], 1);
tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
gen_op_update1_cc();
set_cc_op(s, CC_OP_LOGICB + ot);
}
@@ -3849,7 +3844,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_movi_tl(cpu_A0, -1);
tcg_gen_shl_tl(cpu_A0, cpu_A0, cpu_T[1]);
tcg_gen_andc_tl(cpu_T[0], cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
gen_op_update1_cc();
set_cc_op(s, CC_OP_BMILGB + ot);
break;
@@ -4023,7 +4018,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
}
tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
}
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
case 0x0f3:
@@ -4042,7 +4037,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 1: /* blsr By,Ey */
tcg_gen_neg_tl(cpu_T[1], cpu_T[0]);
tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(ot, s->vex_v);
+ gen_op_mov_reg_v(ot, s->vex_v, cpu_T[0]);
gen_op_update2_cc();
set_cc_op(s, CC_OP_BMILGB + ot);
break;
@@ -4103,7 +4098,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_B(val & 15)));
if (mod == 3) {
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
s->mem_index, MO_UB);
@@ -4113,7 +4108,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_W(val & 7)));
if (mod == 3) {
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
s->mem_index, MO_LEUW);
@@ -4150,7 +4145,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_L(val & 3)));
if (mod == 3) {
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
s->mem_index, MO_LEUL);
@@ -4284,7 +4279,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_rotri_i32(cpu_tmp2_i32, cpu_tmp2_i32, b & 31);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
}
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
default:
@@ -4609,7 +4604,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* xor reg, reg optimisation */
set_cc_op(s, CC_OP_CLR);
tcg_gen_movi_tl(cpu_T[0], 0);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
} else {
opreg = rm;
@@ -4723,7 +4718,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod != 3) {
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
}
break;
case 3: /* neg */
@@ -4731,7 +4726,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod != 3) {
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
}
gen_op_update_neg_cc();
set_cc_op(s, CC_OP_SUBB + ot);
@@ -4744,7 +4739,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(MO_16, R_EAX);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00);
set_cc_op(s, CC_OP_MULB);
@@ -4755,10 +4750,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(MO_16, R_EAX);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
- gen_op_mov_reg_T0(MO_16, R_EDX);
+ gen_op_mov_reg_v(MO_16, R_EDX, cpu_T[0]);
tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
set_cc_op(s, CC_OP_MULW);
break;
@@ -4793,7 +4788,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(MO_16, R_EAX);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
@@ -4805,12 +4800,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(MO_16, R_EAX);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
- gen_op_mov_reg_T0(MO_16, R_EDX);
+ gen_op_mov_reg_v(MO_16, R_EDX, cpu_T[0]);
set_cc_op(s, CC_OP_MULW);
break;
default:
@@ -5029,18 +5024,18 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case MO_64:
gen_op_mov_TN_reg(MO_32, 0, R_EAX);
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(MO_64, R_EAX);
+ gen_op_mov_reg_v(MO_64, R_EAX, cpu_T[0]);
break;
#endif
case MO_32:
gen_op_mov_TN_reg(MO_16, 0, R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(MO_32, R_EAX);
+ gen_op_mov_reg_v(MO_32, R_EAX, cpu_T[0]);
break;
case MO_16:
gen_op_mov_TN_reg(MO_8, 0, R_EAX);
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(MO_16, R_EAX);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
break;
default:
tcg_abort();
@@ -5052,20 +5047,20 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case MO_64:
gen_op_mov_TN_reg(MO_64, 0, R_EAX);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
- gen_op_mov_reg_T0(MO_64, R_EDX);
+ gen_op_mov_reg_v(MO_64, R_EDX, cpu_T[0]);
break;
#endif
case MO_32:
gen_op_mov_TN_reg(MO_32, 0, R_EAX);
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
- gen_op_mov_reg_T0(MO_32, R_EDX);
+ gen_op_mov_reg_v(MO_32, R_EDX, cpu_T[0]);
break;
case MO_16:
gen_op_mov_TN_reg(MO_16, 0, R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
- gen_op_mov_reg_T0(MO_16, R_EDX);
+ gen_op_mov_reg_v(MO_16, R_EDX, cpu_T[0]);
break;
default:
tcg_abort();
@@ -5119,7 +5114,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
}
set_cc_op(s, CC_OP_MULB + ot);
@@ -5136,7 +5131,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_mov_TN_reg(ot, 1, rm);
gen_op_addl_T0_T1();
gen_op_mov_reg_T1(ot, reg);
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
gen_lea_modrm(env, s, modrm);
gen_op_mov_TN_reg(ot, 0, reg);
@@ -5240,7 +5235,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
ot = gen_pop_T0(s);
/* NOTE: order is important for pop %sp */
gen_pop_update(s, ot);
- gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s));
+ gen_op_mov_reg_v(ot, (b & 7) | REX_B(s), cpu_T[0]);
break;
case 0x60: /* pusha */
if (CODE64(s))
@@ -5270,7 +5265,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* NOTE: order is important for pop %sp */
gen_pop_update(s, ot);
rm = (modrm & 7) | REX_B(s);
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
/* NOTE: order is important too for MMU exceptions */
s->popl_esp_hack = 1 << ot;
@@ -5292,16 +5287,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* XXX: exception not precise (ESP is updated before potential exception) */
if (CODE64(s)) {
gen_op_mov_TN_reg(MO_64, 0, R_EBP);
- gen_op_mov_reg_T0(MO_64, R_ESP);
+ gen_op_mov_reg_v(MO_64, R_ESP, cpu_T[0]);
} else if (s->ss32) {
gen_op_mov_TN_reg(MO_32, 0, R_EBP);
- gen_op_mov_reg_T0(MO_32, R_ESP);
+ gen_op_mov_reg_v(MO_32, R_ESP, cpu_T[0]);
} else {
gen_op_mov_TN_reg(MO_16, 0, R_EBP);
- gen_op_mov_reg_T0(MO_16, R_ESP);
+ gen_op_mov_reg_v(MO_16, R_ESP, cpu_T[0]);
}
ot = gen_pop_T0(s);
- gen_op_mov_reg_T0(ot, R_EBP);
+ gen_op_mov_reg_v(ot, R_EBP, cpu_T[0]);
gen_pop_update(s, ot);
break;
case 0x06: /* push es */
@@ -5376,7 +5371,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod != 3) {
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s));
+ gen_op_mov_reg_v(ot, (modrm & 7) | REX_B(s), cpu_T[0]);
}
break;
case 0x8a:
@@ -5386,7 +5381,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
reg = ((modrm >> 3) & 7) | rex_r;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
case 0x8e: /* mov seg, Gv */
modrm = cpu_ldub_code(env, s->pc++);
@@ -5456,11 +5451,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
break;
}
- gen_op_mov_reg_T0(d_ot, reg);
+ gen_op_mov_reg_v(d_ot, reg, cpu_T[0]);
} else {
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, s_ot, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(d_ot, reg);
+ gen_op_mov_reg_v(d_ot, reg, cpu_T[0]);
}
}
break;
@@ -5504,7 +5499,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_add_A0_ds_seg(s);
if ((b & 2) == 0) {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(ot, R_EAX);
+ gen_op_mov_reg_v(ot, R_EAX, cpu_T[0]);
} else {
gen_op_mov_TN_reg(ot, 0, R_EAX);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
@@ -5518,12 +5513,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_extu(s->aflag, cpu_A0);
gen_add_A0_ds_seg(s);
gen_op_ld_v(s, MO_8, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(MO_8, R_EAX);
+ gen_op_mov_reg_v(MO_8, R_EAX, cpu_T[0]);
break;
case 0xb0 ... 0xb7: /* mov R, Ib */
val = insn_get(env, s, MO_8);
tcg_gen_movi_tl(cpu_T[0], val);
- gen_op_mov_reg_T0(MO_8, (b & 7) | REX_B(s));
+ gen_op_mov_reg_v(MO_8, (b & 7) | REX_B(s), cpu_T[0]);
break;
case 0xb8 ... 0xbf: /* mov R, Iv */
#ifdef TARGET_X86_64
@@ -5534,7 +5529,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
s->pc += 8;
reg = (b & 7) | REX_B(s);
tcg_gen_movi_tl(cpu_T[0], tmp);
- gen_op_mov_reg_T0(MO_64, reg);
+ gen_op_mov_reg_v(MO_64, reg, cpu_T[0]);
} else
#endif
{
@@ -5542,7 +5537,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
val = insn_get(env, s, ot);
reg = (b & 7) | REX_B(s);
tcg_gen_movi_tl(cpu_T[0], val);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
}
break;
@@ -5563,7 +5558,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
do_xchg_reg:
gen_op_mov_TN_reg(ot, 0, reg);
gen_op_mov_TN_reg(ot, 1, rm);
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
gen_op_mov_reg_T1(ot, reg);
} else {
gen_lea_modrm(env, s, modrm);
@@ -6166,7 +6161,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0:
gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_mov_reg_T0(MO_16, R_EAX);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
break;
default:
goto illegal_op;
@@ -6630,7 +6625,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_compute_eflags(s);
/* Note: gen_compute_eflags() only gives the condition codes */
tcg_gen_ori_tl(cpu_T[0], cpu_cc_src, 0x02);
- gen_op_mov_reg_T0(MO_8, R_AH);
+ gen_op_mov_reg_v(MO_8, R_AH, cpu_T[0]);
break;
case 0xf5: /* cmc */
gen_compute_eflags(s);
@@ -6737,7 +6732,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod != 3) {
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
}
tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
tcg_gen_movi_tl(cpu_cc_dst, 0);
@@ -6794,7 +6789,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_movcond_tl(TCG_COND_EQ, cpu_T[0], cpu_cc_dst, cpu_tmp0,
cpu_regs[reg], cpu_T[0]);
}
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
/************************/
/* bcd */
@@ -6966,14 +6961,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (dflag == MO_64) {
gen_op_mov_TN_reg(MO_64, 0, reg);
tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(MO_64, reg);
+ gen_op_mov_reg_v(MO_64, reg, cpu_T[0]);
} else
#endif
{
gen_op_mov_TN_reg(MO_32, 0, reg);
tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(MO_32, reg);
+ gen_op_mov_reg_v(MO_32, reg, cpu_T[0]);
}
break;
case 0xd6: /* salc */
@@ -6981,7 +6976,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_compute_eflags_c(s, cpu_T[0]);
tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(MO_8, R_EAX);
+ gen_op_mov_reg_v(MO_8, R_EAX, cpu_T[0]);
break;
case 0xe0: /* loopnz */
case 0xe1: /* loopz */
@@ -7475,11 +7470,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (d_ot == MO_64) {
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
}
- gen_op_mov_reg_T0(d_ot, reg);
+ gen_op_mov_reg_v(d_ot, reg, cpu_T[0]);
} else {
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, MO_32 | MO_SIGN, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(d_ot, reg);
+ gen_op_mov_reg_v(d_ot, reg, cpu_T[0]);
}
} else
#endif
@@ -7617,7 +7612,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_eob(s);
} else {
gen_helper_read_crN(cpu_T[0], cpu_env, tcg_const_i32(reg));
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
}
break;
default:
@@ -7654,7 +7649,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg);
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg]));
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
}
}
break;
@@ -7789,7 +7784,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
gen_helper_popcnt(cpu_T[0], cpu_env, cpu_T[0], tcg_const_i32(ot));
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
set_cc_op(s, CC_OP_EFLAGS);
break;
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 43/49] target-i386: Remove gen_op_mov_reg_T1
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (41 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 42/49] target-i386: Remove gen_op_mov_reg_T0 Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 44/49] target-i386: Remove gen_op_addl_T0_T1 Richard Henderson
` (5 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Replace with its definition.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 31 +++++++++++++------------------
1 file changed, 13 insertions(+), 18 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 8553b71..46bc615 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -358,11 +358,6 @@ static void gen_op_mov_reg_v(TCGMemOp ot, int reg, TCGv t0)
}
}
-static inline void gen_op_mov_reg_T1(TCGMemOp ot, int reg)
-{
- gen_op_mov_reg_v(ot, reg, cpu_T[1]);
-}
-
static inline void gen_op_mov_reg_A0(TCGMemOp size, int reg)
{
gen_op_mov_reg_v(size, reg, cpu_A0);
@@ -2464,7 +2459,7 @@ static void gen_pusha(DisasContext *s)
gen_op_st_v(s, s->dflag, cpu_T[0], cpu_A0);
gen_op_addl_A0_im(1 << s->dflag);
}
- gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
+ gen_op_mov_reg_v(MO_16 + s->ss32, R_ESP, cpu_T[1]);
}
/* NOTE: wrap around in 16 bit not fully handled */
@@ -2486,7 +2481,7 @@ static void gen_popa(DisasContext *s)
}
gen_op_addl_A0_im(1 << s->dflag);
}
- gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
+ gen_op_mov_reg_v(MO_16 + s->ss32, R_ESP, cpu_T[1]);
}
static void gen_enter(DisasContext *s, int esp_addend, int level)
@@ -2510,9 +2505,9 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
tcg_const_i32((ot == MO_64)),
cpu_T[1]);
}
- gen_op_mov_reg_T1(ot, R_EBP);
+ gen_op_mov_reg_v(ot, R_EBP, cpu_T[1]);
tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
- gen_op_mov_reg_T1(MO_64, R_ESP);
+ gen_op_mov_reg_v(MO_64, R_ESP, cpu_T[1]);
} else
#endif
{
@@ -2532,9 +2527,9 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
tcg_const_i32(s->dflag - 1),
cpu_T[1]);
}
- gen_op_mov_reg_T1(ot, R_EBP);
+ gen_op_mov_reg_v(ot, R_EBP, cpu_T[1]);
tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
- gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
+ gen_op_mov_reg_v(MO_16 + s->ss32, R_ESP, cpu_T[1]);
}
}
@@ -5130,7 +5125,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_mov_TN_reg(ot, 0, reg);
gen_op_mov_TN_reg(ot, 1, rm);
gen_op_addl_T0_T1();
- gen_op_mov_reg_T1(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[1]);
gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
gen_lea_modrm(env, s, modrm);
@@ -5138,7 +5133,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
gen_op_addl_T0_T1();
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T1(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[1]);
}
gen_op_update2_cc();
set_cc_op(s, CC_OP_ADDB + ot);
@@ -5559,7 +5554,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_mov_TN_reg(ot, 0, reg);
gen_op_mov_TN_reg(ot, 1, rm);
gen_op_mov_reg_v(ot, rm, cpu_T[0]);
- gen_op_mov_reg_T1(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[1]);
} else {
gen_lea_modrm(env, s, modrm);
gen_op_mov_TN_reg(ot, 0, reg);
@@ -5570,7 +5565,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
if (!(prefixes & PREFIX_LOCK))
gen_helper_unlock();
- gen_op_mov_reg_T1(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[1]);
}
break;
case 0xc4: /* les Gv */
@@ -5603,7 +5598,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
gen_movl_seg_T0(s, op, pc_start - s->cs_base);
/* then put the data */
- gen_op_mov_reg_T1(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[1]);
if (s->is_jmp) {
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
@@ -6311,7 +6306,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_io_start();
tcg_gen_movi_i32(cpu_tmp2_i32, val);
gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
- gen_op_mov_reg_T1(ot, R_EAX);
+ gen_op_mov_reg_v(ot, R_EAX, cpu_T[1]);
if (use_icount) {
gen_io_end();
gen_jmp(s, s->pc - s->cs_base);
@@ -6345,7 +6340,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_io_start();
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
- gen_op_mov_reg_T1(ot, R_EAX);
+ gen_op_mov_reg_v(ot, R_EAX, cpu_T[1]);
if (use_icount) {
gen_io_end();
gen_jmp(s, s->pc - s->cs_base);
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 44/49] target-i386: Remove gen_op_addl_T0_T1
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (42 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 43/49] target-i386: Remove gen_op_mov_reg_T1 Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 45/49] target-i386: Remove gen_op_mov_TN_reg Richard Henderson
` (4 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Replace with its definition.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 11 +++--------
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 46bc615..e7a7ce5 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -408,11 +408,6 @@ static void gen_add_A0_im(DisasContext *s, int val)
gen_op_addl_A0_im(val);
}
-static inline void gen_op_addl_T0_T1(void)
-{
- tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
-}
-
static inline void gen_op_jmp_T0(void)
{
tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, eip));
@@ -1340,7 +1335,7 @@ static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d)
set_cc_op(s1, CC_OP_SBBB + ot);
break;
case OP_ADDL:
- gen_op_addl_T0_T1();
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
gen_op_st_rm_T0_A0(s1, ot, d);
gen_op_update2_cc();
set_cc_op(s1, CC_OP_ADDB + ot);
@@ -5124,14 +5119,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
gen_op_mov_TN_reg(ot, 0, reg);
gen_op_mov_TN_reg(ot, 1, rm);
- gen_op_addl_T0_T1();
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
gen_op_mov_reg_v(ot, reg, cpu_T[1]);
gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
gen_lea_modrm(env, s, modrm);
gen_op_mov_TN_reg(ot, 0, reg);
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
- gen_op_addl_T0_T1();
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_mov_reg_v(ot, reg, cpu_T[1]);
}
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 45/49] target-i386: Remove gen_op_mov_TN_reg
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (43 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 44/49] target-i386: Remove gen_op_addl_T0_T1 Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 46/49] target-i386: Remove gen_op_mov_reg_A0 Richard Henderson
` (3 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Replace with its definition.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 123 +++++++++++++++++++++++-------------------------
1 file changed, 59 insertions(+), 64 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index e7a7ce5..2b6d777 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -373,11 +373,6 @@ static inline void gen_op_mov_v_reg(TCGMemOp ot, TCGv t0, int reg)
}
}
-static inline void gen_op_mov_TN_reg(TCGMemOp ot, int t_index, int reg)
-{
- gen_op_mov_v_reg(ot, cpu_T[t_index], reg);
-}
-
static inline void gen_op_movl_A0_reg(int reg)
{
tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
@@ -1136,7 +1131,7 @@ static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
static inline void gen_stos(DisasContext *s, TCGMemOp ot)
{
- gen_op_mov_TN_reg(MO_32, 0, R_EAX);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], R_EAX);
gen_string_movl_A0_EDI(s);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_movl_T0_Dshift(ot);
@@ -1313,7 +1308,7 @@ static void gen_helper_fp_arith_STN_ST0(int op, int opreg)
static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d)
{
if (d != OR_TMP0) {
- gen_op_mov_TN_reg(ot, 0, d);
+ gen_op_mov_v_reg(ot, cpu_T[0], d);
} else {
gen_op_ld_v(s1, ot, cpu_T[0], cpu_A0);
}
@@ -1379,7 +1374,7 @@ static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d)
static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c)
{
if (d != OR_TMP0) {
- gen_op_mov_TN_reg(ot, 0, d);
+ gen_op_mov_v_reg(ot, cpu_T[0], d);
} else {
gen_op_ld_v(s1, ot, cpu_T[0], cpu_A0);
}
@@ -1449,7 +1444,7 @@ static void gen_shift_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
if (op1 == OR_TMP0) {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, op1);
+ gen_op_mov_v_reg(ot, cpu_T[0], op1);
}
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
@@ -1485,7 +1480,7 @@ static void gen_shift_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,
if (op1 == OR_TMP0)
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
else
- gen_op_mov_TN_reg(ot, 0, op1);
+ gen_op_mov_v_reg(ot, cpu_T[0], op1);
op2 &= mask;
if (op2 != 0) {
@@ -1533,7 +1528,7 @@ static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right)
if (op1 == OR_TMP0) {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, op1);
+ gen_op_mov_v_reg(ot, cpu_T[0], op1);
}
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
@@ -1619,7 +1614,7 @@ static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,
if (op1 == OR_TMP0) {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, op1);
+ gen_op_mov_v_reg(ot, cpu_T[0], op1);
}
op2 &= mask;
@@ -1697,7 +1692,7 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
if (op1 == OR_TMP0)
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
else
- gen_op_mov_TN_reg(ot, 0, op1);
+ gen_op_mov_v_reg(ot, cpu_T[0], op1);
if (is_right) {
switch (ot) {
@@ -1753,7 +1748,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
if (op1 == OR_TMP0) {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, op1);
+ gen_op_mov_v_reg(ot, cpu_T[0], op1);
}
count = tcg_temp_new();
@@ -1827,7 +1822,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
static void gen_shift(DisasContext *s1, int op, TCGMemOp ot, int d, int s)
{
if (s != OR_TMP1)
- gen_op_mov_TN_reg(ot, 1, s);
+ gen_op_mov_v_reg(ot, cpu_T[1], s);
switch(op) {
case OP_ROL:
gen_rot_rm_T1(s1, ot, d, 0);
@@ -2157,10 +2152,10 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
if (mod == 3) {
if (is_store) {
if (reg != OR_TMP0)
- gen_op_mov_TN_reg(ot, 0, reg);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
if (reg != OR_TMP0)
gen_op_mov_reg_v(ot, reg, cpu_T[0]);
}
@@ -2168,7 +2163,7 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
gen_lea_modrm(env, s, modrm);
if (is_store) {
if (reg != OR_TMP0)
- gen_op_mov_TN_reg(ot, 0, reg);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
@@ -2450,7 +2445,7 @@ static void gen_pusha(DisasContext *s)
if (s->addseg)
gen_op_addl_A0_seg(s, R_SS);
for(i = 0;i < 8; i++) {
- gen_op_mov_TN_reg(MO_32, 0, 7 - i);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], 7 - i);
gen_op_st_v(s, s->dflag, cpu_T[0], cpu_A0);
gen_op_addl_A0_im(1 << s->dflag);
}
@@ -2492,7 +2487,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
/* push bp */
- gen_op_mov_TN_reg(MO_32, 0, R_EBP);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], R_EBP);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
if (level) {
/* XXX: must save state */
@@ -2514,7 +2509,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
if (s->addseg)
gen_op_addl_A0_seg(s, R_SS);
/* push bp */
- gen_op_mov_TN_reg(MO_32, 0, R_EBP);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], R_EBP);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
if (level) {
/* XXX: must save state */
@@ -4143,7 +4138,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x20: /* pinsrb */
if (mod == 3) {
- gen_op_mov_TN_reg(MO_32, 0, rm);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], rm);
} else {
tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0,
s->mem_index, MO_UB);
@@ -4599,7 +4594,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
opreg = rm;
}
- gen_op_mov_TN_reg(ot, 1, reg);
+ gen_op_mov_v_reg(ot, cpu_T[1], reg);
gen_op(s, op, ot, opreg);
break;
case 1: /* OP Gv, Ev */
@@ -4613,7 +4608,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else if (op == OP_XORL && rm == reg) {
goto xor_zero;
} else {
- gen_op_mov_TN_reg(ot, 1, rm);
+ gen_op_mov_v_reg(ot, cpu_T[1], rm);
}
gen_op(s, op, ot, reg);
break;
@@ -4693,7 +4688,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
}
switch(op) {
@@ -4724,7 +4719,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 4: /* mul */
switch(ot) {
case MO_8:
- gen_op_mov_TN_reg(MO_8, 1, R_EAX);
+ gen_op_mov_v_reg(MO_8, cpu_T[1], R_EAX);
tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
@@ -4735,7 +4730,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
set_cc_op(s, CC_OP_MULB);
break;
case MO_16:
- gen_op_mov_TN_reg(MO_16, 1, R_EAX);
+ gen_op_mov_v_reg(MO_16, cpu_T[1], R_EAX);
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
@@ -4773,7 +4768,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 5: /* imul */
switch(ot) {
case MO_8:
- gen_op_mov_TN_reg(MO_8, 1, R_EAX);
+ gen_op_mov_v_reg(MO_8, cpu_T[1], R_EAX);
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
@@ -4785,7 +4780,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
set_cc_op(s, CC_OP_MULB);
break;
case MO_16:
- gen_op_mov_TN_reg(MO_16, 1, R_EAX);
+ gen_op_mov_v_reg(MO_16, cpu_T[1], R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
@@ -4902,7 +4897,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (op >= 2 && op != 3 && op != 5)
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
}
switch(op) {
@@ -4992,7 +4987,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
reg = ((modrm >> 3) & 7) | rex_r;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- gen_op_mov_TN_reg(ot, 1, reg);
+ gen_op_mov_v_reg(ot, cpu_T[1], reg);
gen_op_testl_T0_T1_cc();
set_cc_op(s, CC_OP_LOGICB + ot);
break;
@@ -5002,7 +4997,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
ot = mo_b_d(b, dflag);
val = insn_get(env, s, ot);
- gen_op_mov_TN_reg(ot, 0, OR_EAX);
+ gen_op_mov_v_reg(ot, cpu_T[0], OR_EAX);
tcg_gen_movi_tl(cpu_T[1], val);
gen_op_testl_T0_T1_cc();
set_cc_op(s, CC_OP_LOGICB + ot);
@@ -5012,18 +5007,18 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
switch (dflag) {
#ifdef TARGET_X86_64
case MO_64:
- gen_op_mov_TN_reg(MO_32, 0, R_EAX);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], R_EAX);
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_v(MO_64, R_EAX, cpu_T[0]);
break;
#endif
case MO_32:
- gen_op_mov_TN_reg(MO_16, 0, R_EAX);
+ gen_op_mov_v_reg(MO_16, cpu_T[0], R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_v(MO_32, R_EAX, cpu_T[0]);
break;
case MO_16:
- gen_op_mov_TN_reg(MO_8, 0, R_EAX);
+ gen_op_mov_v_reg(MO_8, cpu_T[0], R_EAX);
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
break;
@@ -5035,19 +5030,19 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
switch (dflag) {
#ifdef TARGET_X86_64
case MO_64:
- gen_op_mov_TN_reg(MO_64, 0, R_EAX);
+ gen_op_mov_v_reg(MO_64, cpu_T[0], R_EAX);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
gen_op_mov_reg_v(MO_64, R_EDX, cpu_T[0]);
break;
#endif
case MO_32:
- gen_op_mov_TN_reg(MO_32, 0, R_EAX);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], R_EAX);
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
gen_op_mov_reg_v(MO_32, R_EDX, cpu_T[0]);
break;
case MO_16:
- gen_op_mov_TN_reg(MO_16, 0, R_EAX);
+ gen_op_mov_v_reg(MO_16, cpu_T[0], R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
gen_op_mov_reg_v(MO_16, R_EDX, cpu_T[0]);
@@ -5074,7 +5069,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
val = (int8_t)insn_get(env, s, MO_8);
tcg_gen_movi_tl(cpu_T[1], val);
} else {
- gen_op_mov_TN_reg(ot, 1, reg);
+ gen_op_mov_v_reg(ot, cpu_T[1], reg);
}
switch (ot) {
#ifdef TARGET_X86_64
@@ -5117,14 +5112,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
mod = (modrm >> 6) & 3;
if (mod == 3) {
rm = (modrm & 7) | REX_B(s);
- gen_op_mov_TN_reg(ot, 0, reg);
- gen_op_mov_TN_reg(ot, 1, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
+ gen_op_mov_v_reg(ot, cpu_T[1], rm);
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
gen_op_mov_reg_v(ot, reg, cpu_T[1]);
gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
gen_lea_modrm(env, s, modrm);
- gen_op_mov_TN_reg(ot, 0, reg);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
@@ -5218,7 +5213,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/**************************/
/* push/pop */
case 0x50 ... 0x57: /* push */
- gen_op_mov_TN_reg(MO_32, 0, (b & 7) | REX_B(s));
+ gen_op_mov_v_reg(MO_32, cpu_T[0], (b & 7) | REX_B(s));
gen_push_v(s, cpu_T[0]);
break;
case 0x58 ... 0x5f: /* pop */
@@ -5276,13 +5271,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xc9: /* leave */
/* XXX: exception not precise (ESP is updated before potential exception) */
if (CODE64(s)) {
- gen_op_mov_TN_reg(MO_64, 0, R_EBP);
+ gen_op_mov_v_reg(MO_64, cpu_T[0], R_EBP);
gen_op_mov_reg_v(MO_64, R_ESP, cpu_T[0]);
} else if (s->ss32) {
- gen_op_mov_TN_reg(MO_32, 0, R_EBP);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], R_EBP);
gen_op_mov_reg_v(MO_32, R_ESP, cpu_T[0]);
} else {
- gen_op_mov_TN_reg(MO_16, 0, R_EBP);
+ gen_op_mov_v_reg(MO_16, cpu_T[0], R_EBP);
gen_op_mov_reg_v(MO_16, R_ESP, cpu_T[0]);
}
ot = gen_pop_T0(s);
@@ -5425,7 +5420,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
if (mod == 3) {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
switch (s_ot) {
case MO_UB:
tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
@@ -5491,7 +5486,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
gen_op_mov_reg_v(ot, R_EAX, cpu_T[0]);
} else {
- gen_op_mov_TN_reg(ot, 0, R_EAX);
+ gen_op_mov_v_reg(ot, cpu_T[0], R_EAX);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
}
}
@@ -5546,13 +5541,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod == 3) {
rm = (modrm & 7) | REX_B(s);
do_xchg_reg:
- gen_op_mov_TN_reg(ot, 0, reg);
- gen_op_mov_TN_reg(ot, 1, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
+ gen_op_mov_v_reg(ot, cpu_T[1], rm);
gen_op_mov_reg_v(ot, rm, cpu_T[0]);
gen_op_mov_reg_v(ot, reg, cpu_T[1]);
} else {
gen_lea_modrm(env, s, modrm);
- gen_op_mov_TN_reg(ot, 0, reg);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
/* for xchg, lock is implicit */
if (!(prefixes & PREFIX_LOCK))
gen_helper_lock();
@@ -5672,7 +5667,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
opreg = rm;
}
- gen_op_mov_TN_reg(ot, 1, reg);
+ gen_op_mov_v_reg(ot, cpu_T[1], reg);
if (shift) {
TCGv imm = tcg_const_tl(cpu_ldub_code(env, s->pc++));
@@ -6313,7 +6308,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
val = cpu_ldub_code(env, s->pc++);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes));
- gen_op_mov_TN_reg(ot, 1, R_EAX);
+ gen_op_mov_v_reg(ot, cpu_T[1], R_EAX);
if (use_icount)
gen_io_start();
@@ -6347,7 +6342,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes));
- gen_op_mov_TN_reg(ot, 1, R_EAX);
+ gen_op_mov_v_reg(ot, cpu_T[1], R_EAX);
if (use_icount)
gen_io_start();
@@ -6603,7 +6598,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x9e: /* sahf */
if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
goto illegal_op;
- gen_op_mov_TN_reg(MO_8, 0, R_AH);
+ gen_op_mov_v_reg(MO_8, cpu_T[0], R_AH);
gen_compute_eflags(s);
tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C);
@@ -6651,7 +6646,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
}
/* load shift */
val = cpu_ldub_code(env, s->pc++);
@@ -6677,7 +6672,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
- gen_op_mov_TN_reg(MO_32, 1, reg);
+ gen_op_mov_v_reg(MO_32, cpu_T[1], reg);
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
/* specific case: we need to add a displacement */
@@ -6687,7 +6682,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
}
bt_op:
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1);
@@ -6935,7 +6930,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
mod = (modrm >> 6) & 3;
if (mod == 3)
goto illegal_op;
- gen_op_mov_TN_reg(ot, 0, reg);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
gen_lea_modrm(env, s, modrm);
gen_jmp_im(pc_start - s->cs_base);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
@@ -6949,13 +6944,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
reg = (b & 7) | REX_B(s);
#ifdef TARGET_X86_64
if (dflag == MO_64) {
- gen_op_mov_TN_reg(MO_64, 0, reg);
+ gen_op_mov_v_reg(MO_64, cpu_T[0], reg);
tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_v(MO_64, reg, cpu_T[0]);
} else
#endif
{
- gen_op_mov_TN_reg(MO_32, 0, reg);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], reg);
tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_v(MO_32, reg, cpu_T[0]);
@@ -7455,7 +7450,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
if (mod == 3) {
- gen_op_mov_TN_reg(MO_32, 0, rm);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], rm);
/* sign extend */
if (d_ot == MO_64) {
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
@@ -7595,7 +7590,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
if (b & 2) {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
gen_helper_write_crN(cpu_env, tcg_const_i32(reg),
cpu_T[0]);
gen_jmp_im(s->pc - s->cs_base);
@@ -7632,7 +7627,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
if (b & 2) {
gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
gen_helper_movl_drN_T0(cpu_env, tcg_const_i32(reg), cpu_T[0]);
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 46/49] target-i386: Remove gen_op_mov_reg_A0
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (44 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 45/49] target-i386: Remove gen_op_mov_TN_reg Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 47/49] target-i386: Tidy some size computation Richard Henderson
` (2 subsequent siblings)
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Replace with its definition.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 2b6d777..69c25fd 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -358,11 +358,6 @@ static void gen_op_mov_reg_v(TCGMemOp ot, int reg, TCGv t0)
}
}
-static inline void gen_op_mov_reg_A0(TCGMemOp size, int reg)
-{
- gen_op_mov_reg_v(size, reg, cpu_A0);
-}
-
static inline void gen_op_mov_v_reg(TCGMemOp ot, TCGv t0, int reg)
{
if (ot == MO_8 && byte_reg_is_xH(reg)) {
@@ -5458,7 +5453,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
s->addseg = 0;
gen_lea_modrm(env, s, modrm);
s->addseg = val;
- gen_op_mov_reg_A0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_A0);
break;
case 0xa0: /* mov EAX, Ov */
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 47/49] target-i386: Tidy some size computation
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (45 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 46/49] target-i386: Remove gen_op_mov_reg_A0 Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 48/49] target-i386: Rename gen_op_jmp_T0 to gen_op_jmp_v Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 49/49] target-i386: Tidy ljmp Richard Henderson
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Clean up relics of multiple size domains: - MO_16 + 1 => - 1 + 1 => 0.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 69c25fd..ac78fd2 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -4923,7 +4923,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 3: /* lcall Ev */
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
- gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
+ gen_add_A0_im(s, 1 << ot);
gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
do_lcall:
if (s->pe && !s->vm86) {
@@ -4950,7 +4950,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 5: /* ljmp Ev */
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
- gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
+ gen_add_A0_im(s, 1 << ot);
gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
do_ljmp:
if (s->pe && !s->vm86) {
@@ -5578,7 +5578,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
- gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
+ gen_add_A0_im(s, 1 << ot);
/* load the segment first to handle exceptions properly */
gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
gen_movl_seg_T0(s, op, pc_start - s->cs_base);
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 48/49] target-i386: Rename gen_op_jmp_T0 to gen_op_jmp_v
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (46 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 47/49] target-i386: Tidy some size computation Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
2014-01-07 21:00 ` [Qemu-devel] [PULL 49/49] target-i386: Tidy ljmp Richard Henderson
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
And make the destination argument explicit.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index ac78fd2..ed3e6ce 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -398,9 +398,9 @@ static void gen_add_A0_im(DisasContext *s, int val)
gen_op_addl_A0_im(val);
}
-static inline void gen_op_jmp_T0(void)
+static inline void gen_op_jmp_v(TCGv dest)
{
- tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, eip));
+ tcg_gen_st_tl(dest, cpu_env, offsetof(CPUX86State, eip));
}
static inline void gen_op_add_reg_im(TCGMemOp size, int reg, int32_t val)
@@ -495,7 +495,7 @@ static inline void gen_op_st_rm_T0_A0(DisasContext *s, int idx, int d)
static inline void gen_jmp_im(target_ulong pc)
{
tcg_gen_movi_tl(cpu_tmp0, pc);
- tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, eip));
+ gen_op_jmp_v(cpu_tmp0);
}
static inline void gen_string_movl_A0_ESI(DisasContext *s)
@@ -4918,7 +4918,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
next_eip = s->pc - s->cs_base;
tcg_gen_movi_tl(cpu_T[1], next_eip);
gen_push_v(s, cpu_T[1]);
- gen_op_jmp_T0();
+ gen_op_jmp_v(cpu_T[0]);
gen_eob(s);
break;
case 3: /* lcall Ev */
@@ -4945,7 +4945,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (dflag == MO_16) {
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
}
- gen_op_jmp_T0();
+ gen_op_jmp_v(cpu_T[0]);
gen_eob(s);
break;
case 5: /* ljmp Ev */
@@ -4962,7 +4962,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_op_movl_seg_T0_vm(R_CS);
tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
- gen_op_jmp_T0();
+ gen_op_jmp_v(cpu_T[0]);
}
gen_eob(s);
break;
@@ -6358,14 +6358,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
ot = gen_pop_T0(s);
gen_stack_update(s, val + (1 << ot));
/* Note that gen_pop_T0 uses a zero-extending load. */
- gen_op_jmp_T0();
+ gen_op_jmp_v(cpu_T[0]);
gen_eob(s);
break;
case 0xc3: /* ret */
ot = gen_pop_T0(s);
gen_pop_update(s, ot);
/* Note that gen_pop_T0 uses a zero-extending load. */
- gen_op_jmp_T0();
+ gen_op_jmp_v(cpu_T[0]);
gen_eob(s);
break;
case 0xca: /* lret im */
@@ -6383,7 +6383,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_ld_v(s, dflag, cpu_T[0], cpu_A0);
/* NOTE: keeping EIP updated is not a problem in case of
exception */
- gen_op_jmp_T0();
+ gen_op_jmp_v(cpu_T[0]);
/* pop selector */
gen_op_addl_A0_im(1 << dflag);
gen_op_ld_v(s, dflag, cpu_T[0], cpu_A0);
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread* [Qemu-devel] [PULL 49/49] target-i386: Tidy ljmp
2014-01-07 20:59 [Qemu-devel] [PULL 00/49] target-i386 improvements, part 1 Richard Henderson
` (47 preceding siblings ...)
2014-01-07 21:00 ` [Qemu-devel] [PULL 48/49] target-i386: Rename gen_op_jmp_T0 to gen_op_jmp_v Richard Henderson
@ 2014-01-07 21:00 ` Richard Henderson
48 siblings, 0 replies; 52+ messages in thread
From: Richard Henderson @ 2014-01-07 21:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Remove an unnecessary move opcode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index ed3e6ce..b0f2279 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -4961,8 +4961,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_const_i32(s->pc - pc_start));
} else {
gen_op_movl_seg_T0_vm(R_CS);
- tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
- gen_op_jmp_v(cpu_T[0]);
+ gen_op_jmp_v(cpu_T[1]);
}
gen_eob(s);
break;
--
1.8.4.2
^ permalink raw reply related [flat|nested] 52+ messages in thread